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Clean-up of cpu_arm920t and cpu_arm920t_s3c24x0 code

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This patch re-formats the code in cpu/arm920t and cpu/arm920t/23c24x0 in
preparation for changes to add support for the Embest SBC2440-II Board.

The changes are as follows:
- re-indent the code using Lindent
- make sure register layouts are defined using a C struct
- replace the upper-case typedef'ed C struct names with lower case
  non-typedef'ed ones
- make sure registers are accessed using the proper accessor functions
- run checkpatch.pl and fix any error reports

It assumes the following patch has been applied first:
- [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009

Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have
any s3c2400 or s3c2410 boards but need this patch applying before I can submit
patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets and no
new warnings or errors were found.

Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
kevin.morfitt@fearnside-systems.co.uk 2009-10-10 13:30:22 +09:00 committed by Tom Rix
parent cd85662b34
commit d67cce2dda
7 changed files with 906 additions and 821 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
cpu/arm920t/s3c24x0/interrupts.c
View File

@ -40,7 +40,7 @@
void do_irq (struct pt_regs *pt_regs) void do_irq (struct pt_regs *pt_regs)
{ {
S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT(); struct s3c24x0_interrupt *irq = s3c24x0_get_base_interrupt();
u_int32_t intpnd = irq->INTPND; u_int32_t intpnd = readl(&irq->INTPND);
} }

42
cpu/arm920t/s3c24x0/speed.c
View File

@ -32,6 +32,8 @@
#include <common.h> #include <common.h>
#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
#include <asm/io.h>
#if defined(CONFIG_S3C2400) #if defined(CONFIG_S3C2400)
#include <s3c2400.h> #include <s3c2400.h>
#elif defined(CONFIG_S3C2410) #elif defined(CONFIG_S3C2410)
@ -53,49 +55,51 @@
static ulong get_PLLCLK(int pllreg) static ulong get_PLLCLK(int pllreg)
{ {
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
ulong r, m, p, s; ulong r, m, p, s;
if (pllreg == MPLL) if (pllreg == MPLL)
r = clk_power->MPLLCON; r = readl(&clk_power->MPLLCON);
else if (pllreg == UPLL) else if (pllreg == UPLL)
r = clk_power->UPLLCON; r = readl(&clk_power->UPLLCON);
else else
hang(); hang();
m = ((r & 0xFF000) >> 12) + 8; m = ((r & 0xFF000) >> 12) + 8;
p = ((r & 0x003F0) >> 4) + 2; p = ((r & 0x003F0) >> 4) + 2;
s = r & 0x3; s = r & 0x3;
return((CONFIG_SYS_CLK_FREQ * m) / (p << s)); return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
} }
/* return FCLK frequency */ /* return FCLK frequency */
ulong get_FCLK(void) ulong get_FCLK(void)
{ {
return(get_PLLCLK(MPLL)); return get_PLLCLK(MPLL);
} }
/* return HCLK frequency */ /* return HCLK frequency */
ulong get_HCLK(void) ulong get_HCLK(void)
{ {
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK()); return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK();
} }
/* return PCLK frequency */ /* return PCLK frequency */
ulong get_PCLK(void) ulong get_PCLK(void)
{ {
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK()); return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK();
} }
/* return UCLK frequency */ /* return UCLK frequency */
ulong get_UCLK(void) ulong get_UCLK(void)
{ {
return(get_PLLCLK(UPLL)); return get_PLLCLK(UPLL);
} }
#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ #endif /* defined(CONFIG_S3C2400) ||
defined (CONFIG_S3C2410) ||
defined (CONFIG_TRAB) */

74
cpu/arm920t/s3c24x0/timer.c
View File

@ -30,7 +30,11 @@
*/ */
#include <common.h> #include <common.h>
#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) #if defined(CONFIG_S3C2400) || \
defined(CONFIG_S3C2410) || \
defined(CONFIG_TRAB)
#include <asm/io.h>
#if defined(CONFIG_S3C2400) #if defined(CONFIG_S3C2400)
#include <s3c2400.h> #include <s3c2400.h>
@ -44,37 +48,40 @@ static ulong timer_clk;
/* macro to read the 16 bit timer */ /* macro to read the 16 bit timer */
static inline ulong READ_TIMER(void) static inline ulong READ_TIMER(void)
{ {
S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
return (timers->TCNTO4 & 0xffff); return readl(&timers->TCNTO4) & 0xffff;
} }
static ulong timestamp; static ulong timestamp;
static ulong lastdec; static ulong lastdec;
int timer_init (void) int timer_init(void)
{ {
S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
ulong tmr;
/* use PWM Timer 4 because it has no output */ /* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */ /* prescaler for Timer 4 is 16 */
timers->TCFG0 = 0x0f00; writel(0x0f00, &timers->TCFG0);
if (timer_load_val == 0) if (timer_load_val == 0) {
{
/* /*
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
* (default) and prescaler = 16. Should be 10390 * (default) and prescaler = 16. Should be 10390
* @33.25MHz and 15625 @ 50 MHz * @33.25MHz and 15625 @ 50 MHz
*/ */
timer_load_val = get_PCLK()/(2 * 16 * 100); timer_load_val = get_PCLK() / (2 * 16 * 100);
timer_clk = get_PCLK() / (2 * 16); timer_clk = get_PCLK() / (2 * 16);
} }
/* load value for 10 ms timeout */ /* load value for 10 ms timeout */
lastdec = timers->TCNTB4 = timer_load_val; lastdec = timer_load_val;
writel(timer_load_val, &timers->TCNTB4);
/* auto load, manual update of Timer 4 */ /* auto load, manual update of Timer 4 */
timers->TCON = (timers->TCON & ~0x0700000) | 0x600000; tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
writel(tmr, &timers->TCON);
/* auto load, start Timer 4 */ /* auto load, start Timer 4 */
timers->TCON = (timers->TCON & ~0x0700000) | 0x500000; tmr = (tmr & ~0x0700000) | 0x0500000;
writel(tmr, &timers->TCON);
timestamp = 0; timestamp = 0;
return (0); return (0);
@ -84,22 +91,22 @@ int timer_init (void)
* timer without interrupts * timer without interrupts
*/ */
void reset_timer (void) void reset_timer(void)
{ {
reset_timer_masked (); reset_timer_masked();
} }
ulong get_timer (ulong base) ulong get_timer(ulong base)
{ {
return get_timer_masked () - base; return get_timer_masked() - base;
} }
void set_timer (ulong t) void set_timer(ulong t)
{ {
timestamp = t; timestamp = t;
} }
void udelay (unsigned long usec) void udelay(unsigned long usec)
{ {
ulong tmo; ulong tmo;
ulong start = get_ticks(); ulong start = get_ticks();
@ -112,21 +119,21 @@ void udelay (unsigned long usec)
/*NOP*/; /*NOP*/;
} }
void reset_timer_masked (void) void reset_timer_masked(void)
{ {
/* reset time */ /* reset time */
lastdec = READ_TIMER(); lastdec = READ_TIMER();
timestamp = 0; timestamp = 0;
} }
ulong get_timer_masked (void) ulong get_timer_masked(void)
{ {
ulong tmr = get_ticks(); ulong tmr = get_ticks();
return tmr / (timer_clk / CONFIG_SYS_HZ); return tmr / (timer_clk / CONFIG_SYS_HZ);
} }
void udelay_masked (unsigned long usec) void udelay_masked(unsigned long usec)
{ {
ulong tmo; ulong tmo;
ulong endtime; ulong endtime;
@ -138,7 +145,7 @@ void udelay_masked (unsigned long usec)
tmo /= 1000; tmo /= 1000;
} else { } else {
tmo = usec * (timer_load_val * 100); tmo = usec * (timer_load_val * 100);
tmo /= (1000*1000); tmo /= (1000 * 1000);
} }
endtime = get_ticks() + tmo; endtime = get_ticks() + tmo;
@ -173,7 +180,7 @@ unsigned long long get_ticks(void)
* This function is derived from PowerPC code (timebase clock frequency). * This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second. * On ARM it returns the number of timer ticks per second.
*/ */
ulong get_tbclk (void) ulong get_tbclk(void)
{ {
ulong tbclk; ulong tbclk;
@ -193,30 +200,31 @@ ulong get_tbclk (void)
/* /*
* reset the cpu by setting up the watchdog timer and let him time out * reset the cpu by setting up the watchdog timer and let him time out
*/ */
void reset_cpu (ulong ignored) void reset_cpu(ulong ignored)
{ {
volatile S3C24X0_WATCHDOG * watchdog; struct s3c24x0_watchdog *watchdog;
#ifdef CONFIG_TRAB #ifdef CONFIG_TRAB
extern void disable_vfd (void);
disable_vfd(); disable_vfd();
#endif #endif
watchdog = S3C24X0_GetBase_WATCHDOG(); watchdog = s3c24x0_get_base_watchdog();
/* Disable watchdog */ /* Disable watchdog */
watchdog->WTCON = 0x0000; writel(0x0000, &watchdog->WTCON);
/* Initialize watchdog timer count register */ /* Initialize watchdog timer count register */
watchdog->WTCNT = 0x0001; writel(0x0001, &watchdog->WTCNT);
/* Enable watchdog timer; assert reset at timer timeout */ /* Enable watchdog timer; assert reset at timer timeout */
watchdog->WTCON = 0x0021; writel(0x0021, &watchdog->WTCON);
while(1); /* loop forever and wait for reset to happen */ while (1)
/* loop forever and wait for reset to happen */;
/*NOTREACHED*/ /*NOTREACHED*/
} }
#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ #endif /* defined(CONFIG_S3C2400) ||
defined (CONFIG_S3C2410) ||
defined (CONFIG_TRAB) */

30
cpu/arm920t/s3c24x0/usb.c
View File

@ -32,41 +32,43 @@
# include <s3c2410.h> # include <s3c2410.h>
#endif #endif
int usb_cpu_init (void) #include <asm/io.h>
{
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); int usb_cpu_init(void)
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); {
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
/* /*
* Set the 48 MHz UPLL clocking. Values are taken from * Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf. * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/ */
clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2); writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON);
gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */ /* 1 = use pads related USB for USB host */
writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR);
/* /*
* Enable USB host clock. * Enable USB host clock.
*/ */
clk_power->CLKCON |= (1 << 4); writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
return 0; return 0;
} }
int usb_cpu_stop (void) int usb_cpu_stop(void)
{ {
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
/* may not want to do this */ /* may not want to do this */
clk_power->CLKCON &= ~(1 << 4); writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
return 0; return 0;
} }
int usb_cpu_init_fail (void) int usb_cpu_init_fail(void)
{ {
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
clk_power->CLKCON &= ~(1 << 4); writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
return 0; return 0;
} }
# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */ # endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ #endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */

1305
cpu/arm920t/s3c24x0/usb_ohci.c
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File diff suppressed because it is too large Load Diff

209
cpu/arm920t/s3c24x0/usb_ohci.h
View File

@ -11,22 +11,22 @@
static int cc_to_error[16] = { static int cc_to_error[16] = {
/* mapping of the OHCI CC status to error codes */ /* mapping of the OHCI CC status to error codes */
/* No Error */ 0, /* No Error */ 0,
/* CRC Error */ USB_ST_CRC_ERR, /* CRC Error */ USB_ST_CRC_ERR,
/* Bit Stuff */ USB_ST_BIT_ERR, /* Bit Stuff */ USB_ST_BIT_ERR,
/* Data Togg */ USB_ST_CRC_ERR, /* Data Togg */ USB_ST_CRC_ERR,
/* Stall */ USB_ST_STALLED, /* Stall */ USB_ST_STALLED,
/* DevNotResp */ -1, /* DevNotResp */ -1,
/* PIDCheck */ USB_ST_BIT_ERR, /* PIDCheck */ USB_ST_BIT_ERR,
/* UnExpPID */ USB_ST_BIT_ERR, /* UnExpPID */ USB_ST_BIT_ERR,
/* DataOver */ USB_ST_BUF_ERR, /* DataOver */ USB_ST_BUF_ERR,
/* DataUnder */ USB_ST_BUF_ERR, /* DataUnder */ USB_ST_BUF_ERR,
/* reservd */ -1, /* reservd */ -1,
/* reservd */ -1, /* reservd */ -1,
/* BufferOver */ USB_ST_BUF_ERR, /* BufferOver */ USB_ST_BUF_ERR,
/* BuffUnder */ USB_ST_BUF_ERR, /* BuffUnder */ USB_ST_BUF_ERR,
/* Not Access */ -1, /* Not Access */ -1,
/* Not Access */ -1 /* Not Access */ -1
}; };
/* ED States */ /* ED States */
@ -55,14 +55,13 @@ struct ed {
struct usb_device *usb_dev; struct usb_device *usb_dev;
__u32 unused[3]; __u32 unused[3];
} __attribute__((aligned(16))); } __attribute__ ((aligned(16)));
typedef struct ed ed_t;
/* TD info field */ /* TD info field */
#define TD_CC 0xf0000000 #define TD_CC 0xf0000000
#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) #define TD_CC_GET(td_p) (((td_p) >> 28) & 0x0f)
#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) #define TD_CC_SET(td_p, cc) \
{(td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)}
#define TD_EC 0x0C000000 #define TD_EC 0x0C000000
#define TD_T 0x03000000 #define TD_T 0x03000000
#define TD_T_DATA0 0x02000000 #define TD_T_DATA0 0x02000000
@ -112,8 +111,7 @@ struct td {
__u32 data; __u32 data;
__u32 unused2[2]; __u32 unused2[2];
} __attribute__((aligned(32))); } __attribute__ ((aligned(32)));
typedef struct td td_t;
#define OHCI_ED_SKIP (1 << 14) #define OHCI_ED_SKIP (1 << 14)
@ -123,15 +121,14 @@ typedef struct td td_t;
* told the base address of. It must be 256-byte aligned. * told the base address of. It must be 256-byte aligned.
*/ */
#define NUM_INTS 32 /* part of the OHCI standard */ #define NUM_INTS 32 /* part of the OHCI standard */
struct ohci_hcca { struct ohci_hcca {
__u32 int_table[NUM_INTS]; /* Interrupt ED table */ __u32 int_table[NUM_INTS]; /* Interrupt ED table */
__u16 frame_no; /* current frame number */ __u16 frame_no; /* current frame number */
__u16 pad1; /* set to 0 on each frame_no change */ __u16 pad1; /* set to 0 on each frame_no change */
__u32 done_head; /* info returned for an interrupt */ __u32 done_head; /* info returned for an interrupt */
u8 reserved_for_hc[116]; u8 reserved_for_hc[116];
} __attribute__((aligned(256))); } __attribute__ ((aligned(256)));
/* /*
* Maximum number of root hub ports. * Maximum number of root hub ports.
@ -145,35 +142,34 @@ struct ohci_hcca {
*/ */
struct ohci_regs { struct ohci_regs {
/* control and status registers */ /* control and status registers */
__u32 revision; __u32 revision;
__u32 control; __u32 control;
__u32 cmdstatus; __u32 cmdstatus;
__u32 intrstatus; __u32 intrstatus;
__u32 intrenable; __u32 intrenable;
__u32 intrdisable; __u32 intrdisable;
/* memory pointers */ /* memory pointers */
__u32 hcca; __u32 hcca;
__u32 ed_periodcurrent; __u32 ed_periodcurrent;
__u32 ed_controlhead; __u32 ed_controlhead;
__u32 ed_controlcurrent; __u32 ed_controlcurrent;
__u32 ed_bulkhead; __u32 ed_bulkhead;
__u32 ed_bulkcurrent; __u32 ed_bulkcurrent;
__u32 donehead; __u32 donehead;
/* frame counters */ /* frame counters */
__u32 fminterval; __u32 fminterval;
__u32 fmremaining; __u32 fmremaining;
__u32 fmnumber; __u32 fmnumber;
__u32 periodicstart; __u32 periodicstart;
__u32 lsthresh; __u32 lsthresh;
/* Root hub ports */ /* Root hub ports */
struct ohci_roothub_regs { struct ohci_roothub_regs {
__u32 a; __u32 a;
__u32 b; __u32 b;
__u32 status; __u32 status;
__u32 portstatus[MAX_ROOT_PORTS]; __u32 portstatus[MAX_ROOT_PORTS];
} roothub; } roothub;
} __attribute__((aligned(32))); } __attribute__ ((aligned(32)));
/* OHCI CONTROL AND STATUS REGISTER MASKS */ /* OHCI CONTROL AND STATUS REGISTER MASKS */
@ -221,11 +217,10 @@ struct ohci_regs {
#define OHCI_INTR_OC (1 << 30) /* ownership change */ #define OHCI_INTR_OC (1 << 30) /* ownership change */
#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
/* Virtual Root HUB */ /* Virtual Root HUB */
struct virt_root_hub { struct virt_root_hub {
int devnum; /* Address of Root Hub endpoint */ int devnum; /* Address of Root Hub endpoint */
void *dev; /* was urb */ void *dev; /* was urb */
void *int_addr; void *int_addr;
int send; int send;
int interval; int interval;
@ -288,52 +283,52 @@ struct virt_root_hub {
/* OHCI ROOT HUB REGISTER MASKS */ /* OHCI ROOT HUB REGISTER MASKS */
/* roothub.portstatus [i] bits */ /* roothub.portstatus [i] bits */
#define RH_PS_CCS 0x00000001 /* current connect status */ #define RH_PS_CCS 0x00000001 /* current connect status */
#define RH_PS_PES 0x00000002 /* port enable status*/ #define RH_PS_PES 0x00000002 /* port enable status */
#define RH_PS_PSS 0x00000004 /* port suspend status */ #define RH_PS_PSS 0x00000004 /* port suspend status */
#define RH_PS_POCI 0x00000008 /* port over current indicator */ #define RH_PS_POCI 0x00000008 /* port over current indicator */
#define RH_PS_PRS 0x00000010 /* port reset status */ #define RH_PS_PRS 0x00000010 /* port reset status */
#define RH_PS_PPS 0x00000100 /* port power status */ #define RH_PS_PPS 0x00000100 /* port power status */
#define RH_PS_LSDA 0x00000200 /* low speed device attached */ #define RH_PS_LSDA 0x00000200 /* low speed device attached */
#define RH_PS_CSC 0x00010000 /* connect status change */ #define RH_PS_CSC 0x00010000 /* connect status change */
#define RH_PS_PESC 0x00020000 /* port enable status change */ #define RH_PS_PESC 0x00020000 /* port enable status change */
#define RH_PS_PSSC 0x00040000 /* port suspend status change */ #define RH_PS_PSSC 0x00040000 /* port suspend status change */
#define RH_PS_OCIC 0x00080000 /* over current indicator change */ #define RH_PS_OCIC 0x00080000 /* over current indicator change */
#define RH_PS_PRSC 0x00100000 /* port reset status change */ #define RH_PS_PRSC 0x00100000 /* port reset status change */
/* roothub.status bits */ /* roothub.status bits */
#define RH_HS_LPS 0x00000001 /* local power status */ #define RH_HS_LPS 0x00000001 /* local power status */
#define RH_HS_OCI 0x00000002 /* over current indicator */ #define RH_HS_OCI 0x00000002 /* over current indicator */
#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
#define RH_HS_LPSC 0x00010000 /* local power status change */ #define RH_HS_LPSC 0x00010000 /* local power status change */
#define RH_HS_OCIC 0x00020000 /* over current indicator change */ #define RH_HS_OCIC 0x00020000 /* over current indicator change */
#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
/* roothub.b masks */ /* roothub.b masks */
#define RH_B_DR 0x0000ffff /* device removable flags */ #define RH_B_DR 0x0000ffff /* device removable flags */
#define RH_B_PPCM 0xffff0000 /* port power control mask */ #define RH_B_PPCM 0xffff0000 /* port power control mask */
/* roothub.a masks */ /* roothub.a masks */
#define RH_A_NDP (0xff << 0) /* number of downstream ports */ #define RH_A_NDP (0xff << 0) /* number of downstream ports */
#define RH_A_PSM (1 << 8) /* power switching mode */ #define RH_A_PSM (1 << 8) /* power switching mode */
#define RH_A_NPS (1 << 9) /* no power switching */ #define RH_A_NPS (1 << 9) /* no power switching */
#define RH_A_DT (1 << 10) /* device type (mbz) */ #define RH_A_DT (1 << 10) /* device type (mbz) */
#define RH_A_OCPM (1 << 11) /* over current protection mode */ #define RH_A_OCPM (1 << 11) /* over current protection mode */
#define RH_A_NOCP (1 << 12) /* no over current protection */ #define RH_A_NOCP (1 << 12) /* no over current protection */
#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
/* urb */ /* urb */
#define N_URB_TD 48 #define N_URB_TD 48
typedef struct struct urb_priv {
{ struct ed *ed;
ed_t *ed; __u16 length; /* number of tds associated with this request */
__u16 length; /* number of tds associated with this request */ __u16 td_cnt; /* number of tds already serviced */
__u16 td_cnt; /* number of tds already serviced */ int state;
int state;
unsigned long pipe; unsigned long pipe;
int actual_length; int actual_length;
td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ struct td *td[N_URB_TD]; /* list pointer to all corresponding TDs
} urb_priv_t; associated with this request */
};
#define URB_DEL 1 #define URB_DEL 1
/* /*
@ -344,7 +339,7 @@ typedef struct
*/ */
typedef struct ohci { struct ohci {
struct ohci_hcca *hcca; /* hcca */ struct ohci_hcca *hcca; /* hcca */
/*dma_addr_t hcca_dma; */ /*dma_addr_t hcca_dma; */
@ -355,29 +350,29 @@ typedef struct ohci {
struct ohci_regs *regs; /* OHCI controller's memory */ struct ohci_regs *regs; /* OHCI controller's memory */
ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ struct ed *ed_rm_list[2]; /* lists of all endpoints to be removed */
ed_t *ed_bulktail; /* last endpoint of bulk list */ struct ed *ed_bulktail; /* last endpoint of bulk list */
ed_t *ed_controltail; /* last endpoint of control list */ struct ed *ed_controltail; /* last endpoint of control list */
int intrstatus; int intrstatus;
__u32 hc_control; /* copy of the hc control reg */ __u32 hc_control; /* copy of the hc control reg */
struct usb_device *dev[32]; struct usb_device *dev[32];
struct virt_root_hub rh; struct virt_root_hub rh;
const char *slot_name; const char *slot_name;
} ohci_t; };
#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ #define NUM_EDS 8 /* num of preallocated endpoint descriptors */
struct ohci_device { struct ohci_device {
ed_t ed[NUM_EDS]; struct ed ed[NUM_EDS];
int ed_cnt; int ed_cnt;
}; };
/* hcd */ /* hcd */
/* endpoint */ /* endpoint */
static int ep_link (ohci_t * ohci, ed_t * ed); static int ep_link(struct ohci *ohci, struct ed *ed);
static int ep_unlink (ohci_t * ohci, ed_t * ed); static int ep_unlink(struct ohci *ohci, struct ed *ed);
static ed_t *ep_add_ed (struct usb_device *usb_dev, unsigned long pipe); static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe);
/*-------------------------------------------------------------------------*/ /*-------------------------------------------------------------------------*/
@ -385,13 +380,13 @@ static ed_t *ep_add_ed (struct usb_device *usb_dev, unsigned long pipe);
#define NUM_TD 64 #define NUM_TD 64
/* +1 so we can align the storage */ /* +1 so we can align the storage */
td_t gtd[NUM_TD + 1]; struct td gtd[NUM_TD + 1];
/* pointers to aligned storage */ /* pointers to aligned storage */
td_t *ptd; struct td *ptd;
/* TDs ... */ /* TDs ... */
static inline struct td *td_alloc (struct usb_device *usb_dev) static inline struct td *td_alloc(struct usb_device *usb_dev)
{ {
int i; int i;
struct td *td; struct td *td;
@ -408,7 +403,7 @@ static inline struct td *td_alloc (struct usb_device *usb_dev)
return td; return td;
} }
static inline void ed_free (struct ed *ed) static inline void ed_free(struct ed *ed)
{ {
ed->usb_dev = NULL; ed->usb_dev = NULL;
} }

63
cpu/arm920t/start.S
View File

@ -37,7 +37,7 @@
.globl _start .globl _start
_start: b start_code _start: b start_code
ldr pc, _undefined_instruction ldr pc, _undefined_instruction
ldr pc, _software_interrupt ldr pc, _software_interrupt
ldr pc, _prefetch_abort ldr pc, _prefetch_abort
@ -109,13 +109,13 @@ start_code:
/* /*
* set the cpu to SVC32 mode * set the cpu to SVC32 mode
*/ */
mrs r0,cpsr mrs r0, cpsr
bic r0,r0,#0x1f bic r0, r0, #0x1f
orr r0,r0,#0xd3 orr r0, r0, #0xd3
msr cpsr,r0 msr cpsr, r0
bl coloured_LED_init bl coloured_LED_init
bl red_LED_on bl red_LED_on
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
/* /*
@ -135,19 +135,19 @@ copyex:
/* turn off the watchdog */ /* turn off the watchdog */
# if defined(CONFIG_S3C2400) # if defined(CONFIG_S3C2400)
# define pWTCON 0x15300000 # define pWTCON 0x15300000
# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ # define INTMSK 0x14400008 /* Interupt-Controller base addresses */
# define CLKDIVN 0x14800014 /* clock divisor register */ # define CLKDIVN 0x14800014 /* clock divisor register */
#else #else
# define pWTCON 0x53000000 # define pWTCON 0x53000000
# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ # define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
# define INTSUBMSK 0x4A00001C # define INTSUBMSK 0x4A00001C
# define CLKDIVN 0x4C000014 /* clock divisor register */ # define CLKDIVN 0x4C000014 /* clock divisor register */
# endif # endif
ldr r0, =pWTCON ldr r0, =pWTCON
mov r1, #0x0 mov r1, #0x0
str r1, [r0] str r1, [r0]
/* /*
* mask all IRQs by setting all bits in the INTMR - default * mask all IRQs by setting all bits in the INTMR - default
@ -180,8 +180,8 @@ copyex:
relocate: /* relocate U-Boot to RAM */ relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */ adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */ cmp r0, r1 /* don't reloc during debug */
beq stack_setup beq stack_setup
ldr r2, _armboot_start ldr r2, _armboot_start
ldr r3, _bss_start ldr r3, _bss_start
@ -198,8 +198,8 @@ copy_loop:
/* Set up the stack */ /* Set up the stack */
stack_setup: stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ #ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif #endif
@ -297,8 +297,8 @@ cpu_init_crit:
#define S_R1 4 #define S_R1 4
#define S_R0 0 #define S_R0 0
#define MODE_SVC 0x13 #define MODE_SVC 0x13
#define I_BIT 0x80 #define I_BIT 0x80
/* /*
* use bad_save_user_regs for abort/prefetch/undef/swi ... * use bad_save_user_regs for abort/prefetch/undef/swi ...
@ -311,7 +311,8 @@ cpu_init_crit:
ldr r2, _armboot_start ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE) sub r2, r2, #(CONFIG_STACKSIZE)
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN) sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack /* set base 2 words into abort stack */
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
ldmia r2, {r2 - r3} @ get pc, cpsr ldmia r2, {r2 - r3} @ get pc, cpsr
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
@ -324,12 +325,12 @@ cpu_init_crit:
.macro irq_save_user_regs .macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12 stmia sp, {r0 - r12} @ Calling r0-r12
add r7, sp, #S_PC add r7, sp, #S_PC
stmdb r7, {sp, lr}^ @ Calling SP, LR stmdb r7, {sp, lr}^ @ Calling SP, LR
str lr, [r7, #0] @ Save calling PC str lr, [r7, #0] @ Save calling PC
mrs r6, spsr mrs r6, spsr
str r6, [r7, #4] @ Save CPSR str r6, [r7, #4] @ Save CPSR
str r0, [r7, #8] @ Save OLD_R0 str r0, [r7, #8] @ Save OLD_R0
mov r0, sp mov r0, sp
.endm .endm
@ -338,18 +339,20 @@ cpu_init_crit:
mov r0, r0 mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE add sp, sp, #S_FRAME_SIZE
subs pc, lr, #4 @ return & move spsr_svc into cpsr /* return & move spsr_svc into cpsr */
subs pc, lr, #4
.endm .endm
.macro get_bad_stack .macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE) sub r13, r13, #(CONFIG_STACKSIZE)
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack /* reserve a couple spots in abort stack */
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8)
str lr, [r13] @ save caller lr / spsr str lr, [r13] @ save caller lr / spsr
mrs lr, spsr mrs lr, spsr
str lr, [r13, #4] str lr, [r13, #4]
mov r13, #MODE_SVC @ prepare SVC-Mode mov r13, #MODE_SVC @ prepare SVC-Mode
@ msr spsr_c, r13 @ msr spsr_c, r13