mirror of
https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git
synced 2025-09-14 06:26:13 -04:00
mpc83xx: cosmetic: TQM834x.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Joe Hershberger
Kim Phillips
parent
bb0f5bc92d
commit
df939e1647
@ -66,26 +66,27 @@
|
|||||||
/*
|
/*
|
||||||
* DDR Setup
|
* DDR Setup
|
||||||
*/
|
*/
|
||||||
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
|
/* DDR is system memory*/
|
||||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
#define CONFIG_SYS_DDR_BASE 0x00000000
|
||||||
|
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
||||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
||||||
#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
|
#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
|
||||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
|
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
|
||||||
#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
|
#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
|
||||||
|
|
||||||
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
|
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
|
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x00100000
|
#define CONFIG_SYS_MEMTEST_END 0x00100000
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* FLASH on the Local Bus
|
* FLASH on the Local Bus
|
||||||
*/
|
*/
|
||||||
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
|
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
|
||||||
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
|
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
|
||||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||||
#define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
|
#define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
|
||||||
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
|
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
|
||||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
|
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
|
||||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -93,34 +94,41 @@
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
|
* When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
|
||||||
* banks has to be determined at runtime and stored in a gloabl variable
|
* Flash banks has to be determined at runtime and stored in a gloabl variable
|
||||||
* tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is only
|
* tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
|
||||||
* used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array flash_info, and
|
* only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
|
||||||
* should be made sufficiently large to accomodate the number of banks that
|
* flash_info, and should be made sufficiently large to accomodate the number
|
||||||
* might actually be detected. Since most (all?) Flash related functions use
|
* of banks that might actually be detected. Since most (all?) Flash related
|
||||||
* CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on the board, it is
|
* functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
|
||||||
* defined as tqm834x_num_flash_banks.
|
* the board, it is defined as tqm834x_num_flash_banks.
|
||||||
*/
|
*/
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
|
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
|
||||||
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
|
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
|
||||||
|
|
||||||
/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
|
/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
|
||||||
#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) | \
|
#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
|
||||||
BR_MS_GPCM | BR_PS_32 | BR_V)
|
| BR_MS_GPCM \
|
||||||
|
| BR_PS_32 \
|
||||||
|
| BR_V)
|
||||||
|
|
||||||
/* FLASH timing (0x0000_0c54) */
|
/* FLASH timing (0x0000_0c54) */
|
||||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
|
#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
|
||||||
OR_GPCM_SCY_5 | OR_GPCM_TRLX)
|
| OR_GPCM_ACS_DIV4 \
|
||||||
|
| OR_GPCM_SCY_5 \
|
||||||
|
| OR_GPCM_TRLX)
|
||||||
|
|
||||||
#define CONFIG_SYS_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
|
#define CONFIG_SYS_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
|
||||||
|
|
||||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
|
||||||
|
| CONFIG_SYS_OR_TIMING_FLASH)
|
||||||
|
|
||||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */
|
/* 1 GiB window size (2^(size + 1)) */
|
||||||
|
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D
|
||||||
|
|
||||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
|
/* Window base at flash base */
|
||||||
|
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||||
|
|
||||||
/* disable remaining mappings */
|
/* disable remaining mappings */
|
||||||
#define CONFIG_SYS_BR1_PRELIM 0x00000000
|
#define CONFIG_SYS_BR1_PRELIM 0x00000000
|
||||||
@ -150,14 +158,17 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
|
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
|
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
|
||||||
|
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
#define CONFIG_SYS_GBL_DATA_OFFSET \
|
||||||
|
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB = 3 sect. for Mon */
|
/* Reserve 384 kB = 3 sect. for Mon */
|
||||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
|
#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
|
||||||
|
/* Reserve 512 kB for malloc */
|
||||||
|
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Serial Port
|
* Serial Port
|
||||||
@ -169,7 +180,7 @@
|
|||||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||||
|
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
|
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
||||||
|
|
||||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
|
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
|
||||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
|
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
|
||||||
@ -177,30 +188,30 @@
|
|||||||
/*
|
/*
|
||||||
* I2C
|
* I2C
|
||||||
*/
|
*/
|
||||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||||
#define CONFIG_FSL_I2C
|
#define CONFIG_FSL_I2C
|
||||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed: 400KHz */
|
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed: 400KHz */
|
||||||
#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
|
#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
|
||||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||||
|
|
||||||
/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
|
/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
|
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */
|
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
|
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
|
||||||
#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
|
#define CONFIG_SYS_I2C_MULTI_EEPROMS /* more than one eeprom */
|
||||||
|
|
||||||
/* I2C RTC */
|
/* I2C RTC */
|
||||||
#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
|
#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
|
||||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
||||||
|
|
||||||
/* I2C SYSMON (LM75) */
|
/* I2C SYSMON (LM75) */
|
||||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
|
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
|
||||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
||||||
#define CONFIG_SYS_DTT_MAX_TEMP 70
|
#define CONFIG_SYS_DTT_MAX_TEMP 70
|
||||||
#define CONFIG_SYS_DTT_LOW_TEMP -30
|
#define CONFIG_SYS_DTT_LOW_TEMP -30
|
||||||
#define CONFIG_SYS_DTT_HYSTERESIS 3
|
#define CONFIG_SYS_DTT_HYSTERESIS 3
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TSEC
|
* TSEC
|
||||||
@ -209,9 +220,9 @@
|
|||||||
#define CONFIG_MII
|
#define CONFIG_MII
|
||||||
|
|
||||||
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
|
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
|
||||||
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
|
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
|
||||||
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
|
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
|
||||||
#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
|
#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
|
||||||
|
|
||||||
#if defined(CONFIG_TSEC_ENET)
|
#if defined(CONFIG_TSEC_ENET)
|
||||||
|
|
||||||
@ -219,15 +230,15 @@
|
|||||||
#define CONFIG_TSEC1_NAME "TSEC0"
|
#define CONFIG_TSEC1_NAME "TSEC0"
|
||||||
#define CONFIG_TSEC2 1
|
#define CONFIG_TSEC2 1
|
||||||
#define CONFIG_TSEC2_NAME "TSEC1"
|
#define CONFIG_TSEC2_NAME "TSEC1"
|
||||||
#define TSEC1_PHY_ADDR 2
|
#define TSEC1_PHY_ADDR 2
|
||||||
#define TSEC2_PHY_ADDR 1
|
#define TSEC2_PHY_ADDR 1
|
||||||
#define TSEC1_PHYIDX 0
|
#define TSEC1_PHYIDX 0
|
||||||
#define TSEC2_PHYIDX 0
|
#define TSEC2_PHYIDX 0
|
||||||
#define TSEC1_FLAGS TSEC_GIGABIT
|
#define TSEC1_FLAGS TSEC_GIGABIT
|
||||||
#define TSEC2_FLAGS TSEC_GIGABIT
|
#define TSEC2_FLAGS TSEC_GIGABIT
|
||||||
|
|
||||||
/* Options are: TSEC[0-1] */
|
/* Options are: TSEC[0-1] */
|
||||||
#define CONFIG_ETHPRIME "TSEC0"
|
#define CONFIG_ETHPRIME "TSEC0"
|
||||||
|
|
||||||
#endif /* CONFIG_TSEC_ENET */
|
#endif /* CONFIG_TSEC_ENET */
|
||||||
|
|
||||||
@ -239,19 +250,20 @@
|
|||||||
|
|
||||||
#if defined(CONFIG_PCI)
|
#if defined(CONFIG_PCI)
|
||||||
|
|
||||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||||
|
|
||||||
/* PCI1 host bridge */
|
/* PCI1 host bridge */
|
||||||
#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
|
#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
|
||||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
|
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
|
||||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
|
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
|
||||||
#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
|
#define CONFIG_SYS_PCI1_MMIO_BASE \
|
||||||
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
|
(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
|
||||||
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
|
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
|
||||||
#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
|
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
|
||||||
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
|
#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
|
||||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
|
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
|
||||||
|
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||||
|
|
||||||
#undef CONFIG_EEPRO100
|
#undef CONFIG_EEPRO100
|
||||||
#define CONFIG_EEPRO100
|
#define CONFIG_EEPRO100
|
||||||
@ -270,15 +282,16 @@
|
|||||||
/*
|
/*
|
||||||
* Environment
|
* Environment
|
||||||
*/
|
*/
|
||||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
#define CONFIG_ENV_ADDR \
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
|
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||||
#define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
|
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
|
||||||
|
#define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
|
||||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
|
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
|
||||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||||
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* BOOTP options
|
* BOOTP options
|
||||||
@ -319,30 +332,32 @@
|
|||||||
/*
|
/*
|
||||||
* Miscellaneous configurable options
|
* Miscellaneous configurable options
|
||||||
*/
|
*/
|
||||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||||
|
|
||||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
||||||
|
|
||||||
#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
|
#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
|
||||||
#ifdef CONFIG_SYS_HUSH_PARSER
|
#ifdef CONFIG_SYS_HUSH_PARSER
|
||||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB)
|
#if defined(CONFIG_CMD_KGDB)
|
||||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||||
#else
|
#else
|
||||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
/* Print Buffer Size */
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
|
/* Boot Argument Buffer Size */
|
||||||
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||||
|
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
|
||||||
|
|
||||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||||
|
|
||||||
/* pass open firmware flat tree */
|
/* pass open firmware flat tree */
|
||||||
#define CONFIG_OF_LIBFDT 1
|
#define CONFIG_OF_LIBFDT 1
|
||||||
@ -354,7 +369,8 @@
|
|||||||
* have to be in the first 256 MB of memory, since this is
|
* have to be in the first 256 MB of memory, since this is
|
||||||
* the maximum mapped by the Linux kernel during initialization.
|
* the maximum mapped by the Linux kernel during initialization.
|
||||||
*/
|
*/
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
|
/* Initial Memory map for Linux */
|
||||||
|
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
|
||||||
|
|
||||||
#define CONFIG_SYS_HRCW_LOW (\
|
#define CONFIG_SYS_HRCW_LOW (\
|
||||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||||
@ -375,7 +391,7 @@
|
|||||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||||
HRCWH_TSEC1M_IN_GMII |\
|
HRCWH_TSEC1M_IN_GMII |\
|
||||||
HRCWH_TSEC2M_IN_GMII )
|
HRCWH_TSEC2M_IN_GMII)
|
||||||
#else
|
#else
|
||||||
#define CONFIG_SYS_HRCW_HIGH (\
|
#define CONFIG_SYS_HRCW_HIGH (\
|
||||||
HRCWH_PCI_HOST |\
|
HRCWH_PCI_HOST |\
|
||||||
@ -388,7 +404,7 @@
|
|||||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||||
HRCWH_TSEC1M_IN_GMII |\
|
HRCWH_TSEC1M_IN_GMII |\
|
||||||
HRCWH_TSEC2M_IN_GMII )
|
HRCWH_TSEC2M_IN_GMII)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* System IO Config */
|
/* System IO Config */
|
||||||
@ -404,23 +420,55 @@
|
|||||||
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
|
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
|
||||||
|
|
||||||
/* DDR 0 - 512M */
|
/* DDR 0 - 512M */
|
||||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
|
||||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
| BATL_PP_10 \
|
||||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
|
| BATL_MEMCOHERENCE)
|
||||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
|
||||||
|
| BATU_BL_256M \
|
||||||
|
| BATU_VS \
|
||||||
|
| BATU_VP)
|
||||||
|
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
|
||||||
|
| BATL_PP_10 \
|
||||||
|
| BATL_MEMCOHERENCE)
|
||||||
|
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
|
||||||
|
| BATU_BL_256M \
|
||||||
|
| BATU_VS \
|
||||||
|
| BATU_VP)
|
||||||
|
|
||||||
/* stack in DCACHE @ 512M (no backing mem) */
|
/* stack in DCACHE @ 512M (no backing mem) */
|
||||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
|
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
|
||||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
|
| BATL_PP_10 \
|
||||||
|
| BATL_MEMCOHERENCE)
|
||||||
|
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
|
||||||
|
| BATU_BL_128K \
|
||||||
|
| BATU_VS \
|
||||||
|
| BATU_VP)
|
||||||
|
|
||||||
/* PCI */
|
/* PCI */
|
||||||
#ifdef CONFIG_PCI
|
#ifdef CONFIG_PCI
|
||||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
|
||||||
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
| BATL_PP_10 \
|
||||||
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE)
|
| BATL_MEMCOHERENCE)
|
||||||
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
|
||||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
| BATU_BL_256M \
|
||||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
|
| BATU_VS \
|
||||||
|
| BATU_VP)
|
||||||
|
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
|
||||||
|
| BATL_PP_10 \
|
||||||
|
| BATL_MEMCOHERENCE \
|
||||||
|
| BATL_GUARDEDSTORAGE)
|
||||||
|
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
|
||||||
|
| BATU_BL_256M \
|
||||||
|
| BATU_VS \
|
||||||
|
| BATU_VP)
|
||||||
|
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
|
||||||
|
| BATL_PP_10 \
|
||||||
|
| BATL_CACHEINHIBIT \
|
||||||
|
| BATL_GUARDEDSTORAGE)
|
||||||
|
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
|
||||||
|
| BATU_BL_16M \
|
||||||
|
| BATU_VS \
|
||||||
|
| BATU_VP)
|
||||||
#else
|
#else
|
||||||
#define CONFIG_SYS_IBAT3L (0)
|
#define CONFIG_SYS_IBAT3L (0)
|
||||||
#define CONFIG_SYS_IBAT3U (0)
|
#define CONFIG_SYS_IBAT3U (0)
|
||||||
@ -431,12 +479,24 @@
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* IMMRBAR */
|
/* IMMRBAR */
|
||||||
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
|
||||||
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
|
| BATL_PP_10 \
|
||||||
|
| BATL_CACHEINHIBIT \
|
||||||
|
| BATL_GUARDEDSTORAGE)
|
||||||
|
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
|
||||||
|
| BATU_BL_1M \
|
||||||
|
| BATU_VS \
|
||||||
|
| BATU_VP)
|
||||||
|
|
||||||
/* FLASH */
|
/* FLASH */
|
||||||
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
|
||||||
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
| BATL_PP_10 \
|
||||||
|
| BATL_CACHEINHIBIT \
|
||||||
|
| BATL_GUARDEDSTORAGE)
|
||||||
|
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
|
||||||
|
| BATU_BL_256M \
|
||||||
|
| BATU_VS \
|
||||||
|
| BATU_VP)
|
||||||
|
|
||||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
||||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
||||||
@ -464,10 +524,11 @@
|
|||||||
* Environment Configuration
|
* Environment Configuration
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
|
/* default location for tftp and bootm */
|
||||||
|
#define CONFIG_LOADADDR 400000
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
|
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
|
||||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 115200
|
#define CONFIG_BAUDRATE 115200
|
||||||
|
|
||||||
@ -486,7 +547,7 @@
|
|||||||
"addip=setenv bootargs ${bootargs} " \
|
"addip=setenv bootargs ${bootargs} " \
|
||||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||||
":${hostname}:${netdev}:off panic=1\0" \
|
":${hostname}:${netdev}:off panic=1\0" \
|
||||||
"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
|
||||||
"flash_nfs_old=run nfsargs addip addcons;" \
|
"flash_nfs_old=run nfsargs addip addcons;" \
|
||||||
"bootm ${kernel_addr}\0" \
|
"bootm ${kernel_addr}\0" \
|
||||||
"flash_nfs=run nfsargs addip addcons;" \
|
"flash_nfs=run nfsargs addip addcons;" \
|
||||||
@ -530,8 +591,8 @@
|
|||||||
#define MTDIDS_DEFAULT "nor0=TQM834x-0"
|
#define MTDIDS_DEFAULT "nor0=TQM834x-0"
|
||||||
|
|
||||||
/* default mtd partition table */
|
/* default mtd partition table */
|
||||||
#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env),"\
|
#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \
|
||||||
"1m(kernel),2m(initrd),"\
|
"1m(kernel),2m(initrd)," \
|
||||||
"-(user);"\
|
"-(user);" \
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
#endif /* __CONFIG_H */
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user