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powerpc/mpc85xx: sparse fixes

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fsl_corenet_serdes.c:485:6: warning: symbol '__soc_serdes_init' was not declared. Should it be static?
cpu_init.c:185:6: warning: symbol 'invalidate_cpc' was not declared. Should it be static?
bcsr.c:28:27: warning: non-ANSI function declaration of function 'enable_8568mds_duart'
bcsr.c:39:33: warning: non-ANSI function declaration of function 'enable_8568mds_flash_write'
bcsr.c:46:34: warning: non-ANSI function declaration of function 'disable_8568mds_flash_write'
bcsr.c:53:29: warning: non-ANSI function declaration of function 'enable_8568mds_qe_mdio'
bcsr.c:28:33: warning: non-ANSI function declaration of function 'enable_8569mds_flash_write'
bcsr.c:33:34: warning: non-ANSI function declaration of function 'disable_8569mds_flash_write'
bcsr.c:38:28: warning: non-ANSI function declaration of function 'enable_8569mds_qe_uec'
bcsr.c:63:47: warning: non-ANSI function declaration of function 'disable_8569mds_brd_eeprom_write_protect'
ngpixis.c:245:1: error: directive in argument list
ngpixis.c:247:1: error: directive in argument list

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Kim Phillips 2012-10-29 13:34:38 +00:00 committed by Tom Rini
parent 2ed2e9121f
commit e56143e54f
5 changed files with 18 additions and 14 deletions
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2
arch/powerpc/cpu/mpc85xx/cpu_init.c
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@ -182,7 +182,7 @@ static void enable_cpc(void)
printf("Corenet Platform Cache: %d KB enabled\n", size); printf("Corenet Platform Cache: %d KB enabled\n", size);
} }
void invalidate_cpc(void) static void invalidate_cpc(void)
{ {
int i; int i;
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;

2
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
View File

@ -489,7 +489,7 @@ static void wait_for_rstdone(unsigned int bank)
} }
void __soc_serdes_init(void) static void __soc_serdes_init(void)
{ {
/* Allow for SoC-specific initialization in <SOC>_serdes.c */ /* Allow for SoC-specific initialization in <SOC>_serdes.c */
}; };

12
board/freescale/common/ngpixis.c
View File

@ -237,13 +237,17 @@ int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0; return 0;
} }
U_BOOT_CMD( #ifdef CONFIG_SYS_LONGHELP
pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd, static char pixis_help_text[] =
"Reset the board using the FPGA sequencer",
"- hard reset to default bank\n" "- hard reset to default bank\n"
"pixis_reset altbank - reset to alternate bank\n" "pixis_reset altbank - reset to alternate bank\n"
#ifdef DEBUG #ifdef DEBUG
"pixis_reset dump - display the PIXIS registers\n" "pixis_reset dump - display the PIXIS registers\n"
#endif #endif
"pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n" "pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n";
#endif
U_BOOT_CMD(
pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
"Reset the board using the FPGA sequencer", pixis_help_text
); );

8
board/freescale/mpc8568mds/bcsr.c
View File

@ -25,7 +25,7 @@
#include "bcsr.h" #include "bcsr.h"
void enable_8568mds_duart() void enable_8568mds_duart(void)
{ {
volatile uint* duart_mux = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060); volatile uint* duart_mux = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060);
volatile uint* devices = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070); volatile uint* devices = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070);
@ -36,21 +36,21 @@ void enable_8568mds_duart()
bcsr[5] |= 0x01; /* Enable Duart in BCSR*/ bcsr[5] |= 0x01; /* Enable Duart in BCSR*/
} }
void enable_8568mds_flash_write() void enable_8568mds_flash_write(void)
{ {
volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
bcsr[9] |= 0x01; bcsr[9] |= 0x01;
} }
void disable_8568mds_flash_write() void disable_8568mds_flash_write(void)
{ {
volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
bcsr[9] &= ~(0x01); bcsr[9] &= ~(0x01);
} }
void enable_8568mds_qe_mdio() void enable_8568mds_qe_mdio(void)
{ {
u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);

8
board/freescale/mpc8569mds/bcsr.c
View File

@ -25,17 +25,17 @@
#include "bcsr.h" #include "bcsr.h"
void enable_8569mds_flash_write() void enable_8569mds_flash_write(void)
{ {
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
} }
void disable_8569mds_flash_write() void disable_8569mds_flash_write(void)
{ {
clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
} }
void enable_8569mds_qe_uec() void enable_8569mds_qe_uec(void)
{ {
#if defined(CONFIG_SYS_UCC_RGMII_MODE) #if defined(CONFIG_SYS_UCC_RGMII_MODE)
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
@ -60,7 +60,7 @@ void enable_8569mds_qe_uec()
#endif #endif
} }
void disable_8569mds_brd_eeprom_write_protect() void disable_8569mds_brd_eeprom_write_protect(void)
{ {
clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT); clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
} }