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powerpc/85xx: Convert MPC8569MDS to use common SRIO init code

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Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2011-01-04 18:04:01 -06:00
parent 5f7bbd13a8
commit e5fe96b1ab
2 changed files with 9 additions and 6 deletions
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3
board/freescale/mpc8569mds/law.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright 2009-2010 Freescale Semiconductor, Inc. * Copyright 2009-2011 Freescale Semiconductor, Inc.
* *
* (C) Copyright 2000 * (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -52,7 +52,6 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR), SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
#endif #endif
SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
}; };
int num_law_entries = ARRAY_SIZE(law_table); int num_law_entries = ARRAY_SIZE(law_table);

12
include/configs/MPC8569MDS.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. * Copyright 2009-2011 Freescale Semiconductor, Inc.
* *
* See file CREDITS for list of people who contributed to this * See file CREDITS for list of people who contributed to this
* project. * project.
@ -35,6 +35,9 @@
#define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_PCI 1 /* Disable PCI/PCIE */ #define CONFIG_PCI 1 /* Disable PCI/PCIE */
#define CONFIG_PCIE1 1 /* PCIE controller */ #define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
@ -355,9 +358,10 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#ifdef CONFIG_QE #ifdef CONFIG_QE
/* /*