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MPC85xx: remove broken "mpq101" board
The board stopped building some time ago, and the board maintainer agrtees to drop it - see http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112674 Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Alex Dubov <oakad@yahoo.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Wolfgang Denk
parent
8cb9b23755
commit
e877fabeb9
@ -134,10 +134,6 @@ Wolfgang Denk <wd@denx.de>
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PCIPPC2 MPC750
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PCIPPC2 MPC750
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PCIPPC6 MPC750
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PCIPPC6 MPC750
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Alex Dubov <oakad@yahoo.com>
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mpq101 MPC8548
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Phil Edworthy <phil.edworthy@renesas.com>
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Phil Edworthy <phil.edworthy@renesas.com>
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rsk7264 SH7264
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rsk7264 SH7264
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@ -1,47 +0,0 @@
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#
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# Copyright 2007 Freescale Semiconductor, Inc.
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS-y += $(BOARD).o
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COBJS-y += law.o
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COBJS-y += tlb.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -1,52 +0,0 @@
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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/*
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* LAW(Local Access Window) configuration:
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*
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* 0x0000_0000 0x1fff_ffff DDR SYS_SDRAM_SIZE
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* 0xc000_0000 0xdfff_ffff RapidIO (set elsewhere) 512M
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* 0xe000_0000 0xe000_ffff CCSR (set elsewhere) 1M
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* 0xf000_0000 0xffff_ffff LBC options + FLASH 256M
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*
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* Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*
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* LAW 0 is reserved for boot mapping
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*/
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struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE_LOG - 1,
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LAW_TRGT_IF_DDR_1),
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SET_LAW(CONFIG_SYS_LBC_OPTION_BASE_PHYS, LAW_SIZE_256M,
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LAW_TRGT_IF_LBC)
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@ -1,129 +0,0 @@
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/*
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* (C) Copyright 2011 Alex Dubov <oakad@yahoo.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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/*
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* Initialize Local Bus
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*/
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void local_bus_init(void)
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{
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fsl_lbc_t *lbc = LBC_BASE_ADDR;
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out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
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out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
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}
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int checkboard(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
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puts("Board: Mercury Computer Systems, Inc. MPQ-101 ");
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#ifdef CONFIG_PHYS_64BIT
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puts("(36-bit addrmap) ");
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#endif
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putc('\n');
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/*
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* Initialize local bus.
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*/
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local_bus_init();
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/*
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* Hack TSEC 3 and 4 IO voltages.
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*/
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out_be32(&gur->tsec34ioovcr, 0xe7e0); /* 1110 0111 1110 0xxx */
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out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
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out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
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return 0;
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}
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phys_size_t fixed_sdram(void)
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{
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ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
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const char *p_mode = getenv("perf_mode");
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puts("Initializing....");
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out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
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out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
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out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
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out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
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if (p_mode && !strcmp("performance", p_mode)) {
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out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_PERF);
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out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_PERF);
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out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_PERF);
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out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_PERF);
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out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_PERF);
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} else {
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out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
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out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
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out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
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out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
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out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
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}
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out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
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out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
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asm("sync;isync");
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udelay(500);
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
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asm("sync; isync");
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udelay(500);
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return ((phys_size_t)1) << CONFIG_SYS_SDRAM_SIZE_LOG;
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}
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void pci_init_board(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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/* PCI is disabled */
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out_be32(&gur->devdisr, in_be32(&gur->devdisr)
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| MPC85xx_DEVDISR_PCI1
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| MPC85xx_DEVDISR_PCI2
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| MPC85xx_DEVDISR_PCIE);
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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}
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#endif
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@ -1,82 +0,0 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/mmu.h>
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/*
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* TLB 0: 256M Non-cacheable, guarded
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* 0xf0000000 256M LBC (FLASH included)
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* Out of reset this entry is only 4K.
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE,
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CONFIG_SYS_LBC_OPTION_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_256M, 1),
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/*
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* TLB 1: 1M Non-cacheable, guarded
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* 0xe000_0000 1M CCSRBAR
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_1M, 1),
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#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
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/*
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* TLB 2: 256M Non-cacheable, guarded
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 2, BOOKE_PAGESZ_256M, 1),
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/*
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* TLB 3: 256M Non-cacheable, guarded
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000,
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CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 3, BOOKE_PAGESZ_256M, 1),
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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@ -1,132 +0,0 @@
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/*
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* Copyright 2007-2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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|
||||||
* modify it under the terms of the GNU General Public License as
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|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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||||||
* MA 02111-1307 USA
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*/
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#ifndef RESET_VECTOR_ADDRESS
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|
||||||
#define RESET_VECTOR_ADDRESS 0xfffffffc
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#include <config.h>
|
|
||||||
|
|
||||||
OUTPUT_ARCH(powerpc)
|
|
||||||
|
|
||||||
PHDRS
|
|
||||||
{
|
|
||||||
text PT_LOAD;
|
|
||||||
bss PT_LOAD;
|
|
||||||
}
|
|
||||||
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
/* Read-only sections, merged into text segment: */
|
|
||||||
. = + SIZEOF_HEADERS;
|
|
||||||
.interp : { *(.interp) }
|
|
||||||
/* To simplify mass deployment, environment precedes the monitor text in the
|
|
||||||
* same flash sector.
|
|
||||||
*/
|
|
||||||
.ppcenv CONFIG_ENV_ADDR : { common/env_embedded.o (.ppcenv) }
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
*(.text*)
|
|
||||||
} :text
|
|
||||||
_etext = .;
|
|
||||||
PROVIDE (etext = .);
|
|
||||||
.rodata :
|
|
||||||
{
|
|
||||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
|
||||||
} :text
|
|
||||||
|
|
||||||
/* Read-write section, merged into data segment: */
|
|
||||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
|
||||||
_erotext = .;
|
|
||||||
PROVIDE (erotext = .);
|
|
||||||
.reloc :
|
|
||||||
{
|
|
||||||
_GOT2_TABLE_ = .;
|
|
||||||
KEEP(*(.got2))
|
|
||||||
KEEP(*(.got))
|
|
||||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
|
|
||||||
_FIXUP_TABLE_ = .;
|
|
||||||
KEEP(*(.fixup))
|
|
||||||
}
|
|
||||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
|
|
||||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
|
||||||
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
*(.data*)
|
|
||||||
*(.sdata*)
|
|
||||||
}
|
|
||||||
_edata = .;
|
|
||||||
PROVIDE (edata = .);
|
|
||||||
|
|
||||||
. = .;
|
|
||||||
__u_boot_cmd_start = .;
|
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
|
||||||
__u_boot_cmd_end = .;
|
|
||||||
|
|
||||||
. = .;
|
|
||||||
__start___ex_table = .;
|
|
||||||
__ex_table : { *(__ex_table) }
|
|
||||||
__stop___ex_table = .;
|
|
||||||
|
|
||||||
. = ALIGN(256);
|
|
||||||
__init_begin = .;
|
|
||||||
.text.init : { *(.text.init) }
|
|
||||||
.data.init : { *(.data.init) }
|
|
||||||
. = ALIGN(256);
|
|
||||||
__init_end = .;
|
|
||||||
|
|
||||||
.bootpg RESET_VECTOR_ADDRESS - 0xffc :
|
|
||||||
{
|
|
||||||
arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
|
|
||||||
} :text = 0xffff
|
|
||||||
|
|
||||||
.resetvec RESET_VECTOR_ADDRESS :
|
|
||||||
{
|
|
||||||
KEEP(*(.resetvec))
|
|
||||||
} :text = 0xffff
|
|
||||||
|
|
||||||
. = RESET_VECTOR_ADDRESS + 0x4;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Make sure that the bss segment isn't linked at 0x0, otherwise its
|
|
||||||
* address won't be updated during relocation fixups. Note that
|
|
||||||
* this is a temporary fix. Code to dynamically the fixup the bss
|
|
||||||
* location will be added in the future. When the bss relocation
|
|
||||||
* fixup code is present this workaround should be removed.
|
|
||||||
*/
|
|
||||||
#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
|
|
||||||
. |= 0x10;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
__bss_start = .;
|
|
||||||
.bss (NOLOAD) :
|
|
||||||
{
|
|
||||||
*(.sbss*)
|
|
||||||
*(.bss*)
|
|
||||||
*(COMMON)
|
|
||||||
} :bss
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
__bss_end__ = . ;
|
|
||||||
PROVIDE (end = .);
|
|
||||||
}
|
|
||||||
@ -706,7 +706,6 @@ P5020DS_NAND powerpc mpc85xx corenet_ds freescale -
|
|||||||
P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
|
P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
|
||||||
P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT
|
P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT
|
||||||
P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
|
P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
|
||||||
mpq101 powerpc mpc85xx mpq101 mercury - mpq101
|
|
||||||
stxgp3 powerpc mpc85xx stxgp3 stx
|
stxgp3 powerpc mpc85xx stxgp3 stx
|
||||||
stxssa powerpc mpc85xx stxssa stx - stxssa
|
stxssa powerpc mpc85xx stxssa stx - stxssa
|
||||||
stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M
|
stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M
|
||||||
|
|||||||
@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
|
|||||||
|
|
||||||
Board Arch CPU removed Commit last known maintainer/contact
|
Board Arch CPU removed Commit last known maintainer/contact
|
||||||
=============================================================================
|
=============================================================================
|
||||||
|
mpq101 powerpc mpc85xx - 2011-10-23 Alex Dubov <oakad@yahoo.com>
|
||||||
ixdpg425 arm ixp 0ca8eb7 2011-09-22 Stefan Roese <sr@denx.de>
|
ixdpg425 arm ixp 0ca8eb7 2011-09-22 Stefan Roese <sr@denx.de>
|
||||||
ixdp425 arm ixp 0ca8eb7 2011-09-22 Kyle Harris <kharris@nexus-tech.net>
|
ixdp425 arm ixp 0ca8eb7 2011-09-22 Kyle Harris <kharris@nexus-tech.net>
|
||||||
zylonite arm pxa b66521a 2011-09-05
|
zylonite arm pxa b66521a 2011-09-05
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user