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mpc8308rdb: add support for Spansion SPI flash on header J8

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The SPI pins are routed to header J8 for testing SPI functionality. A
Spansion flash has been wired up and tested on this header.

This patch breaks support for the second TSEC interface, since the GPIO
pin used as a chip select is pinmuxed with some of the TSEC pins.

Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Ira W. Snyder 2012-09-12 14:17:32 -07:00 committed by Kim Phillips
parent f138ca1373
commit ea1ea54e35
2 changed files with 62 additions and 0 deletions
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49
board/freescale/mpc8308rdb/mpc8308rdb.c
View File

@ -24,6 +24,7 @@
#include <common.h> #include <common.h>
#include <hwconfig.h> #include <hwconfig.h>
#include <i2c.h> #include <i2c.h>
#include <spi.h>
#include <libfdt.h> #include <libfdt.h>
#include <fdt_support.h> #include <fdt_support.h>
#include <pci.h> #include <pci.h>
@ -36,6 +37,35 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
/*
* The following are used to control the SPI chip selects for the SPI command.
*/
#ifdef CONFIG_MPC8XXX_SPI
#define SPI_CS_MASK 0x00400000
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
/* active low */
clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
/* inactive high */
setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
}
#endif /* CONFIG_MPC8XXX_SPI */
static u8 read_board_info(void) static u8 read_board_info(void)
{ {
u8 val8; u8 val8;
@ -109,6 +139,25 @@ void pci_init_board(void)
*/ */
int misc_init_r(void) int misc_init_r(void)
{ {
#ifdef CONFIG_MPC8XXX_SPI
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
sysconf83xx_t *sysconf = &immr->sysconf;
/*
* Set proper bits in SICRH to allow SPI on header J8
*
* NOTE: this breaks the TSEC2 interface, attached to the Vitesse
* switch. The pinmux configuration does not have a fine enough
* granularity to support both simultaneously.
*/
clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
puts("WARNING: SPI enabled, TSEC2 support is broken\n");
/* Set header J8 SPI chip select output, disabled */
setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
#endif
#ifdef CONFIG_VSC7385_IMAGE #ifdef CONFIG_VSC7385_IMAGE
if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
CONFIG_VSC7385_IMAGE_SIZE)) { CONFIG_VSC7385_IMAGE_SIZE)) {

13
include/configs/MPC8308RDB.h
View File

@ -340,6 +340,19 @@
#define CONFIG_SYS_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C2_OFFSET 0x3100
/*
* SPI on header J8
*
* WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
* due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
*/
#ifdef CONFIG_MPC8XXX_SPI
#define CONFIG_CMD_SPI
#define CONFIG_USE_SPIFLASH
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#endif
/* /*
* Board info - revision and where boot from * Board info - revision and where boot from