From fed36ac5ae613773b6cd90e61e292c45440e10c8 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 20 Nov 2008 09:57:47 +0100 Subject: [PATCH 001/188] powerpc: 83xx: add support for the kmeter1 board This patch adds support for the kmeter1 board from Keymile, based on a Freescale MPC8360 CPU. - serial console on UART 1 - 256 MB DDR2 RAM - 64 MB NOR Flash - Ethernet RMII Mode over UCC4 - PHY SMSC LAN8700 Signed-off-by: Heiko Schocher Signed-off-by: Kim Phillips --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/keymile/kmeter1/Makefile | 51 ++++ board/keymile/kmeter1/config.mk | 24 ++ board/keymile/kmeter1/kmeter1.c | 153 ++++++++++ doc/README.kmeter1 | 91 ++++++ include/configs/kmeter1.h | 523 ++++++++++++++++++++++++++++++++ 8 files changed, 847 insertions(+) create mode 100644 board/keymile/kmeter1/Makefile create mode 100644 board/keymile/kmeter1/config.mk create mode 100644 board/keymile/kmeter1/kmeter1.c create mode 100644 doc/README.kmeter1 create mode 100644 include/configs/kmeter1.h diff --git a/MAINTAINERS b/MAINTAINERS index 127604b0f..40868310b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -374,6 +374,7 @@ Heiko Schocher ids8247 MPC8247 jupiter MPC5200 + kmeter1 MPC8360 mgcoge MPC8247 mgsuvd MPC852 mucmc52 MPC5200 diff --git a/MAKEALL b/MAKEALL index dbed26805..a4e38ceff 100755 --- a/MAKEALL +++ b/MAKEALL @@ -326,6 +326,7 @@ LIST_8260=" \ ######################################################################### LIST_83xx=" \ + kmeter1 \ MPC8313ERDB_33 \ MPC8313ERDB_NAND_66 \ MPC8315ERDB \ diff --git a/Makefile b/Makefile index fd521b6b5..1fe8f7021 100644 --- a/Makefile +++ b/Makefile @@ -2175,6 +2175,9 @@ TASREG_config : unconfig ## MPC83xx Systems ######################################################################### +kmeter1_config: unconfig + @$(MKCONFIG) kmeter1 ppc mpc83xx kmeter1 keymile + MPC8313ERDB_33_config \ MPC8313ERDB_66_config \ MPC8313ERDB_NAND_33_config \ diff --git a/board/keymile/kmeter1/Makefile b/board/keymile/kmeter1/Makefile new file mode 100644 index 000000000..88b79f3f0 --- /dev/null +++ b/board/keymile/kmeter1/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/keymile/kmeter1/config.mk b/board/keymile/kmeter1/config.mk new file mode 100644 index 000000000..20f298bdb --- /dev/null +++ b/board/keymile/kmeter1/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2008 +# Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xF0000000 diff --git a/board/keymile/kmeter1/kmeter1.c b/board/keymile/kmeter1/kmeter1.c new file mode 100644 index 000000000..f9a59a644 --- /dev/null +++ b/board/keymile/kmeter1/kmeter1.c @@ -0,0 +1,153 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* port pin dir open_drain assign */ + + /* MDIO */ + {0, 1, 3, 0, 2}, /* MDIO */ + {0, 2, 1, 0, 1}, /* MDC */ + + /* UCC4 - UEC */ + {1, 14, 1, 0, 1}, /* TxD0 */ + {1, 15, 1, 0, 1}, /* TxD1 */ + {1, 20, 2, 0, 1}, /* RxD0 */ + {1, 21, 2, 0, 1}, /* RxD1 */ + {1, 18, 1, 0, 1}, /* TX_EN */ + {1, 26, 2, 0, 1}, /* RX_DV */ + {1, 27, 2, 0, 1}, /* RX_ER */ + {1, 24, 2, 0, 1}, /* COL */ + {1, 25, 2, 0, 1}, /* CRS */ + {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */ + {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */ + + /* DUART - UART2 */ + {5, 0, 1, 0, 2}, /* UART2_SOUT */ + {5, 2, 1, 0, 1}, /* UART2_RTS */ + {5, 3, 2, 0, 2}, /* UART2_SIN */ + {5, 1, 2, 0, 3}, /* UART2_CTS */ + + /* END of table */ + {0, 0, 0, 0, QE_IOP_TAB_END}, +}; + +int board_early_init_r (void) +{ + void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8); + u32 val; + + /* + * Because of errata in the UCCs, we have to write to the reserved + * registers to slow the clocks down. + */ + val = in_be32 (reg); + /* UCC1 */ + val |= 0x00003000; + /* UCC2 */ + val |= 0x0c000000; + out_be32 (reg, val); + /* enable the PHY on the PIGGY */ + setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01); + + return 0; +} + +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CONFIG_SYS_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { + if (ddr_size & 1) + return -1; + } + + im->sysconf.ddrlaw[0].ar = + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); + + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; + udelay (200); + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + return msize; +} + +phys_size_t initdram (int board_type) +{ +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) + extern void ddr_enable_ecc (unsigned int dram_size); +#endif + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + msize = fixed_sdram (); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) + /* + * Initialize DDR ECC byte + */ + ddr_enable_ecc (msize * 1024 * 1024); +#endif + + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + +int checkboard (void) +{ + puts ("Board: Keymile kmeter1\n"); + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup (void *blob, bd_t *bd) +{ + ft_cpu_setup (blob, bd); +} +#endif diff --git a/doc/README.kmeter1 b/doc/README.kmeter1 new file mode 100644 index 000000000..44ebb7a78 --- /dev/null +++ b/doc/README.kmeter1 @@ -0,0 +1,91 @@ +Keymile kmeter1 Board +----------------------------------------- +1. Alternative Boot EEPROM + + Upon the kmeter1 startup the I2C_1 controller is used to fetch the boot + configuration from a serial EEPROM. During the development and debugging + phase it might be helpful to apply an alternative boot configuration in + a simple way. Therefore it is an alternative boot eeprom on the PIGGY, + which can be activated by setting the "ST" jumper on the PIGGY board. + +2. Memory Map + + BaseAddr PortSz Size Device + ----------- ------ ----- ------ + 0x0000_0000 64 bit 256MB DDR + 0x8000_0000 8 bit 256KB GPIO/PIGGY on CS1 + 0xa000_0000 8 bit 256MB PAXE on CS3 + 0xe000_0000 2MB Int Mem Reg Space + 0xf000_0000 16 bit 256MB FLASH on CS0 + + + DDR-SDRAM: + The current realization is made with four 16-bits memory devices. + Mounting options have been foreseen for device architectures from + 4Mx16 to 512Mx16. The kmeter1 is equipped with four 32Mx16 devices + thus resulting in a total capacity of 256MBytes. + +3. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make kmeter1_config + make + +4. Downloading and Flashing Images + +4.0 Download over serial line using Kermit: + + loadb + [Drop to kermit: + ^\c + send + c + ] + + + Or via tftp: + + tftp 10000 u-boot.bin + => run load + Using FSL UEC0 device + TFTP from server 192.168.1.1; our IP address is 192.168.205.4 + Filename '/tftpboot/kmeter1/u-boot.bin'. + Load address: 0x200000 + Loading: ############## + done + Bytes transferred = 204204 (31dac hex) + => + +4.1 Reflash U-boot Image using U-boot + + => run update + ..... done + Un-Protected 5 sectors + + ..... done + Erased 5 sectors + Copy to Flash... done + ..... done + Protected 5 sectors + Total of 204204 bytes were the same + Saving Environment to Flash... + . done + Un-Protected 1 sectors + . done + Un-Protected 1 sectors + Erasing Flash... + . done + Erased 1 sectors + Writing to Flash... done + . done + Protected 1 sectors + . done + Protected 1 sectors + => + +5. Notes + 1) The console baudrate for kmeter1 is 115200bps. diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h new file mode 100644 index 000000000..e105c3bd2 --- /dev/null +++ b/include/configs/kmeter1.h @@ -0,0 +1,523 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ +#define CONFIG_KMETER1 1 /* KMETER1 board specific */ + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_CSB_TO_CLKIN_4X1 | \ + HRCWL_CORE_TO_CSB_2X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X6 ) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_NORMAL | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LDP_CLEAR ) + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x00000006 +#define CONFIG_SYS_SICRL 0x00000000 + +#define CONFIG_BOARD_EARLY_INIT_R + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +#undef CONFIG_DDR_ECC + +/* + * DDRCDR - DDR Control Driver Register + */ + +#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS) + +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_SREN) +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x100 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x406 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_MODE 0x04440242 +#define CONFIG_SYS_DDR_MODE2 0x00800000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_40) | \ + ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \ + ( 1 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + ( 2 << TIMING_CFG1_WRREC_SHIFT) | \ + ( 2 << TIMING_CFG1_REFREC_SHIFT) | \ + ( 2 << TIMING_CFG1_ACTTORW_SHIFT) | \ + ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + ( 2 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((5 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (4 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +/* + * Memory test + */ +#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */ +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x00F00000 + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 +#define CONFIG_SYS_FLASH_BASE_1 0xF2000000 +#define CONFIG_SYS_PIGGY_BASE 0x80000000 +#define CONFIG_SYS_PAXE_BASE 0xA0000000 +#define CONFIG_SYS_PAXE_SIZE 256 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 256KB GPIO/PIGGY + * 3 Local GPCM 8 bit 256MB PAXE + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */ + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 } + +#undef CONFIG_SYS_FLASH_CHECKSUM + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWAR1_PRELIM 0x80000011 /* 256KB window size */ + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \ + (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (0xfffc0000 | /* 256KB */ \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +/* + * PAXE on the local bus CS3 + */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001b /* 256MB window size */ + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \ + (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ + BR_V) +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200,} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#undef CONFIG_PCI /* No PCI */ + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "FSL UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_RAMBOOT */ +#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ +#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_RAMBOOT */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#endif + +#if defined(CFG_RAMBOOT) +#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_LOADS +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +#define CONFIG_SYS_HZ 1000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_256K | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* PAXE: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256K | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else /* CONFIG_PCI */ +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U +#endif /* CONFIG_PCI */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=ttyS0,${baudrate}\0" \ + "fdt_addr=f0080000\0" \ + "kernel_addr=f00a0000\0" \ + "ramdisk_addr=f03a0000\0" \ + "kernel_addr_r=400000\0" \ + "fdt_addr_r=800000\0" \ + "ramdisk_addr_r=810000\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${boot_file}; " \ + "tftp ${fdt_addr_r} ${fdt_file}; " \ + "run nfsargs addip addtty;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "fdt_file=/tftpboot/kmeter1/kmeter1.dtb\0" \ + "boot_file=/tftpboot/kmeter1/uImage\0" \ + "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0" \ + "u-boot=/tftpboot/kmeter1/u-boot.bin\0" \ + "loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \ + "load=tftp $loadaddr ${u-boot}\0" \ + "update=protect off " MK_STR(TEXT_BASE) " +$filesize;" \ + "erase " MK_STR(TEXT_BASE) " +$filesize;" \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \ + "protect on " MK_STR(TEXT_BASE) " +$filesize;" \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \ + "setenv filesize;saveenv\0" \ + "upd=run load update\0" \ + "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0" \ + "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \ + "loadkernel=tftp ${kernel_addr_r} ${boot_file}\0" \ + "unlock=yes\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#endif /* __CONFIG_H */ From 9482a8e3d6ac766d90e5059dce777b1e4c868a30 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 21 Nov 2008 08:29:40 +0100 Subject: [PATCH 002/188] powerpc: keymile: Add a check for the PIGGY debug board Check the presence of the PIGGY on the keymile boards mgcoge, mgsuvd and kmeter1. If the PIGGY is not present, dont register this Ethernet device. Signed-off-by: Heiko Schocher Signed-off-by: Kim Phillips --- board/keymile/common/common.c | 23 +++++++++++++++++++++-- board/keymile/common/common.h | 20 ++++++++++++++++++++ board/keymile/kmeter1/Makefile | 6 ++++-- board/keymile/kmeter1/kmeter1.c | 7 ++++++- board/keymile/mgcoge/mgcoge.c | 10 +++++++--- board/keymile/mgsuvd/mgsuvd.c | 8 ++++++-- include/configs/kmeter1.h | 9 +++++++++ include/configs/mgcoge.h | 10 ++++++++++ include/configs/mgsuvd.h | 9 +++++++++ 9 files changed, 92 insertions(+), 10 deletions(-) create mode 100644 board/keymile/common/common.h diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index a4cf24cf7..133895081 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -22,10 +22,14 @@ */ #include +#if defined(CONFIG_MGCOGE) #include +#endif #include #include #include +#include +#include #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) #include @@ -33,8 +37,6 @@ #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) #include -#endif -#include extern int i2c_soft_read_pin (void); @@ -495,6 +497,7 @@ void i2c_init_board(void) #endif } #endif +#endif #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) int fdt_set_node_and_value (void *blob, @@ -521,3 +524,19 @@ int fdt_set_node_and_value (void *blob, return ret; } #endif + +int ethernet_present (void) +{ + return (in_8((u8 *)CONFIG_SYS_PIGGY_BASE + CONFIG_SYS_SLOT_ID_OFF) & 0x80); +} + +int board_eth_init (bd_t *bis) +{ +#ifdef CONFIG_KEYMILE_HDLC_ENET + (void)keymile_hdlc_enet_initialize (bis); +#endif + if (ethernet_present ()) { + return -1; + } + return 0; +} diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h new file mode 100644 index 000000000..d3d681424 --- /dev/null +++ b/board/keymile/common/common.h @@ -0,0 +1,20 @@ +/* + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __KEYMILE_COMMON_H +#define __KEYMILE_COMMON_H + +int ethernet_present (void); +int ivm_read_eeprom (void); + +#ifdef CONFIG_KEYMILE_HDLC_ENET +int keymile_hdlc_enet_initialize (bd_t *bis); +#endif +#endif /* __KEYMILE_COMMON_H */ diff --git a/board/keymile/kmeter1/Makefile b/board/keymile/kmeter1/Makefile index 88b79f3f0..12a1518ff 100644 --- a/board/keymile/kmeter1/Makefile +++ b/board/keymile/kmeter1/Makefile @@ -22,12 +22,14 @@ # include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif LIB = $(obj)lib$(BOARD).a -COBJS-y += $(BOARD).o +COBJS += $(BOARD).o ../common/common.o -COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/keymile/kmeter1/kmeter1.c b/board/keymile/kmeter1/kmeter1.c index f9a59a644..f04a57a9c 100644 --- a/board/keymile/kmeter1/kmeter1.c +++ b/board/keymile/kmeter1/kmeter1.c @@ -27,6 +27,8 @@ #include #include +#include "../common/common.h" + const qe_iop_conf_t qe_iop_conf_tab[] = { /* port pin dir open_drain assign */ @@ -141,7 +143,10 @@ phys_size_t initdram (int board_type) int checkboard (void) { - puts ("Board: Keymile kmeter1\n"); + puts ("Board: Keymile kmeter1"); + if (ethernet_present ()) + puts (" with PIGGY."); + puts ("\n"); return 0; } diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c index 3683417f5..5c5073964 100644 --- a/board/keymile/mgcoge/mgcoge.c +++ b/board/keymile/mgcoge/mgcoge.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) @@ -35,7 +36,8 @@ #include #endif -extern int ivm_read_eeprom (void); +#include "../common/common.h" + /* * I/O Port configuration table * @@ -285,8 +287,10 @@ phys_size_t initdram (int board_type) int checkboard(void) { - puts ("Board: mgcoge\n"); - + puts ("Board: Keymile mgcoge"); + if (ethernet_present ()) + puts (" with PIGGY."); + puts ("\n"); return 0; } diff --git a/board/keymile/mgsuvd/mgsuvd.c b/board/keymile/mgsuvd/mgsuvd.c index 3726acf4a..02baf622e 100644 --- a/board/keymile/mgsuvd/mgsuvd.c +++ b/board/keymile/mgsuvd/mgsuvd.c @@ -22,13 +22,14 @@ */ #include #include +#include #include #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) #include #endif -extern int ivm_read_eeprom (void); +#include "../common/common.h" DECLARE_GLOBAL_DATA_PTR; @@ -60,7 +61,10 @@ const uint sdram_table[] = int checkboard (void) { - puts ("Board: Keymile mgsuvd\n"); + puts ("Board: Keymile mgsuvd"); + if (ethernet_present ()) + puts (" with PIGGY."); + puts ("\n"); return (0); } diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index e105c3bd2..7a63a4189 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -313,6 +313,15 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * How to get access to the slot ID. Put this here to make it easy + * to modify in a centralized location. This is used in the HDLC + * driver to set the MAC. +*/ +#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE +#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ +#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ + /* * BOOTP options */ diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index dc9b311d4..31428ea09 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -400,4 +400,14 @@ #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" +/* + * How to get access to the slot ID. Put this here to make it easy + * to modify in a centralized location. This is used in the HDLC + * driver to set the MAC. +*/ +#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE +#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ +#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ + + #endif /* __CONFIG_H */ diff --git a/include/configs/mgsuvd.h b/include/configs/mgsuvd.h index fca2e5513..b862130ae 100644 --- a/include/configs/mgsuvd.h +++ b/include/configs/mgsuvd.h @@ -211,6 +211,15 @@ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +/* + * How to get access to the slot ID. Put this here to make it easy + * to modify in a centralized location. This is used in the HDLC + * driver to set the MAC. +*/ +#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE +#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ +#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ + /*----------------------------------------------------------------------- * Cache Configuration */ From 633639587e3596f0dbf5e6247dd3faf80b1d9063 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 20 Nov 2008 09:59:09 +0100 Subject: [PATCH 003/188] powerpc, keymile boards: extract identical config options This patch extracts the identical config options for the keymile boards mgcoge, mgsuvd and kmeter1 in a new common config file keymile-common.h. Signed-off-by: Heiko Schocher Signed-off-by: Kim Phillips --- include/configs/keymile-common.h | 113 +++++++++++++++++++++++++++++++ include/configs/kmeter1.h | 81 +--------------------- include/configs/mgcoge.h | 61 +---------------- include/configs/mgsuvd.h | 81 +--------------------- 4 files changed, 120 insertions(+), 216 deletions(-) create mode 100644 include/configs/keymile-common.h diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h new file mode 100644 index 000000000..d70bc4808 --- /dev/null +++ b/include/configs/keymile-common.h @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_KEYMILE_H +#define __CONFIG_KEYMILE_H + +/* Do boardspecific init for all boards */ +#define CONFIG_BOARD_EARLY_INIT_R 1 + +#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD) +#define CONFIG_BOOTCOUNT_LIMIT +#endif + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + +/* should go away, if kmeter I2C support is enabled */ +#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD) +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#endif + +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ + +#define CONFIG_BOOTCOMMAND "run net_nfs" +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +/* should go away, if kmeter I2C support is enabled */ +#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD) +#define CONFIG_HUSH_INIT_VAR 1 +#endif + +#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */ +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ + +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * How to get access to the slot ID. Put this here to make it easy + * to modify in a centralized location. This is used in the HDLC + * driver to set the MAC. +*/ +#define CONFIG_CHECK_ETHERNET_PRESENT 1 +#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE +#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ +#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +#endif /* __CONFIG_KEYMILE_H */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 7a63a4189..25b1c172e 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -29,6 +29,9 @@ #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ #define CONFIG_KMETER1 1 /* KMETER1 board specific */ +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" + /* * System Clock Setup */ @@ -60,8 +63,6 @@ #define CONFIG_SYS_SICRH 0x00000006 #define CONFIG_SYS_SICRL 0x00000000 -#define CONFIG_BOARD_EARLY_INIT_R - /* * IMMR new address */ @@ -134,13 +135,6 @@ #define CONFIG_SYS_DDR_TIMING_3 0x00000000 -/* - * Memory test - */ -#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00F00000 - /* * The reserved memory */ @@ -249,9 +243,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200,} - #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) @@ -269,7 +260,6 @@ #ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI 1 #endif - /* * QE UEC ethernet configuration */ @@ -310,37 +300,6 @@ #define CONFIG_ENV_SIZE 0x2000 #endif /* CFG_RAMBOOT */ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * How to get access to the slot ID. Put this here to make it easy - * to modify in a centralized location. This is used in the HDLC - * driver to set the MAC. -*/ -#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE -#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ -#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING - #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI #endif @@ -350,28 +309,6 @@ #undef CONFIG_CMD_LOADS #endif -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#define CONFIG_SYS_HZ 1000 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is @@ -464,11 +401,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - /* * Environment Configuration */ @@ -478,11 +410,6 @@ #define CONFIG_HAS_ETH0 #endif -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "rootpath=/opt/eldk/ppc_82xx\0" \ @@ -527,6 +454,4 @@ "unlock=yes\0" \ "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - #endif /* __CONFIG_H */ diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 31428ea09..233bee002 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -35,8 +35,8 @@ #define CONFIG_CPM2 1 /* Has a CPM2 */ -/* Do boardspecific init */ -#define CONFIG_BOARD_EARLY_INIT_R 1 +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" /* * Select serial console configuration @@ -74,23 +74,6 @@ #define CONFIG_8260_CLKIN 66000000 /* in Hz */ #endif -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTCOUNT_LIMIT - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DTT -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING - /* * Default environment settings */ @@ -124,36 +107,6 @@ "run ramargs addip; " \ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ "" -#define CONFIG_BOOTCOMMAND "run net_nfs" -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_HUSH_INIT_VAR 1 -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_FLASH_BASE 0xFE000000 @@ -400,14 +353,4 @@ #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" -/* - * How to get access to the slot ID. Put this here to make it easy - * to modify in a centralized location. This is used in the HDLC - * driver to set the MAC. -*/ -#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE -#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ -#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ - - #endif /* __CONFIG_H */ diff --git a/include/configs/mgsuvd.h b/include/configs/mgsuvd.h index b862130ae..f53b6d382 100644 --- a/include/configs/mgsuvd.h +++ b/include/configs/mgsuvd.h @@ -36,8 +36,8 @@ #define CONFIG_MPC866 1 /* This is a MPC866 CPU */ #define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */ -/* Do boardspecific init */ -#define CONFIG_BOARD_EARLY_INIT_R 1 +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" #define CONFIG_8xx_GCLK_FREQ 66000000 @@ -45,22 +45,13 @@ #define CONFIG_SYS_SMC_DPMEM_OFFSET 0x1fc0 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT #define CONFIG_SYS_CPM_BOOTCOUNT_ADDR 0x1eb0 /* In case of SMC relocation, the * default value is not working */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - #define CONFIG_PREBOOT "echo;" \ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ "echo" -#undef CONFIG_BOOTARGS - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \ @@ -88,70 +79,11 @@ "cp.b 200000 f0000000 ${filesize};" \ "protect on f0000000 +${filesize}\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ #define CONFIG_TIMESTAMP /* but print image timestmps */ -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_HUSH_INIT_VAR 1 -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) @@ -211,15 +143,6 @@ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -/* - * How to get access to the slot ID. Put this here to make it easy - * to modify in a centralized location. This is used in the HDLC - * driver to set the MAC. -*/ -#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE -#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ -#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ - /*----------------------------------------------------------------------- * Cache Configuration */ From 9def12cae33d2d3ea2dd56b197fd3dfb3ad60bf4 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 27 Nov 2008 14:05:15 +0100 Subject: [PATCH 004/188] MTD: Fix problem based on non-working relocation (list head mtd_partitions) Don't use LIST_HEAD() but initialize the struct via INIT_LIST_HEAD() upon first call of add_mtd_partitions(). Otherwise this won't work on platforms where the relocation is broken (like MIPS or PPC). Signed-off-by: Stefan Roese --- drivers/mtd/mtdpart.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index 9a3bf6f39..f010f5e3a 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -20,7 +20,7 @@ #include /* Our partition linked list */ -static LIST_HEAD(mtd_partitions); +struct list_head mtd_partitions; /* Our partition node structure */ struct mtd_part { @@ -349,6 +349,14 @@ int add_mtd_partitions(struct mtd_info *master, u_int32_t cur_offset = 0; int i; + /* + * Need to init the list here, since LIST_INIT() does not + * work on platforms where relocation has problems (like MIPS + * & PPC). + */ + if (mtd_partitions.next == NULL) + INIT_LIST_HEAD(&mtd_partitions); + printk (KERN_NOTICE "Creating %d MTD partitions on \"%s\":\n", nbparts, master->name); for (i = 0; i < nbparts; i++) { From 2ee951ba2ac9874d2a93d52e7a187d3184be937e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 27 Nov 2008 14:07:09 +0100 Subject: [PATCH 005/188] UBI: Enable re-initializing of the "ubi part" command With this patch now, the user can call "ubi part" multiple times to re-connect the UBI device to another MTD partition. Signed-off-by: Stefan Roese --- common/cmd_ubi.c | 11 +++++++++++ drivers/mtd/ubi/build.c | 1 + include/ubi_uboot.h | 1 + 3 files changed, 13 insertions(+) diff --git a/common/cmd_ubi.c b/common/cmd_ubi.c index 844676587..495d71ec0 100644 --- a/common/cmd_ubi.c +++ b/common/cmd_ubi.c @@ -31,6 +31,7 @@ /* Private own data */ static struct ubi_device *ubi; static char buffer[80]; +static int ubi_initialized; struct selected_dev { char dev_name[32]; /* NAND/OneNAND etc */ @@ -428,6 +429,8 @@ static int ubi_dev_scan(struct mtd_info *info, char *ubidev) return err; } + ubi_initialized = 1; + return 0; } @@ -463,6 +466,14 @@ static int do_ubi(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* todo: get dev number for NAND... */ ubi_dev.nr = 0; + /* + * Call ubi_exit() before re-initializing the UBI subsystem + */ + if (ubi_initialized) { + ubi_exit(); + del_mtd_partitions(ubi_dev.mtd_info); + } + /* * Check for nand|onenand selection */ diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index 17cabb2ae..bdf75c98a 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -1059,6 +1059,7 @@ void __exit ubi_exit(void) misc_deregister(&ubi_ctrl_cdev); class_remove_file(ubi_class, &ubi_version); class_destroy(ubi_class); + mtd_devs = 0; } module_exit(ubi_exit); diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h index 295f2c0ff..095dfc1b2 100644 --- a/include/ubi_uboot.h +++ b/include/ubi_uboot.h @@ -211,6 +211,7 @@ static inline long IS_ERR(const void *ptr) /* functions */ extern int ubi_mtd_param_parse(const char *val, struct kernel_param *kp); extern int ubi_init(void); +extern void ubi_exit(void); extern struct ubi_device *ubi_devices[]; From 2d2e05727fe4013f807ffa814dff0e75259a1db4 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 2 Dec 2008 10:53:47 +0100 Subject: [PATCH 006/188] UBI: Fix size parsing in "ubi create" Signed-off-by: Stefan Roese --- common/cmd_ubi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/cmd_ubi.c b/common/cmd_ubi.c index 495d71ec0..fd33a6710 100644 --- a/common/cmd_ubi.c +++ b/common/cmd_ubi.c @@ -546,7 +546,7 @@ static int do_ubi(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } /* E.g., create volume size */ if (argc == 4) { - addr = simple_strtoul(argv[3], NULL, 16); + size = simple_strtoul(argv[3], NULL, 16); argc--; } /* Use maximum available size */ From 8c5170a7d088601d5f30d85093388dab1f1e8ec0 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Tue, 9 Dec 2008 23:20:18 -0500 Subject: [PATCH 007/188] fs/fat: handle FAT on SATA The FAT file system driver should also handle FAT on SATA devices. Signed-off-by: Sonic Zhang Signed-off-by: Mike Frysinger --- fs/fat/fat.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 06eabc362..a9dde7def 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -84,6 +84,7 @@ fat_register_device(block_dev_desc_t *dev_desc, int part_no) return -1; } #if (defined(CONFIG_CMD_IDE) || \ + defined(CONFIG_CMD_SATA) || \ defined(CONFIG_CMD_SCSI) || \ defined(CONFIG_CMD_USB) || \ defined(CONFIG_MMC) || \ @@ -980,12 +981,14 @@ file_fat_detectfs(void) return 1; } #if defined(CONFIG_CMD_IDE) || \ + defined(CONFIG_CMD_SATA) || \ defined(CONFIG_CMD_SCSI) || \ defined(CONFIG_CMD_USB) || \ defined(CONFIG_MMC) printf("Interface: "); switch(cur_dev->if_type) { case IF_TYPE_IDE : printf("IDE"); break; + case IF_TYPE_SATA : printf("SATA"); break; case IF_TYPE_SCSI : printf("SCSI"); break; case IF_TYPE_ATAPI : printf("ATAPI"); break; case IF_TYPE_USB : printf("USB"); break; From bcb6dd9187d4b23c748704767bd12d20c829e996 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 9 Dec 2008 23:20:31 -0500 Subject: [PATCH 008/188] tools/netconsole: new script for working with netconsole over UDP While the doc/README.NetConsole does have a snippet for people to create their own netcat script, it's a lot easier to make a simple dedicated script and tell people to use it. Also spruce it up a bit to make it user friendly. Signed-off-by: Mike Frysinger --- doc/README.NetConsole | 18 ++++-------------- tools/netconsole | 42 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+), 14 deletions(-) create mode 100755 tools/netconsole diff --git a/doc/README.NetConsole b/doc/README.NetConsole index fea8e3364..94c881676 100644 --- a/doc/README.NetConsole +++ b/doc/README.NetConsole @@ -22,21 +22,11 @@ For example, if your server IP is 192.168.1.1, you could use: On the host side, please use this script to access the console: -+++++++++++++++++++++++++++++++++++++++++++ -#! /bin/bash + tools/netconsole [port] -[ $# = 1 ] || { echo "Usage: $0 target_ip" >&2 ; exit 1 ; } -TARGET_IP=$1 - -stty -icanon -echo intr ^T -nc -u -l -p 6666 < /dev/null & -nc -u ${TARGET_IP} 6666 -stty icanon echo intr ^C -+++++++++++++++++++++++++++++++++++++++++++ - -The script expects exactly one argument, which is interpreted as the -target IP address (or host name, assuming DNS is working). The script -can be interrupted by pressing ^T (CTRL-T). +The script uses netcat to talk to the board over UDP. It requires you to +specify the target IP address (or host name, assuming DNS is working). The +script can be interrupted by pressing ^T (CTRL-T). Be aware that in some distributives (Fedora Core 5 at least) usage of nc has been changed and -l and -p options are considered diff --git a/tools/netconsole b/tools/netconsole new file mode 100755 index 000000000..09c898168 --- /dev/null +++ b/tools/netconsole @@ -0,0 +1,42 @@ +#!/bin/sh + +usage() { + ( + echo "Usage: $0 [board port]" + echo "" + echo "If port is not specified, '6666' will be used" + [ -z "$*" ] && exit 0 + echo "" + echo "ERROR: $*" + exit 1 + ) 1>&2 + exit $? +} + +while [ -n "$1" ] ; do + case $1 in + -h|--help) usage;; + --) break;; + -*) usage "Invalid option $1";; + *) break;; + esac + shift +done + +ip=$1 +port=${2:-6666} + +if [ -z "${ip}" ] || [ -n "$3" ] ; then + usage "Invalid number of arguments" +fi + +for nc in netcat nc ; do + type ${nc} >/dev/null && break +done + +trap "stty icanon echo intr ^C" 0 2 3 5 10 13 15 +echo "NOTE: the interrupt signal (normally ^C) has been remapped to ^T" + +stty -icanon -echo intr ^T +${nc} -u -l -p ${port} < /dev/null & +exec ${nc} -u ${ip} ${port} From c85ff0553a8cfbcca51c15b947e1ed55d3810a39 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 24 Nov 2008 11:38:22 +0100 Subject: [PATCH 009/188] microblaze: Set up relocation is done --- lib_microblaze/board.c | 1 + 1 file changed, 1 insertion(+) diff --git a/lib_microblaze/board.c b/lib_microblaze/board.c index 250972cb6..4f48341f3 100644 --- a/lib_microblaze/board.c +++ b/lib_microblaze/board.c @@ -120,6 +120,7 @@ void board_init (void) bd->bi_baudrate = CONFIG_BAUDRATE; bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ /* Initialise malloc() area */ mem_malloc_init (); From e7d591e823a991513833af7030468409e25a3b13 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 24 Nov 2008 11:43:00 +0100 Subject: [PATCH 010/188] microblaze: Fix ml401 uart16550 setting Signed-off-by: Michal Simek --- include/configs/ml401.h | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/include/configs/ml401.h b/include/configs/ml401.h index 63d07ffd2..b31c4b53c 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -37,17 +37,20 @@ #define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR #define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } -#else -#ifdef XILINX_UART16550_BASEADDR -#define CONFIG_SYS_NS16550 +#elif XILINX_UART16550_BASEADDR +#define CONFIG_SYS_NS16550 1 #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 4 +#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 XILINX_UART16550_BASEADDR +#define CONFIG_SYS_NS16550_COM1 (XILINX_UART16550_BASEADDR + 0x1000 + 0x3) #define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 115200 } -#endif + +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} +#else +#error Undefined uart #endif /* setting reset address */ From 99ba6f353582720defff6e6e6761dc455a207d31 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 24 Nov 2008 18:25:41 +0100 Subject: [PATCH 011/188] microblaze: Remove CONFIG_LIBFDT due to error in common files --- include/configs/ml401.h | 1 - include/configs/xupv2p.h | 1 - 2 files changed, 2 deletions(-) diff --git a/include/configs/ml401.h b/include/configs/ml401.h index b31c4b53c..c802dcb6a 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -277,6 +277,5 @@ "1m(romfs),1m(cramfs),-(jffs2)\0" #define CONFIG_CMDLINE_EDITING -#define CONFIG_OF_LIBFDT 1 #endif /* __CONFIG_H */ diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h index 6a9270306..ed844bf99 100644 --- a/include/configs/xupv2p.h +++ b/include/configs/xupv2p.h @@ -222,6 +222,5 @@ #endif #define CONFIG_CMDLINE_EDITING -#define CONFIG_OF_LIBFDT 1 /* flat device tree */ #endif /* __CONFIG_H */ From 8fab49ea911fe925392fa5afcc9bc7373a3d0cee Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 25 Nov 2008 11:42:20 +0100 Subject: [PATCH 012/188] microblaze: Remove XUPV2P board --- Microblaze platforms use generic settings and to have many platforms is confusing that's why I decided to remove this platform from U-BOOT. ml401 tree is sufficient for covering all Microblaze platforms. This change will go through microblaze custodian tree. --- MAINTAINERS | 1 - MAKEALL | 1 - Makefile | 5 - board/xilinx/xupv2p/Makefile | 50 ------- board/xilinx/xupv2p/config.mk | 32 ----- board/xilinx/xupv2p/u-boot.lds | 68 --------- board/xilinx/xupv2p/xparameters.h | 58 -------- board/xilinx/xupv2p/xupv2p.c | 49 ------- include/configs/xupv2p.h | 226 ------------------------------ 9 files changed, 490 deletions(-) delete mode 100644 board/xilinx/xupv2p/Makefile delete mode 100644 board/xilinx/xupv2p/config.mk delete mode 100644 board/xilinx/xupv2p/u-boot.lds delete mode 100644 board/xilinx/xupv2p/xparameters.h delete mode 100644 board/xilinx/xupv2p/xupv2p.c delete mode 100644 include/configs/xupv2p.h diff --git a/MAINTAINERS b/MAINTAINERS index 127604b0f..f04879555 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -704,7 +704,6 @@ Yasushi Shoji Michal Simek ML401 MicroBlaze - XUPV2P MicroBlaze ######################################################################### # Coldfire Systems: # diff --git a/MAKEALL b/MAKEALL index a16549c10..cc49a9808 100755 --- a/MAKEALL +++ b/MAKEALL @@ -698,7 +698,6 @@ LIST_nios2=" \ LIST_microblaze=" \ ml401 \ suzaku \ - xupv2p \ " ######################################################################### diff --git a/Makefile b/Makefile index f8fe29cf5..ca91f05a9 100644 --- a/Makefile +++ b/Makefile @@ -3153,11 +3153,6 @@ suzaku_config: unconfig @echo "#define CONFIG_SUZAKU 1" > $(obj)include/config.h @$(MKCONFIG) -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno -xupv2p_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_XUPV2P 1" > $(obj)include/config.h - @$(MKCONFIG) -a $(@:_config=) microblaze microblaze xupv2p xilinx - #======================================================================== # Blackfin #======================================================================== diff --git a/board/xilinx/xupv2p/Makefile b/board/xilinx/xupv2p/Makefile deleted file mode 100644 index 10b47b2ae..000000000 --- a/board/xilinx/xupv2p/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS = $(BOARD).o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/xilinx/xupv2p/config.mk b/board/xilinx/xupv2p/config.mk deleted file mode 100644 index c07b0b35b..000000000 --- a/board/xilinx/xupv2p/config.mk +++ /dev/null @@ -1,32 +0,0 @@ -# -# (C) Copyright 2007 Michal Simek -# -# Michal SIMEK -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# CAUTION: This file is automatically generated by libgen. -# Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 -# - -TEXT_BASE = 0x38000000 - -PLATFORM_CPPFLAGS += -mno-xl-soft-mul -PLATFORM_CPPFLAGS += -mno-xl-soft-div -PLATFORM_CPPFLAGS += -mxl-barrel-shift diff --git a/board/xilinx/xupv2p/u-boot.lds b/board/xilinx/xupv2p/u-boot.lds deleted file mode 100644 index b38f64877..000000000 --- a/board/xilinx/xupv2p/u-boot.lds +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(microblaze) -ENTRY(_start) - -SECTIONS -{ - .text ALIGN(0x4): - { - __text_start = .; - cpu/microblaze/start.o (.text) - *(.text) - __text_end = .; - } - - .rodata ALIGN(0x4): - { - __rodata_start = .; - *(.rodata) - __rodata_end = .; - } - - .data ALIGN(0x4): - { - __data_start = .; - *(.data) - __data_end = .; - } - - .u_boot_cmd ALIGN(0x4): - { - . = .; - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } - - .bss ALIGN(0x4): - { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end = .; - } - __end = . ; -} diff --git a/board/xilinx/xupv2p/xparameters.h b/board/xilinx/xupv2p/xparameters.h deleted file mode 100644 index 9e5ebdabc..000000000 --- a/board/xilinx/xupv2p/xparameters.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * CAUTION: This file is automatically generated by libgen. - * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 - */ - -/* System Clock Frequency */ -#define XILINX_CLOCK_FREQ 100000000 - -/* Interrupt controller is opb_intc_0 */ -#define XILINX_INTC_BASEADDR 0x41200000 -#define XILINX_INTC_NUM_INTR_INPUTS 11 - -/* Timer pheriphery is opb_timer_1 */ -#define XILINX_TIMER_BASEADDR 0x41c00000 -#define XILINX_TIMER_IRQ 1 - -/* Uart pheriphery is RS232_Uart_1 */ -#define XILINX_UARTLITE_BASEADDR 0x40600000 -#define XILINX_UARTLITE_BAUDRATE 115200 - -/* GPIO is LEDs_4Bit*/ -#define XILINX_GPIO_BASEADDR 0x40000000 - -/* FLASH doesn't exist none */ - -/* Main Memory is DDR_256MB_32MX64_rank1_row13_col10_cl2_5 */ -#define XILINX_RAM_START 0x30000000 -#define XILINX_RAM_SIZE 0x10000000 - -/* Sysace Controller is SysACE_CompactFlash */ -#define XILINX_SYSACE_BASEADDR 0x41800000 -#define XILINX_SYSACE_HIGHADDR 0x4180ffff -#define XILINX_SYSACE_MEM_WIDTH 16 - -/* Ethernet controller is Ethernet_MAC */ -#define XILINX_EMACLITE_BASEADDR 0x40C00000 diff --git a/board/xilinx/xupv2p/xupv2p.c b/board/xilinx/xupv2p/xupv2p.c deleted file mode 100644 index b1a76c0c5..000000000 --- a/board/xilinx/xupv2p/xupv2p.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* This is a board specific file. It's OK to include board specific - * header files */ - -#include -#include - -void do_reset (void) -{ -#ifdef CONFIG_SYS_GPIO_0 - *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = - ++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR))); -#endif -#ifdef CONFIG_SYS_RESET_ADDRESS - puts ("Reseting board\n"); - asm ("bra r0"); -#endif -} - -int gpio_init (void) -{ -#ifdef CONFIG_SYS_GPIO_0 - *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0x0; -#endif - return 0; -} diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h deleted file mode 100644 index ed844bf99..000000000 --- a/include/configs/xupv2p.h +++ /dev/null @@ -1,226 +0,0 @@ -/* - * (C) Copyright 2007-2008 Michal Simek - * - * Michal SIMEK - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "../board/xilinx/xupv2p/xparameters.h" - -#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */ -#define CONFIG_XUPV2P 1 - -/* uart */ -#ifdef XILINX_UARTLITE_BASEADDR -#define CONFIG_XILINX_UARTLITE -#define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR -#define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE -#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } -#else -#ifdef XILINX_UART16550_BASEADDR -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 4 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 XILINX_UART16550_BASEADDR -#define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 115200 } -#endif -#endif - -/* - * setting reset address - * - * TEXT_BASE is set to place, where the U-BOOT run in RAM, but - * if you want to store U-BOOT in flash, set CONFIG_SYS_RESET_ADDRESS - * to FLASH memory and after loading bitstream jump to FLASH. - * U-BOOT auto-relocate to TEXT_BASE. After RESET command Microblaze - * jump to CONFIG_SYS_RESET_ADDRESS where is the original U-BOOT code. - */ -/* #define CONFIG_SYS_RESET_ADDRESS 0x36000000 */ - -/* ethernet */ -#ifdef XILINX_EMAC_BASEADDR -#define CONFIG_XILINX_EMAC 1 -#define CONFIG_SYS_ENET -#else -#ifdef XILINX_EMACLITE_BASEADDR -#define CONFIG_XILINX_EMACLITE 1 -#define CONFIG_SYS_ENET -#endif -#endif -#undef ET_DEBUG - -/* gpio */ -#ifdef XILINX_GPIO_BASEADDR -#define CONFIG_SYS_GPIO_0 1 -#define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR -#endif - -/* interrupt controller */ -#ifdef XILINX_INTC_BASEADDR -#define CONFIG_SYS_INTC_0 1 -#define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR -#define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS -#endif - -/* timer */ -#ifdef XILINX_TIMER_BASEADDR -#if (XILINX_TIMER_IRQ != -1) -#define CONFIG_SYS_TIMER_0 1 -#define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR -#define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ -#define FREQUENCE XILINX_CLOCK_FREQ -#define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) -#endif -#else -#ifdef XILINX_CLOCK_FREQ -#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ -#else -#error BAD CLOCK FREQ -#endif -#endif -/* - * memory layout - Example - * TEXT_BASE = 0x3600_0000; - * CONFIG_SYS_SRAM_BASE = 0x3000_0000; - * CONFIG_SYS_SRAM_SIZE = 0x1000_0000; - * - * CONFIG_SYS_GBL_DATA_OFFSET = 0x3000_0000 + 0x1000_0000 - 0x1000 = 0x3FFF_F000 - * CONFIG_SYS_MONITOR_BASE = 0x3FFF_F000 - 0x40000 = 0x3FFB_F000 - * CONFIG_SYS_MALLOC_BASE = 0x3FFB_F000 - 0x40000 = 0x3FF7_F000 - * - * 0x3000_0000 CONFIG_SYS_SDRAM_BASE - * FREE - * 0x3600_0000 TEXT_BASE - * U-BOOT code - * 0x3602_0000 - * FREE - * - * STACK - * 0x3FF7_F000 CONFIG_SYS_MALLOC_BASE - * MALLOC_AREA 256kB Alloc - * 0x3FFB_F000 CONFIG_SYS_MONITOR_BASE - * MONITOR_CODE 256kB Env - * 0x3FFF_F000 CONFIG_SYS_GBL_DATA_OFFSET - * GLOBAL_DATA 4kB bd, gd - * 0x4000_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - */ - -/* ddr sdram - main memory */ -#define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START -#define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) - -/* global pointer */ -#define CONFIG_SYS_GBL_DATA_SIZE 0x1000 /* size of global data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) /* start of global data */ - -/* monitor code */ -#define SIZE 0x40000 -#define CONFIG_SYS_MONITOR_LEN SIZE -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MONITOR_END (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MALLOC_LEN SIZE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) - -/* stack */ -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MALLOC_BASE - -#define CONFIG_SYS_NO_FLASH 1 -#define CONFIG_ENV_IS_NOWHERE 1 -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_JFFS2 -#undef CONFIG_CMD_IMLS - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_IRQ - -#ifndef CONFIG_SYS_ENET - #undef CONFIG_CMD_NET -#else - #define CONFIG_CMD_PING -#endif - -#ifdef XILINX_SYSACE_BASEADDR -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_PROMPT "U-Boot-mONStR> " -#define CONFIG_SYS_CBSIZE 512 /* size of console buffer */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ -#define CONFIG_SYS_MAXARGS 15 /* max number of command args */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_LOAD_ADDR 0x12000000 /* default load address */ - -#define CONFIG_BOOTDELAY 30 -#define CONFIG_BOOTARGS "root=romfs" -#define CONFIG_HOSTNAME "xupv2p" -#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" -#define CONFIG_IPADDR 192.168.0.3 -#define CONFIG_SERVERIP 192.168.0.5 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD - -/* architecture dependent code */ -#define CONFIG_SYS_USR_EXCEP /* user exception */ -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_PREBOOT "echo U-BOOT by mONStR;" \ - "base 0;" \ - "echo" - -/* system ace */ -#ifdef XILINX_SYSACE_BASEADDR -#define CONFIG_SYSTEMACE -/* #define DEBUG_SYSTEMACE */ -#define SYSTEMACE_CONFIG_FPGA -#define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR -#define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH -#define CONFIG_DOS_PARTITION -#endif - -#define CONFIG_CMDLINE_EDITING - -#endif /* __CONFIG_H */ From 2145188bea2df8f2b47a87ec3071b55027e8d0ae Mon Sep 17 00:00:00 2001 From: Ben Warren Date: Tue, 9 Dec 2008 23:34:15 -0800 Subject: [PATCH 013/188] Fix compile error in building MBX860T. Signed-off-by: Ben Warren --- cpu/mpc8xx/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpu/mpc8xx/cpu.c b/cpu/mpc8xx/cpu.c index 40f81efc3..2eb848bd0 100644 --- a/cpu/mpc8xx/cpu.c +++ b/cpu/mpc8xx/cpu.c @@ -644,7 +644,7 @@ void reset_8xx_watchdog (volatile immap_t * immr) */ int cpu_eth_init(bd_t *bis) { -#if defined(SCC_ENET) +#if defined(SCC_ENET) && defined(CONFIG_CMD_NET) scc_initialize(bis); #endif #if defined(FEC_ENET) From 817329351639a8895cd9b87b33aeff043f3d5a44 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 10 Dec 2008 10:28:33 +0100 Subject: [PATCH 014/188] UBI: Return -ENOMEM upon failing malloc Return with correct error code (-ENOMEM) from ubi_attach_mtd_dev() upon failing malloc(). Signed-off-by: Stefan Roese --- drivers/mtd/ubi/build.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index bdf75c98a..f4b01a9de 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -784,19 +784,20 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset) if (err) goto out_free; + err = -ENOMEM; ubi->peb_buf1 = vmalloc(ubi->peb_size); if (!ubi->peb_buf1) goto out_free; ubi->peb_buf2 = vmalloc(ubi->peb_size); if (!ubi->peb_buf2) - goto out_free; + goto out_free; #ifdef CONFIG_MTD_UBI_DEBUG mutex_init(&ubi->dbg_buf_mutex); ubi->dbg_peb_buf = vmalloc(ubi->peb_size); if (!ubi->dbg_peb_buf) - goto out_free; + goto out_free; #endif err = attach_by_scanning(ubi); From 3b089e4f889a2902449d55e081c886ae607cae89 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 10 Dec 2008 10:32:59 +0100 Subject: [PATCH 015/188] UBI: Set ubi_dev.type back to DEV_TYPE_NONE upon failing initialization With this patch we set the type back to NONE upon failing UBI partition initialization. Otherwise further calls to the UBI subsystem would try to really access the non-existing UBI partition. Thanks to Michael Lawnick for pointing this out. Signed-off-by: Stefan Roese --- common/cmd_ubi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/common/cmd_ubi.c b/common/cmd_ubi.c index fd33a6710..4c358924e 100644 --- a/common/cmd_ubi.c +++ b/common/cmd_ubi.c @@ -508,6 +508,7 @@ static int do_ubi(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) err = ubi_dev_scan(ubi_dev.mtd_info, ubi_dev.part_name); if (err) { printf("UBI init error %d\n", err); + ubi_dev.type = DEV_TYPE_NONE; return err; } From 8c92af7b2fbd60ae87379477f93c7ec9441b7452 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 9 Dec 2008 20:08:01 +0100 Subject: [PATCH 016/188] ppc4xx: Remove some features from ALPR to fit into 256k again Signed-off-by: Stefan Roese --- include/configs/alpr.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 6e9f5e5a5..7ce820518 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -235,18 +235,15 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_DIAG #define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF #define CONFIG_CMD_FPGA #define CONFIG_CMD_I2C #define CONFIG_CMD_IRQ #define CONFIG_CMD_MII #define CONFIG_CMD_NAND #define CONFIG_CMD_NET -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI #define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO - +#undef CONFIG_CMD_NFS #undef CONFIG_WATCHDOG /* watchdog disabled */ From 1951f847f0a851853871b613ad7cf21a5242226c Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Wed, 10 Dec 2008 14:41:25 +0100 Subject: [PATCH 017/188] ppc4xx: Update TEXT_BASE for CPCI405 boards This patch fixes building U-Boot for CPCI405 boards. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- Makefile | 5 +---- board/esd/cpci405/config.mk | 6 +----- include/configs/CPCI405.h | 6 +++--- 3 files changed, 5 insertions(+), 12 deletions(-) diff --git a/Makefile b/Makefile index f8fe29cf5..2f07657f5 100644 --- a/Makefile +++ b/Makefile @@ -1261,14 +1261,11 @@ CMS700_config: unconfig CPCI2DP_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd -CPCI405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd - +CPCI405_config \ CPCI4052_config \ CPCI405DT_config \ CPCI405AB_config: unconfig @mkdir -p $(obj)board/esd/cpci405 - @echo "TEXT_BASE = 0xFFFC0000" > $(obj)board/esd/cpci405/config.tmp @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd CPCIISER4_config: unconfig diff --git a/board/esd/cpci405/config.mk b/board/esd/cpci405/config.mk index 6cfb8912d..1bdf5e4fc 100644 --- a/board/esd/cpci405/config.mk +++ b/board/esd/cpci405/config.mk @@ -21,8 +21,4 @@ # MA 02111-1307 USA # -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -ifndef TEXT_BASE -TEXT_BASE = 0xFFFD0000 -endif +TEXT_BASE = 0xFFFC0000 diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 1a2bc1c2e..89ba139af 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -196,9 +196,9 @@ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFD0000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ +#define CONFIG_SYS_FLASH_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ /* From 9a1d3557dcd47365c12eeab584b822e57d994352 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 11 Nov 2008 22:20:15 +0100 Subject: [PATCH 018/188] sh: fix rsk7203 and MigoR out of tree build Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nobuhiro Iwamatsu --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index f8fe29cf5..91acd14ee 100644 --- a/Makefile +++ b/Makefile @@ -3210,7 +3210,7 @@ mimc200_config : unconfig rsk7203_config: unconfig @ >include/config.h @echo "#define CONFIG_RSK7203 1" >> include/config.h - @./mkconfig -a $(@:_config=) sh sh2 rsk7203 renesas + @$(MKCONFIG) -a $(@:_config=) sh sh2 rsk7203 renesas ######################################################################### ## sh3 (Renesas SuperH) @@ -3233,7 +3233,7 @@ ms7720se_config: unconfig MigoR_config : unconfig @mkdir -p $(obj)include @echo "#define CONFIG_MIGO_R 1" > $(obj)include/config.h - @./mkconfig -a $(@:_config=) sh sh4 MigoR renesas + @$(MKCONFIG) -a $(@:_config=) sh sh4 MigoR renesas ms7750se_config: unconfig @mkdir -p $(obj)include From 15e2697c9f7fb2ba672a1a70f07cd6d9d4e92b51 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 17 Nov 2008 16:53:09 +0900 Subject: [PATCH 019/188] sh: Update SuperH serial driver The address of SCFSR register is wrong at SH7720/SH7721. This patch fix this. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- drivers/serial/serial_sh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index f30532b5a..1d76a194a 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -94,7 +94,7 @@ # define LSR_ORER 1 # define FIFOLEVEL_MASK 0x1F #elif defined(CONFIG_CPU_SH7720) -# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +# define SCLSR SCFSR # define LSR_ORER 0x0200 # define FIFOLEVEL_MASK 0x1F #elif defined(CONFIG_CPU_SH7710) || \ From 5783758fd260a02f44566ad8f29f899565cd0403 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Mon, 17 Nov 2008 16:52:09 +0900 Subject: [PATCH 020/188] sh: Update ms7722se board config Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- include/configs/ms7722se.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index 9997c9b01..52020047d 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -31,10 +31,13 @@ #define CONFIG_MS7722SE 1 #define CONFIG_CMD_FLASH +#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NET +#define CONFIG_CMD_NFS #define CONFIG_CMD_PING #define CONFIG_CMD_DFL #define CONFIG_CMD_SDRAM +#define CONFIG_CMD_MEMORY #define CONFIG_CMD_ENV #define CONFIG_BAUDRATE 115200 From b81786cff476c41e332eaeb679158f6527cd67d4 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 4 Nov 2008 11:58:58 +0900 Subject: [PATCH 021/188] sh: Migo-R: Update BSC value A value of BSC CS4 was wrong, Fixed it. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/MigoR/lowlevel_init.S | 32 ++++++++++++++--------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/board/renesas/MigoR/lowlevel_init.S b/board/renesas/MigoR/lowlevel_init.S index e48f7b3b1..4c1900ec2 100644 --- a/board/renesas/MigoR/lowlevel_init.S +++ b/board/renesas/MigoR/lowlevel_init.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 + * Copyright (C) 2007-2008 * Nobuhiro Iwamatsu * * Copyright (C) 2007 @@ -211,25 +211,25 @@ PFC_PULCR_D: .long 0x6000 PFC_DRVCR_D: .long 0x0464 FRQCR_D: .long 0x07033639 PLLCR_D: .long 0x00005000 -DLLFRQ_D: .long 0x000004F6 ! 20080115 +DLLFRQ_D: .long 0x000004F6 CMNCR_A: .long CMNCR -CMNCR_D: .long 0x0000001B ! 20080115 -CS0BCR_A: .long CS0BCR ! Flash bank 1 +CMNCR_D: .long 0x0000001B +CS0BCR_A: .long CS0BCR CS0BCR_D: .long 0x24920400 -CS4BCR_A: .long CS4BCR ! -CS4BCR_D: .long 0x10003400 ! 20080115 -CS5ABCR_A: .long CS5ABCR ! +CS4BCR_A: .long CS4BCR +CS4BCR_D: .long 0x00003400 +CS5ABCR_A: .long CS5ABCR CS5ABCR_D: .long 0x24920400 -CS5BBCR_A: .long CS5BBCR ! +CS5BBCR_A: .long CS5BBCR CS5BBCR_D: .long 0x24920400 -CS6ABCR_A: .long CS6ABCR ! +CS6ABCR_A: .long CS6ABCR CS6ABCR_D: .long 0x24920400 CS0WCR_A: .long CS0WCR CS0WCR_D: .long 0x00000380 CS4WCR_A: .long CS4WCR -CS4WCR_D: .long 0x00100A81 ! 20080115 +CS4WCR_D: .long 0x00110080 CS5AWCR_A: .long CS5AWCR CS5AWCR_D: .long 0x00000300 CS5BWCR_A: .long CS5BWCR @@ -238,20 +238,20 @@ CS6AWCR_A: .long CS6AWCR CS6AWCR_D: .long 0x00000300 SDCR_A: .long SBSC_SDCR -SDCR_D: .long 0x80160809 ! 20080115 +SDCR_D: .long 0x80160809 SDWCR_A: .long SBSC_SDWCR -SDWCR_D: .long 0x0014450C ! 20080115 +SDWCR_D: .long 0x0014450C SDPCR_A: .long SBSC_SDPCR SDPCR_D: .long 0x00000087 RTCOR_A: .long SBSC_RTCOR RTCNT_A: .long SBSC_RTCNT RTCNT_D: .long 0xA55A0012 -RTCOR_D: .long 0xA55A001C ! 20080115 +RTCOR_D: .long 0xA55A001C RTCSR_A: .long SBSC_RTCSR RFCR_A: .long SBSC_RFCR RFCR_D: .long 0xA55A0221 -RTCSR_D: .long 0xA55A009a ! 20080115 -SDMR3_A: .long 0xFE581180 ! 20080115 +RTCSR_D: .long 0xA55A009a +SDMR3_A: .long 0xFE581180 SR_MASK_D: .long 0xEFFFFF0F @@ -260,5 +260,5 @@ SR_MASK_D: .long 0xEFFFFF0F SBSCR_D: .word 0x0044 PSCR_D: .word 0x0000 RWTCSR_D_1: .word 0xA507 -RWTCSR_D_2: .word 0xA504 ! 20080115 +RWTCSR_D_2: .word 0xA504 RWTCNT_D: .word 0x5A00 From e9d5f35497885b3c65d494d09a525d443dcccd3b Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 20 Nov 2008 16:44:42 +0900 Subject: [PATCH 022/188] sh: Update sh timer function Change to write/readX function and fix timer problem. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- cpu/sh2/Makefile | 2 +- cpu/sh3/Makefile | 2 +- cpu/sh3/time.c | 103 ---------------------------- cpu/sh4/Makefile | 2 +- cpu/sh4/time.c | 98 -------------------------- lib_sh/Makefile | 6 +- lib_sh/time.c | 91 ++++++++++++++++++------ cpu/sh2/time.c => lib_sh/time_sh2.c | 0 8 files changed, 78 insertions(+), 226 deletions(-) delete mode 100644 cpu/sh3/time.c delete mode 100644 cpu/sh4/time.c rename cpu/sh2/time.c => lib_sh/time_sh2.c (100%) diff --git a/cpu/sh2/Makefile b/cpu/sh2/Makefile index 50f67208b..e33ba0f2a 100644 --- a/cpu/sh2/Makefile +++ b/cpu/sh2/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -OBJS = cpu.o interrupts.o watchdog.o time.o # cache.o +OBJS = cpu.o interrupts.o watchdog.o all: .depend $(START) $(LIB) diff --git a/cpu/sh3/Makefile b/cpu/sh3/Makefile index 587413d2e..35e8f51ab 100644 --- a/cpu/sh3/Makefile +++ b/cpu/sh3/Makefile @@ -32,7 +32,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a SOBJS = start.o -COBJS = cpu.o interrupts.o watchdog.o time.o cache.o +COBJS = cpu.o interrupts.o watchdog.o cache.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/cpu/sh3/time.c b/cpu/sh3/time.c deleted file mode 100644 index aab365982..000000000 --- a/cpu/sh3/time.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2007 - * Yoshihiro Shimoda - * - * (C) Copyright 2007 - * Nobobuhiro Iwamatsu - * - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define TMU_MAX_COUNTER (~0UL) - -static void tmu_timer_start(unsigned int timer) -{ - if (timer > 2) - return; - - outb(inb(TSTR) | (1 << timer), TSTR); -} - -static void tmu_timer_stop(unsigned int timer) -{ - u8 val = inb(TSTR); - - if (timer > 2) - return; - outb(val & ~(1 << timer), TSTR); -} - -int timer_init(void) -{ - /* Divide clock by 4 */ - outw(0, TCR0); - - tmu_timer_stop(0); - tmu_timer_start(0); - return 0; -} - -/* - In theory we should return a true 64bit value (ie something that doesn't - overflow). However, we don't. Therefore if TMU runs at fastest rate of - 6.75 MHz this value will wrap after u-boot has been running for approx - 10 minutes. -*/ -unsigned long long get_ticks(void) -{ - return (0 - inl(TCNT0)); -} - -unsigned long get_timer(unsigned long base) -{ - return ((0 - inl(TCNT0)) - base); -} - -void set_timer(unsigned long t) -{ - outl(0 - t, TCNT0); -} - -void reset_timer(void) -{ - tmu_timer_stop(0); - set_timer(0); - tmu_timer_start(0); -} - -void udelay(unsigned long usec) -{ - unsigned int start = get_timer(0); - unsigned int end = start + (usec * ((CONFIG_SYS_HZ + 500000) / 1000000)); - - while (get_timer(0) < end) - continue; -} - -unsigned long get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/cpu/sh4/Makefile b/cpu/sh4/Makefile index d3c5eef6b..3c96a4931 100644 --- a/cpu/sh4/Makefile +++ b/cpu/sh4/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a SOBJS = start.o -COBJS = cpu.o interrupts.o watchdog.o time.o cache.o +COBJS = cpu.o interrupts.o watchdog.o cache.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/cpu/sh4/time.c b/cpu/sh4/time.c deleted file mode 100644 index 77e0ae298..000000000 --- a/cpu/sh4/time.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * (C) Copyright 2007 - * Nobobuhiro Iwamatsu - * - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define TMU_MAX_COUNTER (~0UL) - -static void tmu_timer_start (unsigned int timer) -{ - if (timer > 2) - return; - - *((volatile unsigned char *) TSTR) |= (1 << timer); -} - -static void tmu_timer_stop (unsigned int timer) -{ - u8 val = *((volatile u8 *)TSTR); - if (timer > 2) - return; - *((volatile unsigned char *)TSTR) = val &~(1 << timer); -} - -int timer_init (void) -{ - /* Divide clock by 4 */ - *(volatile u16 *)TCR0 = 0; - - tmu_timer_stop(0); - tmu_timer_start(0); - return 0; -} - -/* - In theory we should return a true 64bit value (ie something that doesn't - overflow). However, we don't. Therefore if TMU runs at fastest rate of - 6.75 MHz this value will wrap after u-boot has been running for approx - 10 minutes. -*/ -unsigned long long get_ticks (void) -{ - return (0 - *((volatile u32 *) TCNT0)); -} - -unsigned long get_timer (unsigned long base) -{ - return ((0 - *((volatile u32 *) TCNT0)) - base); -} - -void set_timer (unsigned long t) -{ - *((volatile unsigned int *) TCNT0) = (0 - t); -} - -void reset_timer (void) -{ - tmu_timer_stop(0); - set_timer (0); - tmu_timer_start(0); -} - -void udelay (unsigned long usec) -{ - unsigned int start = get_timer (0); - unsigned int end = start + (usec * ((CONFIG_SYS_HZ + 500000) / 1000000)); - - while (get_timer (0) < end) - continue; -} - -unsigned long get_tbclk (void) -{ - return CONFIG_SYS_HZ; -} diff --git a/lib_sh/Makefile b/lib_sh/Makefile index 40343812f..f7c647942 100644 --- a/lib_sh/Makefile +++ b/lib_sh/Makefile @@ -26,7 +26,11 @@ SOBJS-y += COBJS-y += board.o COBJS-y += bootm.o -# COBJS-y += time.o +ifeq ($(CONFIG_SH2),y) +COBJS-y += time_sh2.o +else +COBJS-y += time.o +endif SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/lib_sh/time.c b/lib_sh/time.c index e637e95a3..2bd771528 100644 --- a/lib_sh/time.c +++ b/lib_sh/time.c @@ -1,6 +1,9 @@ /* - * Copyright (c) 2007 - * Nobuhiro Iwamatsu + * (C) Copyright 2007-2008 + * Nobobuhiro Iwamatsu + * + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this * project. @@ -23,52 +26,98 @@ #include #include +#include + +#define TMU_MAX_COUNTER (~0UL) +static int clk_adj = 1; static void tmu_timer_start (unsigned int timer) { if (timer > 2) return; + writeb(readb(TSTR) | (1 << timer), TSTR); +} - *((volatile unsigned char *) TSTR0) |= (1 << timer); +static void tmu_timer_stop (unsigned int timer) +{ + if (timer > 2) + return; + writeb(readb(TSTR) & ~(1 << timer), TSTR); } int timer_init (void) { - *(volatile u16 *)TCR0 = 0; + /* Divide clock by TMU_CLK_DIVIDER */ + u16 bit = 0; + switch( TMU_CLK_DIVIDER ){ + case 4: + bit = 0; + break; + case 16: + bit = 1; + break; + case 64: bit = 2; + break; + case 256: + bit = 3; + break; + case 1024: + bit = 4; + break; + default: + bit = 0; + break; + } + writew(readw(TCR0) | bit, TCR0); + + /* Clock adjustment calc */ + clk_adj = (int)(1.0/((1.0/CONFIG_SYS_HZ)*1000000)); + if (clk_adj < 1) + clk_adj = 1; + + tmu_timer_stop(0); + tmu_timer_start(0); - tmu_timer_start (0); return 0; } unsigned long long get_ticks (void) { - return (0 - *((volatile unsigned int *) TCNT0)); + return 0 - readl(TCNT0); } -unsigned long get_timer (unsigned long base) +static unsigned long get_usec (void) { - return ((0 - *((volatile unsigned int *) TCNT0)) - base); -} - -void set_timer (unsigned long t) -{ - *((volatile unsigned int *) TCNT0) = (0 - t); -} - -void reset_timer (void) -{ - set_timer (0); + return (0 - readl(TCNT0)); } void udelay (unsigned long usec) { - unsigned int start = get_timer (0); - unsigned int end = start + (usec * ((CONFIG_SYS_HZ + 500000) / 1000000)); + unsigned int start = get_usec(); + unsigned int end = start + (usec * clk_adj); - while (get_timer (0) < end) + while (get_usec() < end) continue; } +unsigned long get_timer (unsigned long base) +{ + /* return msec */ + return ((get_usec()/clk_adj)/1000) - base; +} + +void set_timer (unsigned long t) +{ + writel((0 - t), TCNT0); +} + +void reset_timer (void) +{ + tmu_timer_stop(0); + set_timer (0); + tmu_timer_start(0); +} + unsigned long get_tbclk (void) { return CONFIG_SYS_HZ; diff --git a/cpu/sh2/time.c b/lib_sh/time_sh2.c similarity index 100% rename from cpu/sh2/time.c rename to lib_sh/time_sh2.c From c54b9a42d8f5ab5b2a039b3a2e6fde8b427745e5 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 25 Nov 2008 11:05:19 +0900 Subject: [PATCH 023/188] sh: Changed value of CACHE_OC_NUM_ENTRIES and CACHE_OC_WAY_SHIFT SH4 is different a value of CACHE_OC_NUM_ENTRIES and CACHE_OC_WAY_SHIFT every CPU. This patch corrects these values. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- include/asm-sh/cpu_sh4.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h index b6cc6cfbd..d2dbfcd14 100644 --- a/include/asm-sh/cpu_sh4.h +++ b/include/asm-sh/cpu_sh4.h @@ -26,8 +26,15 @@ #define CCR_CACHE_ICI 0x00000800 #define CACHE_OC_ADDRESS_ARRAY 0xf4000000 + +#if defined (CONFIG_CPU_SH7750) || \ + defined(CONFIG_CPU_SH7751) #define CACHE_OC_WAY_SHIFT 14 #define CACHE_OC_NUM_ENTRIES 512 +#else +#define CACHE_OC_WAY_SHIFT 13 +#define CACHE_OC_NUM_ENTRIES 256 +#endif #define CACHE_OC_ENTRY_SHIFT 5 #if defined (CONFIG_CPU_SH7750) || \ From 4d4a96055f6917335a89dbdf2e5556fa5ac329f6 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 2 Dec 2008 07:40:03 +0100 Subject: [PATCH 024/188] sh: r2dplus/lowlevel_init: coding style fix Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/r2dplus/lowlevel_init.S | 42 +++++++++++++-------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/board/renesas/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S index 5755de87b..87e30c5cf 100644 --- a/board/renesas/r2dplus/lowlevel_init.S +++ b/board/renesas/r2dplus/lowlevel_init.S @@ -11,7 +11,7 @@ .global lowlevel_init .text - .align 2 + .align 2 lowlevel_init: @@ -118,34 +118,34 @@ CCR_D_E: .long 0x8000090B FRQCR_A: .long FRQCR /* FRQCR Address */ FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */ -BCR1_A: .long BCR1 /* BCR1 Address */ -BCR1_D: .long 0x00180008 -BCR2_A: .long BCR2 /* BCR2 Address */ -BCR2_D: .long 0xabe8 -BCR3_A: .long BCR3 /* BCR3 Address */ -BCR3_D: .long 0x0000 -BCR4_A: .long BCR4 /* BCR4 Address */ -BCR4_D: .long 0x00000010 -WCR1_A: .long WCR1 /* WCR1 Address */ -WCR1_D: .long 0x33343333 -WCR2_A: .long WCR2 /* WCR2 Address */ -WCR2_D: .long 0xcff86fbf -WCR3_A: .long WCR3 /* WCR3 Address */ -WCR3_D: .long 0x07777707 +BCR1_A: .long BCR1 /* BCR1 Address */ +BCR1_D: .long 0x00180008 +BCR2_A: .long BCR2 /* BCR2 Address */ +BCR2_D: .long 0xabe8 +BCR3_A: .long BCR3 /* BCR3 Address */ +BCR3_D: .long 0x0000 +BCR4_A: .long BCR4 /* BCR4 Address */ +BCR4_D: .long 0x00000010 +WCR1_A: .long WCR1 /* WCR1 Address */ +WCR1_D: .long 0x33343333 +WCR2_A: .long WCR2 /* WCR2 Address */ +WCR2_D: .long 0xcff86fbf +WCR3_A: .long WCR3 /* WCR3 Address */ +WCR3_D: .long 0x07777707 LED_A: .long 0x04000036 /* LED Address */ RTCNT_A: .long RTCNT /* RTCNT Address */ RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ RTCOR_A: .long RTCOR /* RTCOR Address */ -RTCOR_D: .long 0xA534 /* RTCOR Write Code */ +RTCOR_D: .long 0xA534 /* RTCOR Write Code */ RTCSR_A: .long RTCSR /* RTCSR Address */ RTCSR_D: .long 0xA510 /* RTCSR Write Code */ -SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */ +SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */ SDMR3_D: .long 0x55 MCR_A: .long MCR /* MCR Address */ -MCR_D1: .long 0x081901F4 /* MRSET:'0' */ -MCR_D2: .long 0x481901F4 /* MRSET:'1' */ -RFCR_A: .long RFCR /* RFCR Address */ -RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ +MCR_D1: .long 0x081901F4 /* MRSET:'0' */ +MCR_D2: .long 0x481901F4 /* MRSET:'1' */ +RFCR_A: .long RFCR /* RFCR Address */ +RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ PCR_A: .long PCR /* PCR Address */ PCR_D: .long 0x0000 MMUCR_A: .long MMUCR /* MMUCCR Address */ From a319f1496210117b73198e3d889ffffaf6825d00 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 5 Dec 2008 07:27:37 +0100 Subject: [PATCH 025/188] sh: r2dplus fix register access Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/r2dplus/lowlevel_init.S | 2 +- drivers/pci/pci_sh7751.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/renesas/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S index 87e30c5cf..28d2b3769 100644 --- a/board/renesas/r2dplus/lowlevel_init.S +++ b/board/renesas/r2dplus/lowlevel_init.S @@ -21,7 +21,7 @@ lowlevel_init: mov.l MMUCR_A,r1 mov.l MMUCR_D,r0 - mov.w r0,@r1 + mov.l r0,@r1 mov.l BCR1_A,r1 mov.l BCR1_D,r0 diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c index e3a0ea004..df6d76f7f 100644 --- a/drivers/pci/pci_sh7751.c +++ b/drivers/pci/pci_sh7751.c @@ -187,8 +187,8 @@ int pci_sh7751_init(struct pci_controller *hose) /* Copy BSC registers into PCI BSC */ p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1); - p4_out(inl(SH7751_BCR2), SH7751_PCIBCR2); - p4_out(inl(SH7751_BCR3), SH7751_PCIBCR3); + p4_out(inw(SH7751_BCR2), SH7751_PCIBCR2); + p4_out(inw(SH7751_BCR3), SH7751_PCIBCR3); p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1); p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2); p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3); From d8bbc51c7ba9b737a20984333d19fe28a3526431 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 9 Dec 2008 11:32:46 +0900 Subject: [PATCH 026/188] sh: Update sh2/sh2a timer Renesas SH2/SH2A timer broken. This patch fix timer function. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- lib_sh/time_sh2.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/lib_sh/time_sh2.c b/lib_sh/time_sh2.c index fcbb921c8..4f893c87b 100644 --- a/lib_sh/time_sh2.c +++ b/lib_sh/time_sh2.c @@ -65,8 +65,8 @@ unsigned long long get_ticks(void) return cmt0_timer; } -static vu_long cmcnt; -ulong get_timer(ulong base) +static vu_long cmcnt = 0; +static unsigned long get_usec (void) { ulong data = readw(CMCNT_0); @@ -81,7 +81,13 @@ ulong get_timer(ulong base) cmt0_timer += cmcnt; cmcnt = data; - return cmt0_timer - base; + return cmt0_timer; +} + +/* return msec */ +ulong get_timer(ulong base) +{ + return (get_usec()/1000) - base; } void set_timer(ulong t) @@ -99,9 +105,9 @@ void reset_timer(void) void udelay(unsigned long usec) { - unsigned int start = get_timer(0); + unsigned long end = get_usec() + usec; - while (get_timer((ulong) start) < (usec * (CONFIG_SYS_HZ / 1000000))) + while (get_usec() < end) continue; } From 9d23fc584c4b7b8bb9ecbee48920b1b04b08fa1b Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 12 Nov 2008 13:18:19 +0100 Subject: [PATCH 027/188] MIPS: Add onenand_init() to board.c and move nand_init() This patch adds a call to onenand_init() for OneNAND support and moves the nand_init() call to an earlier place, so that the environment can be used from NAND and OneNAND. Signed-off-by: Stefan Roese Signed-off-by: Shinya Kuribayashi --- lib_mips/board.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/lib_mips/board.c b/lib_mips/board.c index 9c997f190..5133b8a5d 100644 --- a/lib_mips/board.c +++ b/lib_mips/board.c @@ -30,6 +30,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -378,6 +379,15 @@ void board_init_r (gd_t *id, ulong dest_addr) mem_malloc_init(); malloc_bin_reloc(); +#ifdef CONFIG_CMD_NAND + puts ("NAND: "); + nand_init (); /* go init the NAND */ +#endif + +#if defined(CONFIG_CMD_ONENAND) + onenand_init(); +#endif + /* relocate environment function pointers etc. */ env_relocate(); @@ -419,11 +429,6 @@ void board_init_r (gd_t *id, ulong dest_addr) } #endif -#ifdef CONFIG_CMD_NAND - puts ("NAND: "); - nand_init (); /* go init the NAND */ -#endif - #ifdef CONFIG_CMD_SPI puts ("SPI: "); spi_init (); /* go init the SPI */ From db08ecaa6eb8176904b3bae103a85ee8f735dc40 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 12 Nov 2008 13:18:02 +0100 Subject: [PATCH 028/188] MIPS: Add board_early_init_f() to init_sequence This patch adds the board_early_init_f() call to the MIPS init sequence. A weak dummy implementation is also added which can be overridden by a board specific version. This will be used by the upcoming VCTH board support. Signed-off-by: Stefan Roese Signed-off-by: Shinya Kuribayashi --- lib_mips/board.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/lib_mips/board.c b/lib_mips/board.c index 5133b8a5d..dfe683161 100644 --- a/lib_mips/board.c +++ b/lib_mips/board.c @@ -72,6 +72,15 @@ static ulong mem_malloc_brk; */ unsigned long mips_io_port_base = -1; +int __board_early_init_f(void) +{ + /* + * Nothing to do in this dummy implementation + */ + return 0; +} +int board_early_init_f(void) __attribute__((weak, alias("__board_early_init_f"))); + /* * The Malloc area is immediately below the monitor copy in DRAM */ @@ -169,6 +178,7 @@ static int init_baudrate (void) typedef int (init_fnc_t) (void); init_fnc_t *init_sequence[] = { + board_early_init_f, timer_init, env_init, /* initialize environment */ #ifdef CONFIG_INCA_IP From 44174343688dba32571a34550dba08971c65fef1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 18 Nov 2008 16:36:22 +0100 Subject: [PATCH 029/188] MIPS: Add CONFIG_SKIP_LOWLEVEL_INIT This patch adds the CONFIG_SKIP_LOWLEVEL_INIT option to start.S. This enables support for boards where the lowlevel initialization is already done when U-Boot runs (e.g. via OnChip ROM). This will be used in the upcoming VCTH board support. Signed-off-by: Stefan Roese Signed-off-by: Shinya Kuribayashi --- cpu/mips/start.S | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cpu/mips/start.S b/cpu/mips/start.S index 6a22302a0..f6069b3ee 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -243,9 +243,11 @@ reset: mtc0 zero, CP0_COUNT mtc0 zero, CP0_COMPARE +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) /* CONFIG0 register */ li t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */ /* Initialize $gp. */ @@ -255,6 +257,7 @@ reset: 1: lw gp, 0(ra) +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) /* Initialize any external memory. */ la t9, lowlevel_init @@ -271,6 +274,7 @@ reset: */ li t0, CONF_CM_CACHABLE_NONCOHERENT mtc0 t0, CP0_CONFIG +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */ /* Set up temporary stack. */ From 71fa0714fe5134bc8718c38d5261d267e88582ba Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 18 Nov 2008 16:36:12 +0100 Subject: [PATCH 030/188] MIPS: Flush data cache upon relocation This patch now adds a flush to the data cache upon relocation. The current implementation is missing this. Only a comment states that it should be done. So let's really do it now. Signed-off-by: Stefan Roese Signed-off-by: Shinya Kuribayashi --- cpu/mips/start.S | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/cpu/mips/start.S b/cpu/mips/start.S index f6069b3ee..57db589b9 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -311,6 +311,7 @@ relocate_code: la t3, in_ram lw t2, -12(t3) /* t2 <-- uboot_end_data */ move t1, a2 + move s2, a2 /* s2 <-- destination address */ /* * Fix $gp: @@ -320,13 +321,21 @@ relocate_code: move t6, gp sub gp, CONFIG_SYS_MONITOR_BASE add gp, a2 /* gp now adjusted */ - sub t6, gp, t6 /* t6 <-- relocation offset */ + sub s1, gp, t6 /* s1 <-- relocation offset */ /* * t0 = source address * t1 = target address * t2 = source end address */ + + /* + * Save destination address and size for later usage in flush_cache() + */ + move s0, a1 /* save gd in s0 */ + move a0, t1 /* a0 <-- destination addr */ + sub a1, t2, t0 /* a1 <-- size */ + /* On the purple board we copy the code earlier in a special way * in order to solve flash problems */ @@ -342,9 +351,14 @@ relocate_code: /* If caches were enabled, we would have to flush them here. */ + /* a0 & a1 are already set up for flush_cache(start, size) */ + la t9, flush_cache + jalr t9 + nop + /* Jump to where we've relocated ourselves. */ - addi t0, a2, in_ram - _start + addi t0, s2, in_ram - _start jr t0 nop @@ -371,7 +385,7 @@ in_ram: 1: lw t1, 0(t4) beqz t1, 2f - add t1, t6 + add t1, s1 sw t1, 0(t4) 2: addi t2, 1 @@ -382,8 +396,8 @@ in_ram: */ lw t1, -12(t0) /* t1 <-- uboot_end_data */ lw t2, -8(t0) /* t2 <-- uboot_end */ - add t1, t6 /* adjust pointers */ - add t2, t6 + add t1, s1 /* adjust pointers */ + add t2, s1 sub t1, 4 1: @@ -391,10 +405,10 @@ in_ram: bltl t1, t2, 1b sw zero, 0(t1) /* delay slot */ - move a0, a1 + move a0, s0 /* a0 <-- gd */ la t9, board_init_r jr t9 - move a1, a2 /* delay slot */ + move a1, s2 /* delay slot */ .end relocate_code From 5b67a1439a73ba6c34007d9ff60a2c6aa90265df Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Wed, 10 Dec 2008 15:12:56 +0100 Subject: [PATCH 031/188] ppc4xx: Fix Ethernet PHY LED configuration on PMC440 boards Signed-off-by: Matthias Fuchs --- board/esd/pmc440/pmc440.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 8563d7d5f..4d81c33a8 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -755,17 +755,31 @@ int post_hotkeys_pressed(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { + char *s; + unsigned short val_method, val_behavior; + + /* special LED setup for NGCC/CANDES */ + if ((s = getenv("bd_type")) && + ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) { + val_method = 0x0e0a; + val_behavior = 0x0cf2; + } else { + /* PMC440 standard type */ + val_method = 0x0e10; + val_behavior = 0x0cf0; + } + if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) { miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010); - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0df0); - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, 0x0e10); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method); miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000); } if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) { miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010); - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0df0); - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, 0x0e10); + miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior); + miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method); miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000); } } From 19ef4f7a6ef3b725aa9fe4b4f5fb676a84160172 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Wed, 10 Dec 2008 15:13:32 +0100 Subject: [PATCH 032/188] ppc4xx: Disable EEPROM write access on PMC440 boards This patch disables EEPROM wrtie access by default on PMC440 board. Signed-off-by: Matthias Fuchs --- board/esd/pmc440/pmc440.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 4d81c33a8..382410534 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -107,7 +107,7 @@ int board_early_init_f(void) * Setup the GPIO pins * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file */ - out32(GPIO0_OR, 0x40000002); + out32(GPIO0_OR, 0x40000102); out32(GPIO0_TCR, 0x4c90011f); out32(GPIO0_OSRL, 0x28051400); out32(GPIO0_OSRH, 0x55005000); From cd6734510a9ff0f41c4a73567d4080ea0033d2c1 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Mon, 24 Nov 2008 13:33:51 +0100 Subject: [PATCH 033/188] Fix FIT and FDT support to have CONFIG_OF_LIBFDT and CONFIG_FIT independent FDT support is used for both FIT style images and for architectures that can pass a fdt blob to an OS (ppc, m68k, sparc). For other architectures and boards which do not pass a fdt blob to an OS but want to use the new uImage format, we just need FIT support. Now we can have the 4 following configurations : 1) FIT only CONFIG_FIT 2) fdt blob only CONFIG_OF_LIBFDT 3) both CONFIG_OF_LIBFDT & CONFIG_FIT 4) none none Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- common/image.c | 2 ++ include/image.h | 4 ---- libfdt/Makefile | 8 ++++++-- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/common/image.c b/common/image.c index 866edf619..daa68bc2d 100644 --- a/common/image.c +++ b/common/image.c @@ -1071,6 +1071,7 @@ int boot_ramdisk_high (struct lmb *lmb, ulong rd_data, ulong rd_len, error: return -1; } +#endif /* defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC) */ #ifdef CONFIG_OF_LIBFDT static void fdt_error (const char *msg) @@ -1575,6 +1576,7 @@ error: } #endif /* CONFIG_OF_LIBFDT */ +#if defined(CONFIG_PPC) || defined(CONFIG_M68K) /** * boot_get_cmdline - allocate and initialize kernel cmdline * @lmb: pointer to lmb handle, will be used for memory mgmt diff --git a/include/image.h b/include/image.h index 54335559a..4609200b8 100644 --- a/include/image.h +++ b/include/image.h @@ -50,10 +50,6 @@ #endif /* USE_HOSTCC */ -#if defined(CONFIG_FIT) && !defined(CONFIG_OF_LIBFDT) -#error "CONFIG_OF_LIBFDT not enabled, required by CONFIG_FIT!" -#endif - #include #if defined(CONFIG_FIT) diff --git a/libfdt/Makefile b/libfdt/Makefile index ca2ad76c8..d6e283045 100644 --- a/libfdt/Makefile +++ b/libfdt/Makefile @@ -27,9 +27,13 @@ LIB = $(obj)libfdt.a SOBJS = -COBJS-$(CONFIG_OF_LIBFDT) += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o +COBJS-libfdt += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o -COBJS := $(COBJS-y) +COBJS-$(CONFIG_OF_LIBFDT) += $(COBJS-libfdt) +COBJS-$(CONFIG_FIT) += $(COBJS-libfdt) + + +COBJS := $(sort $(COBJS-y)) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) From 0e0c862efe7279e9609db74d758cd1b84c6c7209 Mon Sep 17 00:00:00 2001 From: Sergei Poselenov Date: Fri, 19 Sep 2008 12:07:34 +0200 Subject: [PATCH 034/188] Remove compiler warning: target CPU does not support interworking This warning is issued by modern ARM-EABI GCC on non-thumb targets. Signed-off-by: Vladimir Panfilov Signed-off-by: Sergei Poselenov --- cpu/arm720t/config.mk | 1 + cpu/arm920t/config.mk | 1 + cpu/arm925t/config.mk | 1 + cpu/arm926ejs/config.mk | 1 + cpu/arm946es/config.mk | 1 + cpu/arm_intcm/config.mk | 1 + cpu/lh7a40x/config.mk | 1 + cpu/pxa/config.mk | 1 + cpu/s3c44b0/config.mk | 1 + cpu/sa1100/config.mk | 1 + 10 files changed, 10 insertions(+) diff --git a/cpu/arm720t/config.mk b/cpu/arm720t/config.mk index 641b91cd8..3cae1dc8f 100644 --- a/cpu/arm720t/config.mk +++ b/cpu/arm720t/config.mk @@ -32,4 +32,5 @@ PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi # # ========================================================================= PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/arm920t/config.mk b/cpu/arm920t/config.mk index 8db4adbe1..38718a352 100644 --- a/cpu/arm920t/config.mk +++ b/cpu/arm920t/config.mk @@ -31,4 +31,5 @@ PLATFORM_CPPFLAGS += -march=armv4 # # ========================================================================= PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/arm925t/config.mk b/cpu/arm925t/config.mk index 8db4adbe1..38718a352 100644 --- a/cpu/arm925t/config.mk +++ b/cpu/arm925t/config.mk @@ -31,4 +31,5 @@ PLATFORM_CPPFLAGS += -march=armv4 # # ========================================================================= PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/arm926ejs/config.mk b/cpu/arm926ejs/config.mk index 84b68ae9d..a57d03aa0 100644 --- a/cpu/arm926ejs/config.mk +++ b/cpu/arm926ejs/config.mk @@ -31,4 +31,5 @@ PLATFORM_CPPFLAGS += -march=armv5te # # ========================================================================= PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/arm946es/config.mk b/cpu/arm946es/config.mk index f774c7e82..6190e16cb 100644 --- a/cpu/arm946es/config.mk +++ b/cpu/arm946es/config.mk @@ -31,4 +31,5 @@ PLATFORM_CPPFLAGS += -march=armv4 # # ========================================================================= PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/arm_intcm/config.mk b/cpu/arm_intcm/config.mk index f774c7e82..6190e16cb 100644 --- a/cpu/arm_intcm/config.mk +++ b/cpu/arm_intcm/config.mk @@ -31,4 +31,5 @@ PLATFORM_CPPFLAGS += -march=armv4 # # ========================================================================= PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/lh7a40x/config.mk b/cpu/lh7a40x/config.mk index 10e755beb..32fd1d1eb 100644 --- a/cpu/lh7a40x/config.mk +++ b/cpu/lh7a40x/config.mk @@ -31,4 +31,5 @@ PLATFORM_CPPFLAGS += -march=armv4 # # ======================================================================== PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/pxa/config.mk b/cpu/pxa/config.mk index f0b86b7dc..af910e2f6 100644 --- a/cpu/pxa/config.mk +++ b/cpu/pxa/config.mk @@ -32,4 +32,5 @@ PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale # # ======================================================================== PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/s3c44b0/config.mk b/cpu/s3c44b0/config.mk index 6dc9c463a..01e7040d6 100644 --- a/cpu/s3c44b0/config.mk +++ b/cpu/s3c44b0/config.mk @@ -32,4 +32,5 @@ PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float # # ======================================================================== PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/sa1100/config.mk b/cpu/sa1100/config.mk index 5be7dfb2f..9ef4a19d3 100644 --- a/cpu/sa1100/config.mk +++ b/cpu/sa1100/config.mk @@ -32,4 +32,5 @@ PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100 # # ======================================================================== PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) From 3aed3aa2c128ce9fb39ca3f4e9385a7499e93dbf Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sun, 14 Dec 2008 10:29:39 +0100 Subject: [PATCH 035/188] Fix new found CFG_ Also fix some minor typos. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Wolfgang Denk --- board/esd/pmc440/cmd_pmc440.c | 2 +- board/xilinx/ppc405-generic/u-boot-ram.lds | 2 +- board/xilinx/ppc405-generic/u-boot-rom.lds | 2 +- cpu/arm926ejs/at91/usb.c | 2 +- cpu/mpc86xx/release.S | 2 +- include/configs/PMC440.h | 8 ++++---- include/configs/afeb9260.h | 4 ++-- include/configs/at91cap9adk.h | 2 +- include/configs/at91sam9260ek.h | 2 +- include/configs/at91sam9263ek.h | 2 +- 10 files changed, 14 insertions(+), 14 deletions(-) diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index 3f0dca087..16c9c7eea 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -364,7 +364,7 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD; #endif /* - * gd->bd->bi_memsize == physical ram size - CFG_MEM_TOP_HIDE + * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MEM_TOP_HIDE */ param = base - (pram << 10); printf("PARAM: @%08x\n", param); diff --git a/board/xilinx/ppc405-generic/u-boot-ram.lds b/board/xilinx/ppc405-generic/u-boot-ram.lds index 0004d6100..6bbd3bd47 100644 --- a/board/xilinx/ppc405-generic/u-boot-ram.lds +++ b/board/xilinx/ppc405-generic/u-boot-ram.lds @@ -127,7 +127,7 @@ SECTIONS *(COMMON) } - ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your configuration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified."); _end = . ; PROVIDE (end = .); diff --git a/board/xilinx/ppc405-generic/u-boot-rom.lds b/board/xilinx/ppc405-generic/u-boot-rom.lds index d2bac9f1d..d09400655 100644 --- a/board/xilinx/ppc405-generic/u-boot-rom.lds +++ b/board/xilinx/ppc405-generic/u-boot-rom.lds @@ -137,7 +137,7 @@ SECTIONS *(COMMON) } - ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your configuration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified."); _end = . ; PROVIDE (end = .); diff --git a/cpu/arm926ejs/at91/usb.c b/cpu/arm926ejs/at91/usb.c index 2f5c33747..a15ab1693 100644 --- a/cpu/arm926ejs/at91/usb.c +++ b/cpu/arm926ejs/at91/usb.c @@ -35,7 +35,7 @@ int usb_cpu_init(void) #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ defined(CONFIG_AT91SAM9263) /* Enable PLLB */ - at91_sys_write(AT91_CKGR_PLLBR, CFG_AT91_PLLB); + at91_sys_write(AT91_CKGR_PLLBR, CONFIG_SYS_AT91_PLLB); while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) ; #endif diff --git a/cpu/mpc86xx/release.S b/cpu/mpc86xx/release.S index b524e5016..95efbb4f8 100644 --- a/cpu/mpc86xx/release.S +++ b/cpu/mpc86xx/release.S @@ -125,7 +125,7 @@ invl2: mtspr HID0, r5 /* enable + invalidate */ mtspr HID0, r3 /* enable */ sync -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 sync lis r3, L2_ENABLE@h ori r3, r3, L2_ENABLE@l diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 7219bb8ae..d0e3cda6c 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -219,8 +219,8 @@ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #endif -#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ - /* 440EPx errata CHIP 11 */ +#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ + /* 440EPx errata CHIP 11 */ /*----------------------------------------------------------------------- * I2C @@ -490,8 +490,8 @@ #endif /* Memory Bank 1 (RESET) initialization */ -#define CFG_EBC_PB1AP 0x7f817200 //0x03017200 -#define CFG_EBC_PB1CR (CFG_RESET_BASE | 0x1c000) +#define CONFIG_SYS_EBC_PB1AP 0x7f817200 //0x03017200 +#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_RESET_BASE | 0x1c000) /* Memory Bank 4 (FPGA / 32Bit) initialization */ #define CONFIG_SYS_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */ diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index f077ad90f..90e553d74 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -29,7 +29,7 @@ /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */ #define AT91_MASTER_CLOCK 89999598 /* peripheral = main / 2 */ -#define CFG_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */ +#define CONFIG_SYS_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */ #define CONFIG_SYS_HZ 1000000 /* 1us resolution */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ @@ -150,7 +150,7 @@ #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CFG_LONGHELP 1 +#define CONFIG_SYS_LONGHELP 1 #define CONFIG_CMDLINE_EDITING 1 #define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index aeb06ac64..363df67b5 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -32,7 +32,7 @@ #define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define AT91_MASTER_CLOCK 100000000 /* peripheral */ #define AT91_CPU_CLOCK 200000000 /* cpu */ -#define CFG_AT91_PLLB 0x10073e01 /* PLLB settings for USB */ +#define CONFUG_SYS_AT91_PLLB 0x10073e01 /* PLLB settings for USB */ #define CONFIG_SYS_HZ 1000000 /* 1us resolution */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 2df8d5491..15389296f 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -32,7 +32,7 @@ #define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ #define AT91_MASTER_CLOCK 100000000 /* peripheral */ #define AT91_CPU_CLOCK 200000000 /* cpu */ -#define CFG_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */ +#define CONFIG_SYS_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */ #define CONFIG_SYS_HZ 1000000 /* 1us resolution */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index fc7c94126..d9ebc87ae 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -32,7 +32,7 @@ #define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ #define AT91_MASTER_CLOCK 100000000 /* peripheral */ #define AT91_CPU_CLOCK 200000000 /* cpu */ -#define CFG_AT91_PLLB 0x133a3e8d /* PLLB settings for USB */ +#define CONFIG_SYS_AT91_PLLB 0x133a3e8d /* PLLB settings for USB */ #define CONFIG_SYS_HZ 1000000 /* 1us resolution */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ From d16da93430520d3e46c1ab52eedacf36ab7a2311 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 24 Nov 2008 11:54:47 -0600 Subject: [PATCH 036/188] cmd_mem: Remove unused variable Signed-off-by: Peter Tyser --- common/cmd_mem.c | 1 - 1 file changed, 1 deletion(-) diff --git a/common/cmd_mem.c b/common/cmd_mem.c index d7666c2f3..400cfd747 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -1175,7 +1175,6 @@ int do_unzip ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { unsigned long src, dst; unsigned long src_len = ~0UL, dst_len = ~0UL; - int err; switch (argc) { case 4: From ba490b7761c62b549c222a9723e532dc801a3899 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 1 Dec 2008 16:22:45 -0600 Subject: [PATCH 037/188] Remove unused CONFIG_ADDR_STREAMING defines Signed-off-by: Peter Tyser --- include/configs/ATUM8548.h | 1 - include/configs/MPC8536DS.h | 1 - include/configs/MPC8540ADS.h | 1 - include/configs/MPC8540EVAL.h | 1 - include/configs/MPC8541CDS.h | 1 - include/configs/MPC8544DS.h | 1 - include/configs/MPC8548CDS.h | 1 - include/configs/MPC8555CDS.h | 1 - include/configs/MPC8560ADS.h | 1 - include/configs/MPC8568MDS.h | 1 - include/configs/MPC8572DS.h | 1 - include/configs/PM854.h | 1 - include/configs/PM856.h | 1 - include/configs/SBC8540.h | 1 - include/configs/TQM85xx.h | 1 - include/configs/sbc8548.h | 1 - include/configs/sbc8560.h | 1 - include/configs/socrates.h | 1 - include/configs/stxgp3.h | 1 - include/configs/stxssa.h | 1 - 20 files changed, 20 deletions(-) diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index 1b745265d..7ee05e565 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -67,7 +67,6 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ /* diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 5a99d5fe7..532c3df77 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -70,7 +70,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_ENABLE_36BIT_PHYS 1 diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 0b8fe6ad6..f22b7529d 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -79,7 +79,6 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 21cf965ab..5ac1916cb 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -62,7 +62,6 @@ /* below can be toggled for performance analysis. otherwise use default */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #undef CONFIG_BTB /* toggle branch predition */ -#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index eaa737b88..399189c59 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -63,7 +63,6 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index b31c2bb37..9b1b34cc8 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -66,7 +66,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ /* * Only possible on E500 Version 2 or newer cores. diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 7a7e5a145..e1bd45ef1 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -69,7 +69,6 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ /* diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 40b40ed3a..c92f82d48 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -63,7 +63,6 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 2b5b2c106..bf4bd2c1a 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -73,7 +73,6 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 8bdec65b7..da1f45422 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -61,7 +61,6 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ /* * Only possible on E500 Version 2 or newer cores. diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 9a66ca810..37c3f4200 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -71,7 +71,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_ENABLE_36BIT_PHYS 1 diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 1cc80ad21..41e290d0b 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -71,7 +71,6 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 698ad2d91..6b4e2dd42 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -72,7 +72,6 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 2853fba06..34196319c 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -75,7 +75,6 @@ /* below can be toggled for performance analysis. otherwise use default */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #undef CONFIG_BTB /* toggle branch predition */ -#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 300f49079..6d205a7a1 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -106,7 +106,6 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 5ce4dac5e..528c81090 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -59,7 +59,6 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ /* diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index e1d3a52b5..d4e9d7479 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -69,7 +69,6 @@ /* below can be toggled for performance analysis. otherwise use default */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #undef CONFIG_BTB /* toggle branch predition */ -#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index e89b5a3fb..cbf04e3f2 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -82,7 +82,6 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index a0f2ed0da..ae6f45aee 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -64,7 +64,6 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index f0990c679..c312f1af9 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -64,7 +64,6 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ From 22525779cb51f1bbe4e96fea7b778de1935a5a69 Mon Sep 17 00:00:00 2001 From: Martin Michlmayr Date: Wed, 6 Aug 2008 14:44:05 +0300 Subject: [PATCH 038/188] Fix a typo in fw_env.config Reported-by: Martin Michlmayr Signed-off-by: Wolfgang Denk --- tools/env/fw_env.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/env/fw_env.config b/tools/env/fw_env.config index 0fe37c959..c8f12cf0a 100644 --- a/tools/env/fw_env.config +++ b/tools/env/fw_env.config @@ -1,5 +1,5 @@ # Configuration file for fw_(printenv/saveenv) utility. -# Up to two entries are valid, in this case the redundand +# Up to two entries are valid, in this case the redundant # environment sector is assumed present. # Notice, that the "Number of sectors" is ignored on NOR. From 45845301af3de8675c1f7bbc815c6de35452605a Mon Sep 17 00:00:00 2001 From: Yuri Tikhonov Date: Sun, 7 Dec 2008 22:12:50 +0100 Subject: [PATCH 039/188] POST Make: fix the sub-dir dependencies missing. Signed-off-by: Yuri Tikhonov --- post/Makefile | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/post/Makefile b/post/Makefile index a402e6adc..666a89649 100644 --- a/post/Makefile +++ b/post/Makefile @@ -45,7 +45,12 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) LIB := $(obj)$(LIB) -all: $(LIB) +all: postdeps $(LIB) + +postdeps: + @for lib in $(SPLIB-y) ; do \ + $(MAKE) -C `dirname $$lib` all ; \ + done # generic POST library $(GPLIB): $(obj).depend $(OBJS) From 65e43a10631537dcb92c302d36301a12308216c3 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sat, 13 Dec 2008 17:20:27 -0600 Subject: [PATCH 040/188] Introduce virt_to_phys() virt_to_phys() returns the physical address given a virtual. In most cases this will be just the input value as the vast majority of systems run in a 1:1 mode. However in systems that are not running this way it should report the physical address or ~0 if no mapping exists for the given virtual address. Signed-off-by: Kumar Gala --- include/asm-arm/io.h | 5 +++++ include/asm-avr32/io.h | 5 +++++ include/asm-blackfin/io.h | 5 +++++ include/asm-i386/io.h | 5 +++++ include/asm-m68k/io.h | 5 +++++ include/asm-microblaze/io.h | 5 +++++ include/asm-mips/io.h | 2 +- include/asm-nios/io.h | 5 +++++ include/asm-nios2/io.h | 5 +++++ include/asm-ppc/io.h | 5 +++++ include/asm-sh/io.h | 5 +++++ include/asm-sparc/io.h | 5 +++++ 12 files changed, 56 insertions(+), 1 deletion(-) diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index f4ae30700..fec3a7eac 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -57,6 +57,11 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) } +static inline phys_addr_t virt_to_phys(void * vaddr) +{ + return (phys_addr_t)(vaddr); +} + /* * Generic virtual read/write. Note that we don't support half-word * read/writes. We define __arch_*[bl] here, and leave __arch_*w diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h index 06e52b137..d22cd3561 100644 --- a/include/asm-avr32/io.h +++ b/include/asm-avr32/io.h @@ -125,4 +125,9 @@ static inline void unmap_physmem(void *vaddr, unsigned long len) } +static inline phys_addr_t virt_to_phys(void * vaddr) +{ + return (phys_addr_t)(vaddr); +} + #endif /* __ASM_AVR32_IO_H */ diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index da5891498..680649498 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -64,6 +64,11 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) } +static inline phys_addr_t virt_to_phys(void * vaddr) +{ + return (phys_addr_t)(vaddr); +} + /* * These are for ISA/PCI shared memory _only_ and should never be used * on any other type of memory, including Zorro memory. They are meant to diff --git a/include/asm-i386/io.h b/include/asm-i386/io.h index 2c57140fb..9b757d489 100644 --- a/include/asm-i386/io.h +++ b/include/asm-i386/io.h @@ -229,4 +229,9 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) } +static inline phys_addr_t virt_to_phys(void * vaddr) +{ + return (phys_addr_t)(vaddr); +} + #endif diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h index 1fccc1292..50ea08751 100644 --- a/include/asm-m68k/io.h +++ b/include/asm-m68k/io.h @@ -251,4 +251,9 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) } +static inline phys_addr_t virt_to_phys(void * vaddr) +{ + return (phys_addr_t)(vaddr); +} + #endif /* __ASM_M68K_IO_H__ */ diff --git a/include/asm-microblaze/io.h b/include/asm-microblaze/io.h index 8804724bf..7e190d15c 100644 --- a/include/asm-microblaze/io.h +++ b/include/asm-microblaze/io.h @@ -155,4 +155,9 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) } +static inline phys_addr_t virt_to_phys(void * vaddr) +{ + return (phys_addr_t)(vaddr); +} + #endif /* __MICROBLAZE_IO_H__ */ diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 3a0f33f20..031186d03 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -118,7 +118,7 @@ static inline void set_io_port_base(unsigned long base) * Change virtual addresses to physical addresses and vv. * These are trivial on the 1:1 Linux/MIPS mapping */ -extern inline unsigned long virt_to_phys(volatile void * address) +extern inline phys_addr_t virt_to_phys(void * address) { return CPHYSADDR(address); } diff --git a/include/asm-nios/io.h b/include/asm-nios/io.h index 8b788068b..899682cc4 100644 --- a/include/asm-nios/io.h +++ b/include/asm-nios/io.h @@ -133,4 +133,9 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) } +static inline phys_addr_t virt_to_phys(void * vaddr) +{ + return (phys_addr_t)(vaddr); +} + #endif /* __ASM_NIOS_IO_H_ */ diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h index 2f1ec26bd..01d11efec 100644 --- a/include/asm-nios2/io.h +++ b/include/asm-nios2/io.h @@ -53,6 +53,11 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) } +static inline phys_addr_t virt_to_phys(void * vaddr) +{ + return (phys_addr_t)(vaddr); +} + extern unsigned char inb (unsigned char *port); extern unsigned short inw (unsigned short *port); extern unsigned inl (unsigned port); diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index c3496818f..c00de452d 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -298,4 +298,9 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) } +static inline phys_addr_t virt_to_phys(void * vaddr) +{ + return (phys_addr_t)(vaddr); +} + #endif diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h index adc3f81ed..ca598a60f 100644 --- a/include/asm-sh/io.h +++ b/include/asm-sh/io.h @@ -261,5 +261,10 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) } +static inline phys_addr_t virt_to_phys(void * vaddr) +{ + return (phys_addr_t)(vaddr); +} + #endif /* __KERNEL__ */ #endif /* __ASM_SH_IO_H */ diff --git a/include/asm-sparc/io.h b/include/asm-sparc/io.h index 5f8d05cc3..0c5d86cb3 100644 --- a/include/asm-sparc/io.h +++ b/include/asm-sparc/io.h @@ -90,4 +90,9 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) } +static inline phys_addr_t virt_to_phys(void * vaddr) +{ + return (phys_addr_t)(vaddr); +} + #endif From 63240ba88cd6a220057a0f28e5bf97f5b17ac84b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sat, 13 Dec 2008 17:20:28 -0600 Subject: [PATCH 041/188] Introduce addr_map library Add a library that helps in translating between virtual and physical addresses. This library can be useful as a simple means to implement map_physmem() and virt_to_phys() for platforms that need functionality beyond the simple 1:1 mapping. Signed-off-by: Kumar Gala --- include/addr_map.h | 29 +++++++++++++++ lib_generic/Makefile | 1 + lib_generic/addr_map.c | 81 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 111 insertions(+) create mode 100644 include/addr_map.h create mode 100644 lib_generic/addr_map.c diff --git a/include/addr_map.h b/include/addr_map.h new file mode 100644 index 000000000..d55f5f64e --- /dev/null +++ b/include/addr_map.h @@ -0,0 +1,29 @@ +#ifndef __ADDR_MAP_H +#define __ADDR_MAP_H + +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +extern phys_addr_t addrmap_virt_to_phys(void *vaddr); +extern unsigned long addrmap_phys_to_virt(phys_addr_t paddr); +extern void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr, + phys_size_t size, int idx); + +#endif diff --git a/lib_generic/Makefile b/lib_generic/Makefile index d62c39bef..3f040226e 100644 --- a/lib_generic/Makefile +++ b/lib_generic/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libgeneric.a +COBJS-$(CONFIG_ADDR_MAP) += addr_map.o COBJS-y += bzlib.o COBJS-y += bzlib_crctable.o COBJS-y += bzlib_decompress.o diff --git a/lib_generic/addr_map.c b/lib_generic/addr_map.c new file mode 100644 index 000000000..ff8532cf1 --- /dev/null +++ b/lib_generic/addr_map.c @@ -0,0 +1,81 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +static struct { + phys_addr_t paddr; + phys_size_t size; + unsigned long vaddr; +} address_map[CONFIG_SYS_NUM_ADDR_MAP]; + +phys_addr_t addrmap_virt_to_phys(void * vaddr) +{ + int i; + + for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++) { + u64 base, upper, addr; + + if (address_map[i].size == 0) + continue; + + addr = (u64)((u32)vaddr); + base = (u64)(address_map[i].vaddr); + upper = (u64)(address_map[i].size) + base - 1; + + if (addr >= base && addr <= upper) { + return addr - address_map[i].vaddr + address_map[i].paddr; + } + } + + return (phys_addr_t)(~0); +} + +unsigned long addrmap_phys_to_virt(phys_addr_t paddr) +{ + int i; + + for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++) { + u64 base, upper, addr; + + if (address_map[i].size == 0) + continue; + + addr = (u64)paddr; + base = (u64)(address_map[i].paddr); + upper = (u64)(address_map[i].size) + base - 1; + + if (addr >= base && addr <= upper) { + return paddr - address_map[i].paddr + address_map[i].vaddr; + } + } + + return (unsigned long)(~0); +} + +void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr, + phys_size_t size, int idx) +{ + if (idx > CONFIG_SYS_NUM_ADDR_MAP) + return; + + address_map[idx].vaddr = vaddr; + address_map[idx].paddr = paddr; + address_map[idx].size = size; +} From e39cd81c44740d7355d277ed3d38536cbe1e003d Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Fri, 5 Dec 2008 15:36:14 +0800 Subject: [PATCH 042/188] lib_ppc: rework the flush_cache - It is possible to miss flush/invalidate the last cache line, we fix it at here. - add the volatile and memory clobber. They are pointed by Scott Wood. Signed-off-by: Dave Liu --- lib_ppc/cache.c | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/lib_ppc/cache.c b/lib_ppc/cache.c index 72c838e41..1292b71e6 100644 --- a/lib_ppc/cache.c +++ b/lib_ppc/cache.c @@ -25,29 +25,27 @@ #include #include -void flush_cache (ulong start_addr, ulong size) +void flush_cache(ulong start_addr, ulong size) { #ifndef CONFIG_5xx - ulong addr, end_addr = start_addr + size; + ulong addr, start, end; - if (CONFIG_SYS_CACHELINE_SIZE) { - addr = start_addr & (CONFIG_SYS_CACHELINE_SIZE - 1); - for (addr = start_addr; - addr < end_addr; - addr += CONFIG_SYS_CACHELINE_SIZE) { - asm ("dcbst 0,%0": :"r" (addr)); - WATCHDOG_RESET(); - } - asm ("sync"); /* Wait for all dcbst to complete on bus */ + start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1); + end = start_addr + size - 1; - for (addr = start_addr; - addr < end_addr; - addr += CONFIG_SYS_CACHELINE_SIZE) { - asm ("icbi 0,%0": :"r" (addr)); - WATCHDOG_RESET(); - } + for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) { + asm volatile("dcbst 0,%0" : : "r" (addr) : "memory"); + WATCHDOG_RESET(); } - asm ("sync"); /* Always flush prefetch queue in any case */ - asm ("isync"); + /* wait for all dcbst to complete on bus */ + asm volatile("sync" : : : "memory"); + + for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) { + asm volatile("icbi 0,%0" : : "r" (addr) : "memory"); + WATCHDOG_RESET(); + } + asm volatile("sync" : : : "memory"); + /* flush prefetch queue */ + asm volatile("isync" : : : "memory"); #endif } From ecf5f077c8e77454f532eaac3e3afb7cfc48c62d Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Wed, 3 Dec 2008 11:28:30 -0600 Subject: [PATCH 043/188] i2c: merge all i2c_reg_read() and i2c_reg_write() into inline functions All implementations of the functions i2c_reg_read() and i2c_reg_write() are identical. We can save space and simplify the code by converting these functions into inlines and putting them in i2c.h. Signed-off-by: Timur Tabi Acked-By: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm920t/at91rm9200/i2c.c | 14 -------- cpu/arm926ejs/davinci/i2c.c | 17 ---------- cpu/blackfin/i2c.c | 16 --------- cpu/mpc512x/i2c.c | 17 ---------- cpu/mpc5xxx/i2c.c | 16 --------- cpu/mpc8220/i2c.c | 16 --------- cpu/mpc824x/drivers/i2c/i2c.c | 14 -------- cpu/mpc8260/i2c.c | 16 --------- cpu/mpc8xx/i2c.c | 33 ------------------- cpu/ppc4xx/i2c.c | 20 ----------- cpu/pxa/i2c.c | 15 --------- drivers/i2c/fsl_i2c.c | 16 --------- drivers/i2c/soft_i2c.c | 19 ----------- include/i2c.h | 62 +++++++++++++++++++++++++++++++++-- 14 files changed, 60 insertions(+), 231 deletions(-) diff --git a/cpu/arm920t/at91rm9200/i2c.c b/cpu/arm920t/at91rm9200/i2c.c index b68c5dd82..9fd72d397 100644 --- a/cpu/arm920t/at91rm9200/i2c.c +++ b/cpu/arm920t/at91rm9200/i2c.c @@ -189,20 +189,6 @@ i2c_init(int speed, int slaveaddr) return; } -uchar i2c_reg_read(uchar i2c_addr, uchar reg) -{ - unsigned char buf; - - i2c_read(i2c_addr, reg, 1, &buf, 1); - - return(buf); -} - -void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write(i2c_addr, reg, 1, &val, 1); -} - int i2c_set_bus_speed(unsigned int speed) { return -1; diff --git a/cpu/arm926ejs/davinci/i2c.c b/cpu/arm926ejs/davinci/i2c.c index d220a4c72..3ba20ef18 100644 --- a/cpu/arm926ejs/davinci/i2c.c +++ b/cpu/arm926ejs/davinci/i2c.c @@ -331,21 +331,4 @@ int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) return(0); } - -u_int8_t i2c_reg_read(u_int8_t chip, u_int8_t reg) -{ - u_int8_t tmp; - - i2c_read(chip, reg, 1, &tmp, 1); - return(tmp); -} - - -void i2c_reg_write(u_int8_t chip, u_int8_t reg, u_int8_t val) -{ - u_int8_t tmp; - - i2c_write(chip, reg, 1, &tmp, 1); -} - #endif /* CONFIG_DRIVER_DAVINCI_I2C */ diff --git a/cpu/blackfin/i2c.c b/cpu/blackfin/i2c.c index 60f03d47a..2a3e2238c 100644 --- a/cpu/blackfin/i2c.c +++ b/cpu/blackfin/i2c.c @@ -425,20 +425,4 @@ int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) } -uchar i2c_reg_read(uchar chip, uchar reg) -{ - uchar buf; - - PRINTD("i2c_reg_read: chip=0x%02x, reg=0x%02x\n", chip, reg); - i2c_read(chip, reg, 0, &buf, 1); - return (buf); -} - -void i2c_reg_write(uchar chip, uchar reg, uchar val) -{ - PRINTD("i2c_reg_write: chip=0x%02x, reg=0x%02x, val=0x%02x\n", chip, - reg, val); - i2c_write(chip, reg, 0, &val, 1); -} - #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc512x/i2c.c b/cpu/mpc512x/i2c.c index 77a6f0dc4..4f6bc8640 100644 --- a/cpu/mpc512x/i2c.c +++ b/cpu/mpc512x/i2c.c @@ -382,23 +382,6 @@ Done: return ret; } -uchar i2c_reg_read (uchar chip, uchar reg) -{ - uchar buf; - - i2c_read (chip, reg, 1, &buf, 1); - - return buf; -} - -void i2c_reg_write (uchar chip, uchar reg, uchar val) -{ - i2c_write (chip, reg, 1, &val, 1); - - return; -} - - int i2c_set_bus_num (unsigned int bus) { if (bus >= I2C_BUS_CNT) { diff --git a/cpu/mpc5xxx/i2c.c b/cpu/mpc5xxx/i2c.c index 4d16bbe77..7d76274ad 100644 --- a/cpu/mpc5xxx/i2c.c +++ b/cpu/mpc5xxx/i2c.c @@ -380,20 +380,4 @@ Done: return ret; } -uchar i2c_reg_read(uchar chip, uchar reg) -{ - uchar buf; - - i2c_read(chip, reg, 1, &buf, 1); - - return buf; -} - -void i2c_reg_write(uchar chip, uchar reg, uchar val) -{ - i2c_write(chip, reg, 1, &val, 1); - - return; -} - #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc8220/i2c.c b/cpu/mpc8220/i2c.c index d67936dc3..76ecdf11e 100644 --- a/cpu/mpc8220/i2c.c +++ b/cpu/mpc8220/i2c.c @@ -387,20 +387,4 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buf, int len) return ret; } -uchar i2c_reg_read (uchar chip, uchar reg) -{ - uchar buf; - - i2c_read (chip, reg, 1, &buf, 1); - - return buf; -} - -void i2c_reg_write (uchar chip, uchar reg, uchar val) -{ - i2c_write (chip, reg, 1, &val, 1); - - return; -} - #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc824x/drivers/i2c/i2c.c b/cpu/mpc824x/drivers/i2c/i2c.c index 854345e14..637ae4c1b 100644 --- a/cpu/mpc824x/drivers/i2c/i2c.c +++ b/cpu/mpc824x/drivers/i2c/i2c.c @@ -267,18 +267,4 @@ int i2c_probe (uchar chip) return i2c_read (chip, 0, 1, (uchar *) &tmp, 1); } -uchar i2c_reg_read (uchar i2c_addr, uchar reg) -{ - uchar buf[1]; - - i2c_read (i2c_addr, reg, 1, buf, 1); - - return (buf[0]); -} - -void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write (i2c_addr, reg, 1, &val, 1); -} - #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c index c12463994..35cf8f143 100644 --- a/cpu/mpc8260/i2c.c +++ b/cpu/mpc8260/i2c.c @@ -753,22 +753,6 @@ i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) return 0; } -uchar -i2c_reg_read(uchar chip, uchar reg) -{ - uchar buf; - - i2c_read(chip, reg, 1, &buf, 1); - - return (buf); -} - -void -i2c_reg_write(uchar chip, uchar reg, uchar val) -{ - i2c_write(chip, reg, 1, &val, 1); -} - #if defined(CONFIG_I2C_MULTI_BUS) /* * Functions for multiple I2C bus handling diff --git a/cpu/mpc8xx/i2c.c b/cpu/mpc8xx/i2c.c index 29c7c71bb..338cababe 100644 --- a/cpu/mpc8xx/i2c.c +++ b/cpu/mpc8xx/i2c.c @@ -42,19 +42,6 @@ DECLARE_GLOBAL_DATA_PTR; /* define to enable debug messages */ #undef DEBUG_I2C -/*----------------------------------------------------------------------- - * Set default values - */ -#ifndef CONFIG_SYS_I2C_SPEED -#define CONFIG_SYS_I2C_SPEED 50000 -#endif - -#ifndef CONFIG_SYS_I2C_SLAVE -#define CONFIG_SYS_I2C_SLAVE 0xFE -#endif -/*----------------------------------------------------------------------- - */ - /* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */ #define TOUT_LOOP 1000000 @@ -717,24 +704,4 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) return 0; } -uchar -i2c_reg_read(uchar i2c_addr, uchar reg) -{ - uchar buf; - - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - i2c_read(i2c_addr, reg, 1, &buf, 1); - - return (buf); -} - -void -i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) -{ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - i2c_write(i2c_addr, reg, 1, &val, 1); -} - #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c index 9073ee240..9d416ca5e 100644 --- a/cpu/ppc4xx/i2c.c +++ b/cpu/ppc4xx/i2c.c @@ -419,26 +419,6 @@ int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) return (i2c_transfer(0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0); } -/*----------------------------------------------------------------------- - * Read a register - */ -uchar i2c_reg_read(uchar i2c_addr, uchar reg) -{ - uchar buf; - - i2c_read(i2c_addr, reg, 1, &buf, 1); - - return (buf); -} - -/*----------------------------------------------------------------------- - * Write a register - */ -void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write(i2c_addr, reg, 1, &val, 1); -} - #if defined(CONFIG_I2C_MULTI_BUS) /* * Functions for multiple I2C bus handling diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c index 08042be1c..6b72ba13a 100644 --- a/cpu/pxa/i2c.c +++ b/cpu/pxa/i2c.c @@ -455,19 +455,4 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) } -uchar i2c_reg_read (uchar chip, uchar reg) -{ - uchar buf; - - PRINTD(("i2c_reg_read(chip=0x%02x, reg=0x%02x)\n",chip,reg)); - i2c_read(chip, reg, 1, &buf, 1); - return (buf); -} - -void i2c_reg_write(uchar chip, uchar reg, uchar val) -{ - PRINTD(("i2c_reg_write(chip=0x%02x, reg=0x%02x, val=0x%02x)\n",chip,reg,val)); - i2c_write(chip, reg, 1, &val, 1); -} - #endif /* CONFIG_HARD_I2C */ diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 3b5c06ba6..ce646fd7e 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -367,22 +367,6 @@ i2c_probe(uchar chip) return i2c_read(chip, 0, 0, NULL, 0); } -uchar -i2c_reg_read(uchar i2c_addr, uchar reg) -{ - uchar buf[1]; - - i2c_read(i2c_addr, reg, 1, buf, 1); - - return buf[0]; -} - -void -i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write(i2c_addr, reg, 1, &val, 1); -} - int i2c_set_bus_num(unsigned int bus) { #ifdef CONFIG_SYS_I2C2_OFFSET diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index d2a51426e..f12dedf89 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -435,22 +435,3 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) return(failures); } -/*----------------------------------------------------------------------- - * Read a register - */ -uchar i2c_reg_read(uchar i2c_addr, uchar reg) -{ - uchar buf; - - i2c_read(i2c_addr, reg, 1, &buf, 1); - - return(buf); -} - -/*----------------------------------------------------------------------- - * Write a register - */ -void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) -{ - i2c_write(i2c_addr, reg, 1, &val, 1); -} diff --git a/include/i2c.h b/include/i2c.h index 8d6f86742..fad2d5716 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -76,6 +76,20 @@ # define I2C_SOFT_DECLARATIONS # endif #endif + +#ifdef CONFIG_8xx +/* Set default values for the I2C bus speed and slave address on 8xx. In the + * future, we'll define these in all 8xx board config files. + */ +#ifndef CONFIG_SYS_I2C_SPEED +#define CONFIG_SYS_I2C_SPEED 50000 +#endif + +#ifndef CONFIG_SYS_I2C_SLAVE +#define CONFIG_SYS_I2C_SLAVE 0xFE +#endif +#endif + /* * Initialization, must be called once on start up, may be called * repeatedly to change the speed and slave addresses. @@ -132,8 +146,52 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); /* * Utility routines to read/write registers. */ -uchar i2c_reg_read (uchar chip, uchar reg); -void i2c_reg_write(uchar chip, uchar reg, uchar val); +static inline u8 i2c_reg_read(u8 addr, u8 reg) +{ + u8 buf; + +#ifdef CONFIG_8xx + /* MPC8xx needs this. Maybe one day we can get rid of it. */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + +#ifdef DEBUG + printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg); +#endif + +#ifdef CONFIG_BLACKFIN + /* This ifdef will become unneccessary in a future version of the + * blackfin I2C driver. + */ + i2c_read(addr, reg, 0, &buf, 1); +#else + i2c_read(addr, reg, 1, &buf, 1); +#endif + + return buf; +} + +static inline void i2c_reg_write(u8 addr, u8 reg, u8 val) +{ +#ifdef CONFIG_8xx + /* MPC8xx needs this. Maybe one day we can get rid of it. */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + +#ifdef DEBUG + printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n", + __func__, addr, reg, val); +#endif + +#ifdef CONFIG_BLACKFIN + /* This ifdef will become unneccessary in a future version of the + * blackfin I2C driver. + */ + i2c_write(addr, reg, 0, &val, 1); +#else + i2c_write(addr, reg, 1, &val, 1); +#endif +} /* * Functions for setting the current I2C bus and its speed From 5b3375ac8c36c29c87abb132fede0509eb21e5c9 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 11 Dec 2008 06:23:37 -0500 Subject: [PATCH 044/188] env_sf: support embedded environments If both CONFIG_ENV_SECT_SIZE and CONFIG_ENV_SIZE are defined, and the sect size is larger than the env size, then it means the env is embedded in a block. So we have to save/restore the part of the sector which is not the environment. Previously, saving the environment in SPI flash in this setup would probably brick the board as the rest of the sector tends to contain actual U-Boot data/code. Signed-off-by: Mike Frysinger Acked-by: Haavard Skinnemoen --- common/env_sf.c | 41 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 5 deletions(-) diff --git a/common/env_sf.c b/common/env_sf.c index 1bbf93fdf..2f52e2561 100644 --- a/common/env_sf.c +++ b/common/env_sf.c @@ -27,6 +27,7 @@ */ #include #include +#include #include #ifndef CONFIG_ENV_SPI_BUS @@ -60,13 +61,30 @@ uchar env_get_char_spec(int index) int saveenv(void) { + u32 saved_size, saved_offset; + char *saved_buffer = NULL; u32 sector = 1; + int ret; if (!env_flash) { puts("Environment SPI flash not initialized\n"); return 1; } + /* Is the sector larger than the env (i.e. embedded) */ + if (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) { + saved_size = CONFIG_ENV_SECT_SIZE - CONFIG_ENV_SIZE; + saved_offset = CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE; + saved_buffer = malloc(saved_size); + if (!saved_buffer) { + ret = 1; + goto done; + } + ret = spi_flash_read(env_flash, saved_offset, saved_size, saved_buffer); + if (ret) + goto done; + } + if (CONFIG_ENV_SIZE > CONFIG_ENV_SECT_SIZE) { sector = CONFIG_ENV_SIZE / CONFIG_ENV_SECT_SIZE; if (CONFIG_ENV_SIZE % CONFIG_ENV_SECT_SIZE) @@ -74,15 +92,28 @@ int saveenv(void) } puts("Erasing SPI flash..."); - if (spi_flash_erase(env_flash, CONFIG_ENV_OFFSET, sector * CONFIG_ENV_SECT_SIZE)) - return 1; + ret = spi_flash_erase(env_flash, CONFIG_ENV_OFFSET, sector * CONFIG_ENV_SECT_SIZE); + if (ret) + goto done; puts("Writing to SPI flash..."); - if (spi_flash_write(env_flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, env_ptr)) - return 1; + ret = spi_flash_write(env_flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, env_ptr); + if (ret) + goto done; + if (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) { + ret = spi_flash_write(env_flash, saved_offset, saved_size, saved_buffer); + if (ret) + goto done; + } + + ret = 0; puts("done\n"); - return 0; + + done: + if (saved_buffer) + free(saved_buffer); + return ret; } void env_relocate_spec(void) From 84bc72d90c505fec3ef4b693995407a0bd4064e5 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 11 Dec 2008 18:39:08 -0500 Subject: [PATCH 045/188] spi/stmicro: fix debug() display of cmd The stmicro_wait_ready() func tries to show the actual opcode that was sent to the device, but instead it displays the array pointer. Fix it to pull out the opcode from the start of the array. Signed-off-by: Mike Frysinger --- drivers/mtd/spi/stmicro.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c index b8b835a3f..86324e4e1 100644 --- a/drivers/mtd/spi/stmicro.c +++ b/drivers/mtd/spi/stmicro.c @@ -137,7 +137,7 @@ static int stmicro_wait_ready(struct spi_flash *flash, unsigned long timeout) ret = spi_xfer(spi, 32, &cmd[0], NULL, SPI_XFER_BEGIN); if (ret) { - debug("SF: Failed to send command %02x: %d\n", cmd, ret); + debug("SF: Failed to send command %02x: %d\n", cmd[0], ret); return ret; } From 455ae7e87f67c44e6aea68865c83acadd3fcd36c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 16 Dec 2008 01:02:17 +0100 Subject: [PATCH 046/188] Coding style cleanup, update CHANGELOG. Signed-off-by: Wolfgang Denk --- CHANGELOG | 2668 ++++++++++++++++++++++++++++++++ board/afeb9260/partition.c | 1 - common/cmd_ubi.c | 2 +- cpu/mcf52x2/cpu_init.c | 2 +- cpu/mpc86xx/start.S | 2 - cpu/ppc4xx/cpu.c | 1 - cpu/ppc4xx/start.S | 2 +- drivers/i2c/soft_i2c.c | 1 - drivers/mtd/ubi/crc32.c | 2 +- drivers/mtd/ubi/io.c | 2 +- drivers/mtd/ubi/vmt.c | 2 +- include/configs/PMC440.h | 2 +- include/configs/afeb9260.h | 1 - include/linux/crc32.h | 8 +- include/linux/mtd/partitions.h | 6 +- include/linux/mtd/ubi.h | 2 +- include/ubi_uboot.h | 2 +- 17 files changed, 2684 insertions(+), 22 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 592697887..0c9c0479c 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,2671 @@ +commit 84bc72d90c505fec3ef4b693995407a0bd4064e5 +Author: Mike Frysinger +Date: Thu Dec 11 18:39:08 2008 -0500 + + spi/stmicro: fix debug() display of cmd + + The stmicro_wait_ready() func tries to show the actual opcode that was sent + to the device, but instead it displays the array pointer. Fix it to pull + out the opcode from the start of the array. + + Signed-off-by: Mike Frysinger + +commit 5b3375ac8c36c29c87abb132fede0509eb21e5c9 +Author: Mike Frysinger +Date: Thu Dec 11 06:23:37 2008 -0500 + + env_sf: support embedded environments + + If both CONFIG_ENV_SECT_SIZE and CONFIG_ENV_SIZE are defined, and the sect + size is larger than the env size, then it means the env is embedded in a + block. So we have to save/restore the part of the sector which is not the + environment. Previously, saving the environment in SPI flash in this + setup would probably brick the board as the rest of the sector tends to + contain actual U-Boot data/code. + + Signed-off-by: Mike Frysinger + Acked-by: Haavard Skinnemoen + +commit ecf5f077c8e77454f532eaac3e3afb7cfc48c62d +Author: Timur Tabi +Date: Wed Dec 3 11:28:30 2008 -0600 + + i2c: merge all i2c_reg_read() and i2c_reg_write() into inline functions + + All implementations of the functions i2c_reg_read() and + i2c_reg_write() are identical. We can save space and simplify the + code by converting these functions into inlines and putting them in + i2c.h. + + Signed-off-by: Timur Tabi + Acked-By: Jean-Christophe PLAGNIOL-VILLARD + +commit e39cd81c44740d7355d277ed3d38536cbe1e003d +Author: Dave Liu +Date: Fri Dec 5 15:36:14 2008 +0800 + + lib_ppc: rework the flush_cache + + - It is possible to miss flush/invalidate the last + cache line, we fix it at here. + - add the volatile and memory clobber. + + They are pointed by Scott Wood. + + Signed-off-by: Dave Liu + +commit 63240ba88cd6a220057a0f28e5bf97f5b17ac84b +Author: Kumar Gala +Date: Sat Dec 13 17:20:28 2008 -0600 + + Introduce addr_map library + + Add a library that helps in translating between virtual and physical + addresses. This library can be useful as a simple means to implement + map_physmem() and virt_to_phys() for platforms that need functionality + beyond the simple 1:1 mapping. + + Signed-off-by: Kumar Gala + +commit 65e43a10631537dcb92c302d36301a12308216c3 +Author: Kumar Gala +Date: Sat Dec 13 17:20:27 2008 -0600 + + Introduce virt_to_phys() + + virt_to_phys() returns the physical address given a virtual. In most + cases this will be just the input value as the vast majority of + systems run in a 1:1 mode. + + However in systems that are not running this way it should report the + physical address or ~0 if no mapping exists for the given virtual + address. + + Signed-off-by: Kumar Gala + +commit 45845301af3de8675c1f7bbc815c6de35452605a +Author: Yuri Tikhonov +Date: Sun Dec 7 22:12:50 2008 +0100 + + POST Make: fix the sub-dir dependencies missing. + + Signed-off-by: Yuri Tikhonov + +commit 22525779cb51f1bbe4e96fea7b778de1935a5a69 +Author: Martin Michlmayr +Date: Wed Aug 6 14:44:05 2008 +0300 + + Fix a typo in fw_env.config + + Reported-by: Martin Michlmayr + Signed-off-by: Wolfgang Denk + +commit ba490b7761c62b549c222a9723e532dc801a3899 +Author: Peter Tyser +Date: Mon Dec 1 16:22:45 2008 -0600 + + Remove unused CONFIG_ADDR_STREAMING defines + + Signed-off-by: Peter Tyser + +commit d16da93430520d3e46c1ab52eedacf36ab7a2311 +Author: Peter Tyser +Date: Mon Nov 24 11:54:47 2008 -0600 + + cmd_mem: Remove unused variable + + Signed-off-by: Peter Tyser + +commit 3aed3aa2c128ce9fb39ca3f4e9385a7499e93dbf +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sun Dec 14 10:29:39 2008 +0100 + + Fix new found CFG_ + + Also fix some minor typos. + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Wolfgang Denk + +commit 0e0c862efe7279e9609db74d758cd1b84c6c7209 +Author: Sergei Poselenov +Date: Fri Sep 19 12:07:34 2008 +0200 + + Remove compiler warning: target CPU does not support interworking + + This warning is issued by modern ARM-EABI GCC on non-thumb targets. + + Signed-off-by: Vladimir Panfilov + Signed-off-by: Sergei Poselenov + +commit cd6734510a9ff0f41c4a73567d4080ea0033d2c1 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Mon Nov 24 13:33:51 2008 +0100 + + Fix FIT and FDT support to have CONFIG_OF_LIBFDT and CONFIG_FIT independent + + FDT support is used for both FIT style images and for architectures + that can pass a fdt blob to an OS (ppc, m68k, sparc). + + For other architectures and boards which do not pass a fdt blob to an + OS but want to use the new uImage format, we just need FIT support. + + Now we can have the 4 following configurations : + + 1) FIT only CONFIG_FIT + 2) fdt blob only CONFIG_OF_LIBFDT + 3) both CONFIG_OF_LIBFDT & CONFIG_FIT + 4) none none + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 19ef4f7a6ef3b725aa9fe4b4f5fb676a84160172 +Author: Matthias Fuchs +Date: Wed Dec 10 15:13:32 2008 +0100 + + ppc4xx: Disable EEPROM write access on PMC440 boards + + This patch disables EEPROM wrtie access by default on PMC440 board. + + Signed-off-by: Matthias Fuchs + +commit 5b67a1439a73ba6c34007d9ff60a2c6aa90265df +Author: Matthias Fuchs +Date: Wed Dec 10 15:12:56 2008 +0100 + + ppc4xx: Fix Ethernet PHY LED configuration on PMC440 boards + + Signed-off-by: Matthias Fuchs + +commit 71fa0714fe5134bc8718c38d5261d267e88582ba +Author: Stefan Roese +Date: Tue Nov 18 16:36:12 2008 +0100 + + MIPS: Flush data cache upon relocation + + This patch now adds a flush to the data cache upon relocation. The + current implementation is missing this. Only a comment states that it + should be done. So let's really do it now. + + Signed-off-by: Stefan Roese + Signed-off-by: Shinya Kuribayashi + +commit 44174343688dba32571a34550dba08971c65fef1 +Author: Stefan Roese +Date: Tue Nov 18 16:36:22 2008 +0100 + + MIPS: Add CONFIG_SKIP_LOWLEVEL_INIT + + This patch adds the CONFIG_SKIP_LOWLEVEL_INIT option to start.S. This + enables support for boards where the lowlevel initialization is + already done when U-Boot runs (e.g. via OnChip ROM). + + This will be used in the upcoming VCTH board support. + + Signed-off-by: Stefan Roese + Signed-off-by: Shinya Kuribayashi + +commit db08ecaa6eb8176904b3bae103a85ee8f735dc40 +Author: Stefan Roese +Date: Wed Nov 12 13:18:02 2008 +0100 + + MIPS: Add board_early_init_f() to init_sequence + + This patch adds the board_early_init_f() call to the MIPS init + sequence. A weak dummy implementation is also added which can be + overridden by a board specific version. + + This will be used by the upcoming VCTH board support. + + Signed-off-by: Stefan Roese + Signed-off-by: Shinya Kuribayashi + +commit 9d23fc584c4b7b8bb9ecbee48920b1b04b08fa1b +Author: Stefan Roese +Date: Wed Nov 12 13:18:19 2008 +0100 + + MIPS: Add onenand_init() to board.c and move nand_init() + + This patch adds a call to onenand_init() for OneNAND support and moves + the nand_init() call to an earlier place, so that the environment can + be used from NAND and OneNAND. + + Signed-off-by: Stefan Roese + Signed-off-by: Shinya Kuribayashi + +commit d8bbc51c7ba9b737a20984333d19fe28a3526431 +Author: Nobuhiro Iwamatsu +Date: Tue Dec 9 11:32:46 2008 +0900 + + sh: Update sh2/sh2a timer + + Renesas SH2/SH2A timer broken. + This patch fix timer function. + + Signed-off-by: Nobuhiro Iwamatsu + Signed-off-by: Nobuhiro Iwamatsu + +commit a319f1496210117b73198e3d889ffffaf6825d00 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Fri Dec 5 07:27:37 2008 +0100 + + sh: r2dplus fix register access + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Nobuhiro Iwamatsu + +commit 4d4a96055f6917335a89dbdf2e5556fa5ac329f6 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Tue Dec 2 07:40:03 2008 +0100 + + sh: r2dplus/lowlevel_init: coding style fix + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Nobuhiro Iwamatsu + +commit c54b9a42d8f5ab5b2a039b3a2e6fde8b427745e5 +Author: Nobuhiro Iwamatsu +Date: Tue Nov 25 11:05:19 2008 +0900 + + sh: Changed value of CACHE_OC_NUM_ENTRIES and CACHE_OC_WAY_SHIFT + + SH4 is different a value of CACHE_OC_NUM_ENTRIES and + CACHE_OC_WAY_SHIFT every CPU. + This patch corrects these values. + + Signed-off-by: Nobuhiro Iwamatsu + Signed-off-by: Nobuhiro Iwamatsu + +commit e9d5f35497885b3c65d494d09a525d443dcccd3b +Author: Nobuhiro Iwamatsu +Date: Thu Nov 20 16:44:42 2008 +0900 + + sh: Update sh timer function + + Change to write/readX function and fix timer problem. + + Signed-off-by: Nobuhiro Iwamatsu + Signed-off-by: Nobuhiro Iwamatsu + +commit b81786cff476c41e332eaeb679158f6527cd67d4 +Author: Nobuhiro Iwamatsu +Date: Tue Nov 4 11:58:58 2008 +0900 + + sh: Migo-R: Update BSC value + + A value of BSC CS4 was wrong, Fixed it. + + Signed-off-by: Nobuhiro Iwamatsu + Signed-off-by: Nobuhiro Iwamatsu + +commit 5783758fd260a02f44566ad8f29f899565cd0403 +Author: Nobuhiro Iwamatsu +Date: Mon Nov 17 16:52:09 2008 +0900 + + sh: Update ms7722se board config + + Signed-off-by: Nobuhiro Iwamatsu + Signed-off-by: Nobuhiro Iwamatsu + +commit 15e2697c9f7fb2ba672a1a70f07cd6d9d4e92b51 +Author: Nobuhiro Iwamatsu +Date: Mon Nov 17 16:53:09 2008 +0900 + + sh: Update SuperH serial driver + + The address of SCFSR register is wrong at SH7720/SH7721. + This patch fix this. + + Signed-off-by: Nobuhiro Iwamatsu + Signed-off-by: Nobuhiro Iwamatsu + +commit 9a1d3557dcd47365c12eeab584b822e57d994352 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Tue Nov 11 22:20:15 2008 +0100 + + sh: fix rsk7203 and MigoR out of tree build + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Nobuhiro Iwamatsu + +commit 1951f847f0a851853871b613ad7cf21a5242226c +Author: Matthias Fuchs +Date: Wed Dec 10 14:41:25 2008 +0100 + + ppc4xx: Update TEXT_BASE for CPCI405 boards + + This patch fixes building U-Boot for CPCI405 boards. + + Signed-off-by: Matthias Fuchs + Signed-off-by: Stefan Roese + +commit 8c92af7b2fbd60ae87379477f93c7ec9441b7452 +Author: Stefan Roese +Date: Tue Dec 9 20:08:01 2008 +0100 + + ppc4xx: Remove some features from ALPR to fit into 256k again + + Signed-off-by: Stefan Roese + +commit 3b089e4f889a2902449d55e081c886ae607cae89 +Author: Stefan Roese +Date: Wed Dec 10 10:32:59 2008 +0100 + + UBI: Set ubi_dev.type back to DEV_TYPE_NONE upon failing initialization + + With this patch we set the type back to NONE upon failing UBI partition + initialization. Otherwise further calls to the UBI subsystem would try + to really access the non-existing UBI partition. + + Thanks to Michael Lawnick for pointing this out. + + Signed-off-by: Stefan Roese + +commit 817329351639a8895cd9b87b33aeff043f3d5a44 +Author: Stefan Roese +Date: Wed Dec 10 10:28:33 2008 +0100 + + UBI: Return -ENOMEM upon failing malloc + + Return with correct error code (-ENOMEM) from ubi_attach_mtd_dev() upon + failing malloc(). + + Signed-off-by: Stefan Roese + +commit 2145188bea2df8f2b47a87ec3071b55027e8d0ae +Author: Ben Warren +Date: Tue Dec 9 23:34:15 2008 -0800 + + Fix compile error in building MBX860T. + + Signed-off-by: Ben Warren + +commit 8fab49ea911fe925392fa5afcc9bc7373a3d0cee +Author: Michal Simek +Date: Tue Nov 25 11:42:20 2008 +0100 + + microblaze: Remove XUPV2P board + + --- + + Microblaze platforms use generic settings and to have + many platforms is confusing that's why I decided to remove this + platform from U-BOOT. ml401 tree is sufficient for covering + all Microblaze platforms. + + This change will go through microblaze custodian tree. + +commit 99ba6f353582720defff6e6e6761dc455a207d31 +Author: Michal Simek +Date: Mon Nov 24 18:25:41 2008 +0100 + + microblaze: Remove CONFIG_LIBFDT due to error in common files + +commit e7d591e823a991513833af7030468409e25a3b13 +Author: Michal Simek +Date: Mon Nov 24 11:43:00 2008 +0100 + + microblaze: Fix ml401 uart16550 setting + + Signed-off-by: Michal Simek + +commit c85ff0553a8cfbcca51c15b947e1ed55d3810a39 +Author: Michal Simek +Date: Mon Nov 24 11:38:22 2008 +0100 + + microblaze: Set up relocation is done + +commit bcb6dd9187d4b23c748704767bd12d20c829e996 +Author: Mike Frysinger +Date: Tue Dec 9 23:20:31 2008 -0500 + + tools/netconsole: new script for working with netconsole over UDP + + While the doc/README.NetConsole does have a snippet for people to + create their own netcat script, it's a lot easier to make a simple + dedicated script and tell people to use it. + + Also spruce it up a bit to make it user friendly. + + Signed-off-by: Mike Frysinger + +commit 8c5170a7d088601d5f30d85093388dab1f1e8ec0 +Author: Sonic Zhang +Date: Tue Dec 9 23:20:18 2008 -0500 + + fs/fat: handle FAT on SATA + + The FAT file system driver should also handle FAT on SATA devices. + + Signed-off-by: Sonic Zhang + Signed-off-by: Mike Frysinger + +commit 97a24a78ee6f34b89b821cb70eda1cf34aa11d97 +Author: Jerry Van Baren +Date: Mon Nov 24 08:15:02 2008 -0500 + + libfdt: Fix redefined uintptr_t warning for USE_HOSTCC + + Compiling U-Boot in an old OS environment (RedHat-7.3 :-) gives the + following warnings from FDT: + + include/libfdt_env.h:50: warning: redefinition of 'uintptr_t' + /usr/include/stdint.h:129: warning: 'uintptr_t' previously declared here + + Fix: Protect the definition of uintptr_t when compiling on the host + system. + + Signed-off-by: Gerald Van Baren + +commit 1fc2b165c51d6f40c8d505f1b3eaefdb6599b17b +Author: Graeme Russ +Date: Sat Nov 22 08:43:29 2008 +1100 + + Moved sc520 PCI definitions to stand-alone file + + Signed Off By: Graeme Russ + +commit 1f5070c0c18fa5684bfce09c8abdf10c04ed48fa +Author: Graeme Russ +Date: Sat Nov 22 08:43:21 2008 +1100 + + Fixed path to sc520 SSI include file + + Signed Off By: Graeme Russ + +commit d4f70da544c33db3e4fce6473dea4ecca4322545 +Author: Graeme Russ +Date: Fri Nov 21 06:28:05 2008 +1100 + + Fixed build error due to #define of _LINUX_STRING_H_ in 82559_eeprom.c + + Signed-off-by: Graeme Russ + +commit c034075a713b60e654c64e88e87da29440f31bb4 +Author: Stefan Roese +Date: Wed Nov 12 13:30:10 2008 +0100 + + serial: Add vcth UART driver + + This patch adds the UART driver for the upcoming VCTH board support. + + Signed-off-by: Stefan Roese + +commit 142a80ffc3b537a9c45acd2444a42a77f147c602 +Author: Ilya Yanok +Date: Thu Nov 13 19:49:36 2008 +0300 + + jffs2: cache data_crc results + + As we moved data_crc() invocation from jffs2_1pass_build_lists() to + jffs2_1pass_read_inode() data_crc is going to be calculated on each + inode access. This patch adds caching of data_crc() results. There + is no significant improvement in speed (because of flash access + caching added in previous patch I think, crc in RAM is really fast) + but this patch impacts memory usage -- every b_node structure uses + 12 bytes instead of 8. + + Signed-off-by: Alexey Neyman + Signed-off-by: Ilya Yanok + +commit 9b7076229ec6a958bd835ab70745f7676297ce82 +Author: Ilya Yanok +Date: Thu Nov 13 19:49:35 2008 +0300 + + jffs2: summary support + + This patch adds support for reading fs information from summary + node instead of scanning full eraseblock. + + Signed-off-by: Ilya Yanok + +commit 70741004dc28946cd82c7af6789c4ddb3fc94526 +Author: Ilya Yanok +Date: Thu Nov 13 19:49:34 2008 +0300 + + jffs2: add buffer to cache flash accesses + + With this patch JFFS2 code allocates memory buffer of max_totlen size + (size of the largest node, calculated during scan time) and uses it to + store entire node. Speeds up loading. If malloc fails we use old ways + to do things. + + Signed-off-by: Alexey Neyman + Signed-off-by: Ilya Yanok + +commit 8a36d31f72411144ac0412ee7e1880e801acd754 +Author: Ilya Yanok +Date: Thu Nov 13 19:49:33 2008 +0300 + + jffs2: rewrite jffs2 scanning code based on Linux one + + Rewrites jffs2_1pass_build_lists() function in style of Linux's + jffs2_scan_medium() and jffs2_scan_eraseblock(). + This includes: + - Caching flash acceses + - Smart dealing with free space + + Signed-off-by: Alexey Neyman + Signed-off-by: Ilya Yanok + +commit e0b5532579eda8b4629f1b4f6e49c3cc60f52237 +Author: Ilya Yanok +Date: Thu Nov 13 19:49:32 2008 +0300 + + jffs2: add sector_size field to part_info structure + + This patch adds sector_size field to part_info structure (used + by new JFFS2 code). + + Signed-off-by: Ilya Yanok + +commit f73846956778a7dfee83403ef9747aff77198848 +Author: Ilya Yanok +Date: Thu Nov 13 19:49:31 2008 +0300 + + jffs2: fix searching for latest version in jffs2_1pass_list_inodes() + + We need to update i_version inside cycle to find really latest version + inside jffs2_1pass_list_inodes(). With that fixed we can use isize inside + dump_inode() instead of calling expensive jffs2_1pass_read_inode(). + + Signed-off-by: Alexey Neyman + Signed-off-by: Ilya Yanok + +commit 1113cb764b3da256ef8a1f9539f4efbe221ff3c4 +Author: Wolfgang Denk +Date: Tue Dec 9 23:13:51 2008 +0100 + + evb64260: fix "cast to pointer from integer of different size" warnings + + Signed-off-by: Wolfgang Denk + +commit d2776827315c3d469b8cb4cec14d58877798daa2 +Author: Stefan Althoefer +Date: Sun Dec 7 19:39:11 2008 +0100 + + USB: descriptor handling + + Hi, + + I found a bug when working with the u-boot USB subsystem on IXP425 processor + (big endian Xscale aka ARMv5). + I recognized that the second usb_endpoint_descriptor of the attached memory + stick was corrupted. + + The reason for this are the packed structures below (either u-boot and + u-boot-usb): + + -------------- + /* Endpoint descriptor */ + struct usb_endpoint_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned char bEndpointAddress; + unsigned char bmAttributes; + unsigned short wMaxPacketSize; + unsigned char bInterval; + unsigned char bRefresh; + unsigned char bSynchAddress; + + } __attribute__ ((packed)); + /* Interface descriptor */ + struct usb_interface_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned char bInterfaceNumber; + unsigned char bAlternateSetting; + unsigned char bNumEndpoints; + unsigned char bInterfaceClass; + unsigned char bInterfaceSubClass; + unsigned char bInterfaceProtocol; + unsigned char iInterface; + + unsigned char no_of_ep; + unsigned char num_altsetting; + unsigned char act_altsetting; + struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS]; + } __attribute__ ((packed)); + ------------ + + As usb_endpoint_descriptor is only 7byte in length, the start of all + odd ep_desc[] structures is not word aligned. This makes wMaxPacketSize + of these structures also not word aligned. + + ARMv5 Architecture however does not support non-aligned multibyte + data type (see A2.8 of ARM Architecture Reference Manual). + + Signed-off-by: Stefan Althoefer + Signed-off-by: Remy Böhmer + +commit 4c253fdb2a175ea3472c38a1455a16faa58e81f0 +Author: Kumar Gala +Date: Tue Dec 9 10:27:33 2008 -0600 + + drivers/fsl_pci_init: Fix compile warning + + fsl_pci_init.c: In function 'fsl_pci_setup_inbound_windows': + fsl_pci_init.c:122: warning: comparison is always true due to limited range of data type + + The check only makes sense if we are CONFIG_PHYS_64BIT + + Signed-off-by: Kumar Gala + +commit dedacc18a8c2b3951581eb721fa055a4e0ac4845 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sun Dec 7 09:45:35 2008 +0100 + + usbtty/omap: update to current API + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Remy Böhmer + +commit ee2e9ba917a62cc2e3a484bb79c8da0e01cb93ed +Author: Anatolij Gustschin +Date: Tue Dec 9 17:52:05 2008 +0100 + + video: fix FADS823 and RRvision compiling issues + + Since commit 561858ee building for FADS823 and RRvision + doesn't work. Let's include version.h and timestamp.h + unconditionally to fix the problem. + + Signed-off-by: Anatolij Gustschin + +commit 2d2e05727fe4013f807ffa814dff0e75259a1db4 +Author: Stefan Roese +Date: Tue Dec 2 10:53:47 2008 +0100 + + UBI: Fix size parsing in "ubi create" + + Signed-off-by: Stefan Roese + +commit 2ee951ba2ac9874d2a93d52e7a187d3184be937e +Author: Stefan Roese +Date: Thu Nov 27 14:07:09 2008 +0100 + + UBI: Enable re-initializing of the "ubi part" command + + With this patch now, the user can call "ubi part" multiple times to + re-connect the UBI device to another MTD partition. + + Signed-off-by: Stefan Roese + +commit 9def12cae33d2d3ea2dd56b197fd3dfb3ad60bf4 +Author: Stefan Roese +Date: Thu Nov 27 14:05:15 2008 +0100 + + MTD: Fix problem based on non-working relocation (list head mtd_partitions) + + Don't use LIST_HEAD() but initialize the struct via INIT_LIST_HEAD() upon + first call of add_mtd_partitions(). Otherwise this won't work on platforms + where the relocation is broken (like MIPS or PPC). + + Signed-off-by: Stefan Roese + +commit 5e3ab68e9acf9edf304b8aa32ad7e005483a2c47 +Author: Trent Piepho +Date: Wed Nov 12 17:29:48 2008 -0800 + + Section name should be ".data", not "data" + + Signed-off-by: Trent Piepho + Signed-off-by: Wolfgang Denk + +commit 7fa6a2f3b66579dea8bc1a9177646e1141731b15 +Author: Wolfgang Denk +Date: Tue Dec 9 00:39:08 2008 +0100 + + MAKEALL: Automatically use parallel builds + + Add logic to the MAKEALL script to determine the number of CPU cores + on the system, and run a parallel build if there is more than one. + Usually this significantrly accelerates builds. + + Allow to manually adjust the number of parallel make jobs by using + the "BUILD_NCPUS" environment variable. + + Signed-off-by: Wolfgang Denk + +commit 268405fa7c44156c5192a70779920c70906af8d6 +Author: Wolfgang Denk +Date: Tue Dec 9 00:24:30 2008 +0100 + + vxworks.h: Fix build problem introduced by commits 29a4c24d/e9084b23 + + Signed-off-by: Wolfgang Denk + +commit 153176a9414120ca1736f3cc4951623d6e14e6af +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Tue Nov 11 06:08:59 2008 +0100 + + avr32/bootm: remove unused variable 'ret' + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Acked-by: Haavard Skinnemoen + +commit 434c51a5e62f608a2a78ed5398ac43a1c77cc183 +Author: Peter Tyser +Date: Wed Nov 12 13:06:48 2008 -0600 + + Remove unneeded CONFIG_SHELL references + + Make should be using the bash shell by default which makes + CONFIG_SHELL unnecessary + + Signed-off-by: Peter Tyser + +commit cf7a7b99794bac936899819b95539be1dbd71708 +Author: Peter Tyser +Date: Wed Nov 12 12:33:20 2008 -0600 + + Use bash for default GNU Make shell application + + Some Make script commands rely on bash-specific features like brace + expansion, so default to bash for the SHELL variable with a fallback + to the standard sh shell + + Signed-off-by: Peter Tyser + +commit 4b530018764934ad5689196e9aa5714a6f4d1a6c +Author: Heiko Schocher +Date: Wed Nov 12 09:50:45 2008 +0100 + + jffs2: rename devices_init () in common/jffs2.c + + rename devices_init () in common/jffs2.c to + jffs2_devices_init (), because there is also a + devices_init () in common/devices.c. + + Signed-off-by: Heiko Schocher + +commit af5eb847a10f1037590001355d88bab3fe7be48b +Author: Daniel Hellstrom +Date: Mon Nov 10 12:46:20 2008 +0000 + + SPARC: Fixed compiler error introduced by commit c160a9544743 + + This patch fixes a build error for the SPARC platform. It was + introduced by commit c160a9544743e80e8889edb2275538e7764ce334. + + Signed-off-by: Daniel Hellstrom + +commit 4c60259899aa00f59db0d936b8807f9a26411c0f +Author: Gary Jennejohn +Date: Sun Nov 9 12:50:59 2008 +0100 + + mgsuvd add the board-specific part of the HDLC driver + + Signed-off-by: Gary Jennejohn + +commit 534a4359666af48bd69a3743d8a8c2bdb1d3ec70 +Author: Gary Jennejohn +Date: Sun Nov 9 12:45:03 2008 +0100 + + mgcoge add the board-specific part of the HDLC driver + + Signed-off-by: Gary Jennejohn + +commit 135f5534538bb8ea4f38a7030da12187d22ef7e0 +Author: Gary Jennejohn +Date: Sun Nov 9 12:36:15 2008 +0100 + + keymile add the common parts of the HDLC driver + + This implements the ICN protocol used across the backplane and is + needed by all the keymile boards. + + Signed-off-by: Gary Jennejohn + +commit 1cb82a9207a550557399eabc7fe47f21bbd9ddf8 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Fri Nov 7 22:46:22 2008 +0100 + + drivers/bios_emulator: Move conditional compilation to Makefile + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit bcdf1d2cf6b24fb905fd7da80da4b3c65a7995b5 +Author: Richard Retanubun +Date: Thu Nov 6 14:01:51 2008 -0500 + + common/cmd_ide.c: Corrected endian order printing for compact flash serial number. + + Corrected endian order printing for compact flash serial number. + + Signed-off-by: Richard Retanubun + +commit 16a28ef219c27423a1ef502f19070c4d375079b8 +Author: Gary Jennejohn +Date: Thu Nov 6 15:04:23 2008 +0100 + + IOMUX: Add console multiplexing support. + + Modifications to support console multiplexing. This is controlled using + CONFIG_SYS_CONSOLE_MUX in the board configuration file. + + This allows a user to specify multiple console devices in the environment + with a command like this: setenv stdin serial,nc. As a result, the user can + enter text on both the serial and netconsole interfaces. + + All devices - stdin, stdout and stderr - can be set in this manner. + + 1) common/iomux.c and include/iomux.h contain the environment setting + implementation. + 2) doc/README.iomux contains a somewhat more detailed description. + 3) The implementation in (1) is called from common/cmd_nvedit.c to + handle setenv and from common/console.c to handle initialization of + input/output devices at boot time. + 4) common/console.c also contains the code needed to poll multiple console + devices for input and send output to all devices registered for output. + 5) include/common.h includes iomux.h and common/Makefile generates iomux.o + when CONFIG_SYS_CONSOLE_MUX is set. + + Signed-off-by: Gary Jennejohn + +commit 774ce72026f74ac9641bcbbc588b20f2e13f7ab8 +Author: Mike Frysinger +Date: Tue Nov 4 16:03:46 2008 -0500 + + strings: use puts() rather than printf() + + When running `strings` on really long strings, the stack tends to get + smashed due to printf(). Switch to puts() instead since we're only passing + the data through. + + Signed-off-by: Mike Frysinger + +commit b03150b52e3c491a86a3cc0945274f0e8f9872e7 +Author: Niklaus Giger +Date: Mon Nov 3 22:16:18 2008 +0100 + + Use new CONFIG_SYS_VXWORKS parameters for Netstal boards + + Signed-off-by: Niklaus Giger + +commit 29a4c24de99d8cb4ac32991c04cab87ed94ca1f9 +Author: Niklaus Giger +Date: Mon Nov 3 22:15:34 2008 +0100 + + cmd_elf.c: Cleanup bootvx and handle new CONFIG_SYS_VXWORKS parameters + + - fix size too small by one in sprintf + - changed old (pre 2004) device name ibmEmac to emac + - boot device may be overriden in board config + - servername may be defined in board config + - additional parameters may be defined in board config + - fixed some line wrappings + - replaced redundant MAX define by max + + Signed-off-by: Niklaus Giger + +commit e9084b23d16102f44ace24379a1c0c352497ef80 +Author: Niklaus Giger +Date: Mon Nov 3 22:14:36 2008 +0100 + + Add vxworks.h to handle CONFIG_SYS_VXWORKS parameters + + Signed-off-by: Niklaus Giger + +commit 0b2f4ecad473d785959c7976f20d2a00bd0ee01f +Author: Niklaus Giger +Date: Mon Nov 3 22:13:47 2008 +0100 + + README: Document CONFIG_SYS parameters for vxworks + + Signed-off-by: Niklaus Giger + +commit ace514837cac656e29c37a19569cb8ea83071126 +Author: Peter Tyser +Date: Fri Oct 31 11:12:38 2008 -0500 + + lcd: Let the board code show board-specific info cleanup + + remove unneeded version.h from lcd.c + + Signed-off-by: Peter Tyser + Signed-off-by: Wolfgang Denk + +commit 561858ee7d0274c3e89dc98d4d0698cb6fcf6fd9 +Author: Peter Tyser +Date: Mon Nov 3 09:30:59 2008 -0600 + + Update U-Boot's build timestamp on every compile + + Use the GNU 'date' command to auto-generate a new U-Boot + timestamp on every compile. + + Signed-off-by: Peter Tyser + +commit 83ad179e2f0f625b88adb8ef5696709e46fb9077 +Author: Remy Bohmer +Date: Thu Dec 4 22:25:57 2008 +0100 + + Remove redundant armv4 flag from arm926ejs compile flags + + Currently the arm926ejs tree has the armv4 option set during compilation. + This flag does not belong here because a arm926 CPU is always a armv5 CPU. + + Signed-off-by: Remy Bohmer + +commit 89a7a87f084c657f8e32b513a77b50eca07e17ec +Author: Nicolas Ferre +Date: Sat Dec 6 13:11:14 2008 +0100 + + at91: Choose environment variables location within make config target + + This patch adds the possiblity to choose the media where the environment will + be located. This allow to choose this fundamental configuration without editing + config files. + + Documentation file added. + + Signed-off-by: Nicolas Ferre + Acked-by: Stelian Pop + Acked-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 1450c4a6682378567030414a9f1198c39b7730c7 +Author: Anatolij Gustschin +Date: Mon Nov 3 15:30:34 2008 +0100 + + lwmon, tqm8xx: Fix build errors + + Commit 6b59e03e0237a40a2305ea385defdfd92000978b + lcd: Let the board code show board-specific info + + introduced some bugs which prevent U-Boot building + for lwmon board if CONFIG_LCD_INFO_BELOW_LOGO will + be defined in the board configuration. + + Also "LCD enabled" building for TQM823L doesn't work + since this commit. + + This patch fixes above-mentioned issues. + + Signed-off-by: Anatolij Gustschin + +commit bfa0af6b22ff25b0719a8910f9b6d1f975aa6fb0 +Author: Mike Frysinger +Date: Sun Nov 2 01:18:18 2008 -0400 + + ignore .gdb_history files + + When using gdb, history files will often get generated. So ignore them. + + Signed-off-by: Mike Frysinger + +commit c8aa7dfc18f7cc90d0aea6c7becbb67dfc5bba4b +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Fri Oct 31 12:26:55 2008 +0100 + + FPGA: move fpga drivers to drivers/fpga + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 6a86bb6c25376f0358478219fa28d7c84dd01ed0 +Author: Peter Tyser +Date: Mon Dec 1 16:29:38 2008 -0600 + + net: Fix TftpStart() ip:filename bug + + The TftpStart() function modifies the 'BootFile' + string when 'BootFile' contains both an IP address + and filename (eg 1.2.3.4:/path/file). This causes + subsequent calls to TftpStart to incorrectly parse + the TFTP filename and server IP address to use. + For example: + + => tftp 0x100000 10.52.0.62:/home/ptyser/non_existant + Speed: 100, half duplex + Using eTSEC1 device + TFTP from server 10.52.0.62; our IP address is 10.52.253.79 + ^^^^^^^^^^ CORRECT + Filename '/home/ptyser/non_existant'. + ^^^^^^^^^^^^^^^^^^^^^^^^^ CORRECT + Load address: 0x100000 + Loading: * + TFTP error: 'File not found' (1) + Starting again + + eTSEC2: No link. + Speed: 100, half duplex + Using eTSEC1 device + TFTP from server 10.52.0.33; our IP address is 10.52.253.79 + ^^^^^^^^^^ WRONG + Filename '10.52.0.62'. + ^^^^^^^^^^ WRONG + Load address: 0x100000 + Loading: * + TFTP error: 'File not found' (1) + Starting again + + TftpStart() was modified to not modify the 'BootFile' string. + + Signed-off-by: Peter Tyser + Signed-off-by: Ben Warren + +commit d32c5be50bf0600bfdc54223ef341ee9c63db445 +Author: Peter Tyser +Date: Mon Dec 1 16:26:21 2008 -0600 + + net: Add additional IP fragmentation check + + Ignore IP packets which have the "more fragments" flag bit + set. This flag indicates the IP packet is fragmented and + must be ignored by U-Boot. + + Signed-off-by: Peter Tyser + Signed-off-by: Ben Warren + +commit e0c07b868cab405ab4b5335a0247899bfc5ea0b6 +Author: Peter Tyser +Date: Mon Dec 1 16:26:20 2008 -0600 + + net: Define IP flag field values + + These defines were pulled from the "Add simple + IP/UDP fragmentation support" patch from Frank + Haverkamp . + + Signed-off-by: Peter Tyser + Signed-off-by: Ben Warren + +commit 23afaba65ec5206757e589ef334a8b38168c045f +Author: Anatolij Gustschin +Date: Tue Dec 2 10:31:04 2008 +0100 + + net: tsec: Fix Marvell 88E1121R phy init + + This patch tries to ensure that phy interrupt pin + won't be asserted after booting. We experienced + following issues with current 88E1121R phy init: + + Marvell 88E1121R phy can be hardware-configured + to share MDC/MDIO and interrupt pins for both ports + P0 and P1 (e.g. as configured on socrates board). + Port 0 interrupt pin will be shared by both ports + in such configuration. After booting Linux and + configuring eth0 interface, port 0 phy interrupts + are enabled. After rebooting without proper eth0 + interface shutdown port 0 phy interrupts remain + enabled so any change on port 0 (link status, etc.) + cause assertion of the interrupt. Now booting Linux + and configuring eth1 interface will cause permanent + phy interrupt storm as the registered phy 1 interrupt + handler doesn't acknowledge phy 0 interrupts. This + of course should be fixed in Linux driver too. + + Signed-off-by: Anatolij Gustschin + Acked-by: Andy Fleming + Signed-off-by: Ben Warren + +commit 2e4970d8109d690adcf615d9e3cac7b5b2e8eaed +Author: Peter Tyser +Date: Tue Dec 2 12:59:51 2008 -0600 + + net: Fix download command parsing + + When CONFIG_SYS_HUSH_PARSER is defined network download + commands with 1 argument in the format 'tftp "/path/file"' + do not work as expected. The hush command parser strips + the quotes from "/path/file" which causes the network + commands to interpret "/path/file" as an address + instead of the intended filename. + + The previous check for a leading quote in netboot_common() + was replaced with a check which ensures only valid + numbers are treated as addresses. + + Signed-off-by: Peter Tyser + Signed-off-by: Ben Warren + +commit 3c2c2f427905040c1513d0c51d637689cba48346 +Author: Remy Bohmer +Date: Thu Nov 27 22:30:27 2008 +0100 + + Remove non-ascii characters from fat code + + This code contains some non-ascii characters in comment lines and code. + Most editors do not display those characters properly and editing those + files results always in diffs at these places which are usually not required + to be changed at all. This is error prone. + + So, remove those weird characters and replace them by normal C-style + equivalents for which the proper defines were already in the header. + + Signed-off-by: Remy Bohmer + +commit dc889e865356497d3e495570118c2245ebce2631 +Author: Dave Liu +Date: Fri Nov 28 20:16:58 2008 +0800 + + 85xx: fix the wrong DDR settings for MPC8572DS + + The default DDR freq is 400MHz or 800M data rate, + the old settings is pure wrong for the default case. + + Signed-off-by: Dave Liu + Acked-by: Andy Fleming + +commit 9df59533f77de2829b4b66e5b7620e04edaa391c +Author: Kumar Gala +Date: Mon Nov 24 10:29:26 2008 -0600 + + 85xx: init gd as early as possible + + Moved up the initialization of GD so C code like set_tlb() can use + gd->flags to determine if we've relocated or not in the future. + + Signed-off-by: Kumar Gala + Acked-by: Andy Fleming + +commit aed461af81012a398a205e9be67ab37667491838 +Author: Kumar Gala +Date: Mon Nov 24 10:29:25 2008 -0600 + + 85xx: Fix relocation of CCSRBAR + + If the virtual address for CCSRBAR is the same after relocation but + the physical address is changing we'd end up having two TLB entries with + the same VA. Instead we new us the new CCSRBAR virt address + 4k as a + temp virt address to access the old CCSRBAR to relocate it. + + Signed-off-by: Kumar Gala + Acked-by: Andy Fleming + +commit ea154a1781135d822eedee7567cc156089eae93c +Author: Kumar Gala +Date: Mon Nov 24 10:25:14 2008 -0600 + + FSL: Moved BR_PHYS_ADDR for localbus to common header + + The BR_PHYS_ADDR macro is useful on all machines that have local bus + which is pretty much all 83xx/85xx/86xx chips. + + Additionally most 85xx & 86xx will need it if they want to support + 36-bit physical addresses. + + Signed-off-by: Kumar Gala + Acked-by: Andy Fleming + +commit 9427ccde0355a2ebf47454e8e1be59f5b9864e08 +Author: Peter Tyser +Date: Mon Dec 1 13:47:12 2008 -0600 + + 85xx: Add PORDEVSR_PCI1 define + + Add define used to determine if PCI1 interface is in PCI or PCIX mode. + + Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1 + + Signed-off-by: Peter Tyser + Signed-off-by: Andy Fleming + +commit 35db1c6d34b57ae15e99cf03c8e8f8a6148d74f3 +Author: Becky Bruce +Date: Fri Nov 21 19:24:22 2008 -0600 + + drivers/fsl_pci_init: Fix inbound window mapping bug + + The current code will cause the creation of a 4GB window + starting at 0 if we have more than 4GB of RAM installed, + which overlaps with PCI_MEM space and causes pci_bus_to_phys() + to return erroneous information. Limit the size to 4GB - 1; + which causes the code to create one 2GB and one 1GB window + instead. + + Signed-off-by: Becky Bruce + Signed-off-by: Kumar Gala + Acked-by: Andy Fleming + +commit 5a105a333dab6a23e92d763ce76d6f31d57f45df +Author: Jon Loeliger +Date: Thu Nov 20 15:36:48 2008 -0600 + + Removed unused CONFIG_L1_INIT_RAM symbol. + + Prevent further viral propogation of the unused + symbol CONFIG_L1_INIT_RAM by just removing it. + + Signed-off-by: Jon Loeliger + Acked-by: Andy Fleming + +commit 7008d26a40a76f90cae5824c812cfed449fb97b8 +Author: Ed Swarthout +Date: Wed Oct 29 09:21:44 2008 -0500 + + fsl ddr skip interleaving if not supported. + + Removed while(1) hang if memctl_intlv_ctl is set wrong. + Remove embedded tabs from strings. + + Signed-off-by: Ed Swarthout + Acked-by: Kumar Gala + Acked-by: Andy Fleming + +commit dd332e18d082de75eca3fc2c7c778f5d4571a096 +Author: Anatolij Gustschin +Date: Thu Nov 13 18:08:57 2008 +0100 + + 85xx: socrates: fix DDR SDRAM tlb entry configuration + + since commit be0bd8234b9777ecd63c4c686f72af070d886517 + tlb entry for socrates DDR SDRAM will be reconfigured + by setup_ddr_tlbs() from initdram() causing an + inconsistency with previously configured DDR SDRAM tlb + entry from tlb_table: + + socrates>l2cam 7 9 + IDX PID EPN SIZE V TS RPN U0-U3 WIMGE UUUSSS + 7 : 00 00000000 256MB V 0 -> 0_00000000 0000 -I-G- ---RWX + 8 : 00 00000000 256MB V 0 -> 0_00000000 0000 ----- ---RWX + 9 : 00 10000000 256MB V 0 -> 0_10000000 0000 ----- ---RWX + + This patch makes the presence of the DDR SDRAM tlb entry in + the tlb_table dependent on CONFIG_SPD_EEPROM to avoid this + inconsistency. + + Signed-off-by: Anatolij Gustschin + Acked-by: Andy Fleming + +commit a2cd50ed6ef0ac6b127b3d6db756979a8336718d +Author: Peter Tyser +Date: Tue Nov 11 10:17:10 2008 -0600 + + 85xx: Add CPU 2 errata workaround to all 8548 boards + + All mpc8548-based boards should implement the suggested workaround + to CPU 2 errata. Without the workaround, its possible for the + 8548's core to hang while executing a msync or mbar 0 instruction + and a snoopable transaction from an I/O master tagged to make + quick forward progress is present. + + Signed-off-by: Peter Tyser + Acked-by: Andy Fleming + +commit e57f0fa1333cdf3ca36110aac2900712a5f82976 +Author: Dave Liu +Date: Tue Oct 28 17:53:45 2008 +0800 + + 85xx: the DDR tlb is missed for the !CONFIG_SPD_EEPROM case + + we need TLB entry for DDR at !SPD case. + + Signed-off-by: Dave Liu + Acked-by: Andy Fleming + +commit 9b0ad1b1c7a15ff674978705c7c52264978dc5d8 +Author: Dave Liu +Date: Tue Oct 28 17:53:38 2008 +0800 + + 85xx: remove the unused ddr_enable_ecc in the board file + + The DDR controller of 8548/8544/8568/8572/8536 processors + have the ECC data init feature, and the new DDR code is + using the feature, and we don't need the way with DMA to + init memory any more. + + Signed-off-by: Dave Liu + Acked-by: Andy Fleming + +commit 4a129a57d923f7c15aa1f567028a80a32d66a100 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sun Nov 30 19:36:53 2008 +0100 + + at91rm9200dk: Fix typo + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit ed3b18e05c9a8ffa5fb643da9bcec7452e5d5e01 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sun Nov 30 19:36:50 2008 +0100 + + AT91: remove non supported board AT91RM9200DF macro + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit bd876772ee04095e5dd943d97515a1f14bad4b1c +Author: Ilko Iliev +Date: Tue Dec 2 17:27:54 2008 +0100 + + mtd/dataflash.c: fix a problem with the last partition + + This patch fix the problem that only the [NB_DATAFLASH_AREA - 1] dataflash + partition can be defined to use the area to the end of dataflash size. + Now it is possible to have only one dataflash partition from 0 to the end + of of dataflash size. + + Signed-off-by: Ilko Iliev + +commit 03f797793b124dccaae145b977d15d6cb9e74504 +Author: Ilko Iliev +Date: Tue Dec 2 17:20:17 2008 +0100 + + fix some coding style violations. + + This patch fix some coding style violations. + + Signed-off-by: Ilko Iliev + +commit 5e46b1e54112f4b7fd5185665e571510132c12a7 +Author: Stefan Roese +Date: Thu Nov 27 14:11:37 2008 +0100 + + OneNAND: Add missing mtd info struct before calling onenand_erase() + + Without this patch "saveenv" crashes when MTD partitions are enabled (e.g. + for use in UBI) via CONFIG_MTD_PARTITIONS. + + Signed-off-by: Stefan Roese + Signed-off-by: Scott Wood + +commit 29382d4064fbaff5daacff4c3209370fa5713966 +Author: Becky Bruce +Date: Thu Nov 20 16:43:52 2008 -0600 + + mpc8641: Fix error in README + + I made some updates to the code that didn't make it into the + README - fix this + + Signed-off-by: Becky Bruce + +commit 801a194616d95e6fc426a176d9615ccbf9876c7f +Author: Jon Loeliger +Date: Thu Nov 20 12:01:02 2008 -0600 + + Removed unused CONFIG_L1_INIT_RAM symbol. + + Prevent further viral propogation of the unused + symbol CONFIG_L1_INIT_RAM by just removing it. + + Signed-off-by: Jon Loeliger + +commit f698738e46cb461e28c2d58228bb34a2fcf5a475 +Author: Jon Loeliger +Date: Thu Nov 20 14:02:56 2008 -0600 + + 86xx: Fix non-64-bit compilation problems. + + Introducing 64-bit (36-bit) support for the MPC8641HPCN + failed to accomodate the other two 86xx boards. + Introduce definitions for CONFIG_SYS_CCSRBAR_PHYS_{LOW,HIGH} + CONFIG_SYS_CCSR_DEFAULT_DBAT{U,L} and CONFIG_SYS_CCSR_DEFAULT_IBAT{U,L} + with nominal 32-bit values. + + Signed-off-by: Jon Loeliger + Acked-by: Becky Bruce + +commit bebfc6ef3ec994c8e18783269b1d8d41f8e38afd +Author: Michael Trimarchi +Date: Wed Nov 26 17:40:37 2008 +0100 + + Remove obsolete command (apply afte USB style patch, 80 chars strict) + + Remove USB obsolete commmand + + Signed-off-by: Michael Trimarchi + Signed-off-by: Remy Böhmer + +commit de39f8c19d7c12017248c49d432dcb81db68f724 +Author: Michael Trimarchi +Date: Wed Nov 26 17:41:34 2008 +0100 + + USB style patch, 80 chars strict + + USB Code style patch + + Signed-off-by: Michael Trimarchi + Signed-off-by: Remy Böhmer + +commit d10c5a87cb8affbb4d35a311370316d4383d598e +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Fri Nov 7 22:46:21 2008 +0100 + + drivers/usb: Move conditional compilation to Makefile + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Remy Böhmer + +commit 2077e348c2a84901022ad95311b47b70361e6daa +Author: Scott Wood +Date: Tue Nov 25 10:47:02 2008 -0600 + + NAND: Fix misplaced return statement in nand_{read,write}_skip_bad(). + + This caused the operation to be needlessly repeated if there were + no bad blocks and no errors. + + Signed-off-by: Valeriy Glushkov + Signed-off-by: Scott Wood + +commit 89295028e7d8f7a524f485328279d72fdb102385 +Author: Michal Simek +Date: Mon Nov 24 12:09:50 2008 +0100 + + ppc4xx: ml300 remove Xilinx BSP from ml300 folder + + This BSP should be outside u-boot source tree. + The second reason is that xilinx ppc405 was moved to generic platform. + + Signed-off-by: Michal Simek + Signed-off-by: Stefan Roese + +commit 24eea623d4974a169026a975ba12fb23d48154b1 +Author: Matthias Fuchs +Date: Mon Nov 24 15:11:10 2008 +0100 + + ppc4xx: Remove unused features + + This patch disables some unused features from the PCI405 configuration + to keep U-Boot image size below 192k. + + Signed-off-by: Matthias Fuchs + Signed-off-by: Stefan Roese + +commit 0c2385c3bb51f5d3911fce1ec4720db86b534c2b +Author: Matthias Fuchs +Date: Mon Nov 24 15:11:09 2008 +0100 + + ppc4xx: Use correct io accessors for PCI405 + + Signed-off-by: Matthias Fuchs + Signed-off-by: Stefan Roese + +commit 348c849d86a6f0785752b9bc497a34658713d1d1 +Author: Matthias Fuchs +Date: Mon Nov 24 15:11:08 2008 +0100 + + ppc4xx: Remove unused code from PCI405 code + + Signed-off-by: Matthias Fuchs + Signed-off-by: Stefan Roese + +commit 58c696eed839af894e0265064669c402dc28b371 +Author: Wolfgang Denk +Date: Mon Nov 24 21:50:59 2008 +0100 + + AT91RM9200DK: fix broken boot from NOR flash + + Signed-off-by: Wolfgang Denk + +commit 8052352f20b33bef8f9872fc983eac73d4693c38 +Author: Jens Scharsig +Date: Tue Nov 18 10:48:46 2008 +0100 + + at91rm9200: fix broken boot from nor flash + + This patch fix the broken boot from NOR Flash on AT91RM9200 boards, if + CONFIG_AT91RM9200 is defined and nor preloader is used. + + Signed-off-by: Jens Scharsig + +commit 25ea652e907516a283b38237e83712a918f125d7 +Author: Piotr Ziecik +Date: Mon Nov 17 15:58:00 2008 +0100 + + UBI: Add proof-of-concept CFI flash support + + With this patch UBI can be used on CFI flash chips. + + Signed-off-by: Piotr Ziecik + Signed-off-by: Stefan Roese + +commit e6a7edbc1778d27431ac663b40a71dafa5d20578 +Author: Piotr Ziecik +Date: Mon Nov 17 15:57:59 2008 +0100 + + mtd: Remove a printf() from add_mtd_device(). + + Remove a printf() from add_mtd_device(), which produces spurious output. + + Signed-off-by: Piotr Ziecik + Signed-off-by: Stefan Roese + +commit 91809ed51d8327a8dbbf29aa98a091154c282171 +Author: Piotr Ziecik +Date: Mon Nov 17 15:57:58 2008 +0100 + + cfi-mtd: Add cfi-mtd driver. + + Add cfi-mtd driver, which exports CFI flash to MTD layer. + This allows CFI flash devices to be used from MTD layer. + + Building of the new driver is controlled by CONFIG_FLASH_CFI_MTD + option. Initialization is done by calling cfi_mtd_init() from + flash_init(). + + Signed-off-by: Piotr Ziecik + Signed-off-by: Stefan Roese + +commit 6ea808efdf9aa5d9067fbfac32acde8539129ed2 +Author: Piotr Ziecik +Date: Mon Nov 17 15:49:32 2008 +0100 + + cfi_flash: Add interface for flash verbosity control + + Add interface for flash verbosity control. It allows + to disable output from low-level flash API. It is useful + when calling these low-level functions from context other + than flash commands (for example the MTD/CFI interface + implmentation). + + Signed-off-by: Piotr Ziecik + Signed-off-by: Stefan Roese + +commit ebc9784ce6528385bb8d2558e783622d4bbf20f8 +Author: Piotr Ziecik +Date: Thu Nov 20 15:17:38 2008 +0100 + + cfi_flash: Export flash_sector_size() function. + + Export flash_sector_size() function from drivers/mtd/cfi_flash.c, + so that it can be used in the upcoming cfi-mtd driver. + + Signed-off-by: Piotr Ziecik + Signed-off-by: Stefan Roese + +commit 45aa5a7f4d5bcb79927ddfc896c1d7c4326e235d +Author: Stefan Roese +Date: Mon Nov 17 14:45:22 2008 +0100 + + cfi_flash: Make all flash access functions weak + + This patch defines all flash access functions as weak so that + they can be overridden by board specific versions. + + This will be used by the upcoming VCTH board support where the NOR + FLASH unfortunately can't be accessed memory-mapped. Special + accessor functions are needed here. + + To enable this weak functions you need to define + CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS in your board config header. + Otherwise the "old" default functions will be used resulting + in smaller code. + + Signed-off-by: Stefan Roese + Acked-by: Haavard Skinnemoen + +commit a5c4067017631d903e1afa6ad615f0ce19fea517 +Author: Stefan Roese +Date: Mon Nov 24 08:31:16 2008 +0100 + + UBI: Change parsing of size in commands to default to hex + + Currently the size parameters of the UBI commands (e.g. "ubi write") are + decoded as decimal instead of hex as default. This patch now interprets + all these values consistantly as hex, as all other standard U-Boot commands + do. + + Signed-off-by: Stefan Roese + +commit de01c76c3ccc4e6c5989228eed58e955a3a1a968 +Author: Stefan Roese +Date: Fri Nov 21 13:06:06 2008 +0100 + + ppc4xx: ML2 shouldn't include the 4xx EMAC driver + + Signed-off-by: Stefan Roese + +commit 1a6a00dcc5bdfc6e9b4b00f39c1f583a7f96fc7f +Author: Yuri Tikhonov +Date: Fri Nov 14 16:19:19 2008 +0300 + + ppc4xx: katmai: Change default config + + This patch enables support for EXT2, and increases the + CONFIG_SYS_BOOTMAPSZ size for the default configuration + of the katmai boards to use them as the RAID-reference + AMCC setups. + + EXT2 enabling allows one to boot kernels from the EXT2 + formatted Compact Flash cards. + + CONFIG_SYS_BOOTMAPSZ increasing allows one to boot the + Linux kernels, which use PAGE_SIZE of 256KB. Otherwise, + the memory area with DTB file (which is placed at the + end of the bootmap area) will turn out to be overlapped + with the BSS segment of the 256KB kernel, and zeroed + in early_init() of Linux. + + Actually, increasing of the bootmap size could be done + via setting of the bootm_size U-Boot variable, but it looks + like the current U-Boot implementation have some bootm_size- + related functionality lost. In many places through the U-Boot + code the CONFIG_SYS_BOOTMAPSZ definition is used directly + (instead of trying to read the corresponding value from the + environment). The same is truth for the boot_jump_linux() + function in lib_ppc/bootm.c, where U-Boot transfers control + to Linux passing the CONFIG_SYS_BOOTMAPSZ (not bootm_size) + value to the booting kernel. + + Signed-off-by: Yuri Tikhonov + Signed-off-by: Ilya Yanok + Signed-off-by: Stefan Roese + +commit ddf45cc758d394591fb9bcdcbe96530f733f2bce +Author: Dave Mitchell +Date: Thu Nov 20 14:09:50 2008 -0600 + + ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initialization + + Expanded OCM TLB to allow access to 64K OCM as well as 256K of + internal SRAM. + + Adjusted internal SRAM initialization to match updated user + manual recommendation. + + OCM & ISRAM are now mapped as follows: + physical virtual size + ISRAM 0x4_0000_0000 0xE300_0000 256k + OCM 0x4_0004_0000 0xE304_0000 64k + + A single TLB was used for this mapping. + + Signed-off-by: Dave Mitchell + Signed-off-by: Stefan Roese + +commit b14ca4b61a681f75f3125676e09d7ce6af66e927 +Author: Dave Mitchell +Date: Thu Nov 20 14:00:49 2008 -0600 + + ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRs + + Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and + L2 cache DCRs from ppc440.h to this new header. + + Also converted these DCR defines from lowercase to uppercase and + modified referencing modules to use them. + + Signed-off-by: Dave Mitchell + Signed-off-by: Stefan Roese + +commit 711e2b2af820d21d9931d4cf8057d3894600fd54 +Author: Steven A. Falco +Date: Thu Nov 20 14:37:57 2008 -0500 + + ppc4xx: Delete unused definitions for SDR0_DDRCFG from ppc4xx.h + + The definitions of bits in SDR_CFG are incorrect, and not used within + U-Boot. Therefore, they can be removed. + + The naming of the sdr_ddrdl/sdr_cfg registers do not follow conventions, + and are unused, so they can be removed too. + + A definition for SDR0_DDRCFG is added. + + Signed-off-by: Steven A. Falco + Signed-off-by: Stefan Roese + +commit e23c7c95a96eb0f068efe5c532215a10a1512a95 +Author: Dirk Behme +Date: Mon Nov 10 20:15:25 2008 +0100 + + ARM: OMAP: Convert IO macros + + Convert IO macros to readx/writex. + + Signed-off-by: Dirk Behme + +commit 263b749e2e25473a48776d317bd2a7e2ddcdd212 +Author: Ilko Iliev +Date: Sun Nov 9 15:53:14 2008 +0100 + + lib_arm: do_bootm_linux() - correct a small mistake + + This patch corrects a small bug in the "if" condition: + the parameter "flag" is 0 and the "if" condition is always true. + The result is - the boom command doesn't start the kernel. + Affected targets: all arm based. + + Signed-off-by: Ilko Iliev + +commit 3e0cda071a67cb5709e3fa4faf6b31a731859acc +Author: Stelian Pop +Date: Sun Nov 9 00:14:46 2008 +0100 + + AT91: Enable PLLB for USB + + At least some (old ?) versions of the AT91Bootstrap do not set up the + PLLB correctly to 48 MHz in order to make USB host function correctly. + + This patch sets up the PLLB to the same values Linux uses, and makes USB + work ok on the following CPUs: + - AT91CAP9 + - AT91SAM9260 + - AT91SAM9263 + + This patch also defines CONFIG_USB_STORAGE and CONFIG_CMD_FAT for all + the relevant AT91CAP9/AT91SAM9 atmel boards. + + Signed-off-by: Stelian Pop + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit ad229a44e162af0f65e57e4e3dc133d5f0364ecb +Author: Stelian Pop +Date: Fri Nov 7 13:55:14 2008 +0100 + + AT91: Use AT91_CPU_CLOCK in displays + + Introduce AT91_CPU_CLOCK and use it for displaying the CPU + speed in the LCD driver. + + Also make AT91_MAIN_CLOCK and AT91_MASTER_CLOCK reflect the + corresponding board clocks. + + Signed-off-by: Stelian Pop + +commit 25fb4eaaeab3f8866020818f4729d990dcc91cf0 +Author: Stefan Roese +Date: Thu Nov 20 11:46:20 2008 +0100 + + ppc4xx: Clear all potentially pending exceptions in MCSR + + This is needed on Canyonlands which still has an exception pending + while running relocate_code(). This leads to a failure after trap_init() + is moved to the top of board_init_r(). + + Signed-off-by: Stefan Roese + +commit facdad5f2602e899a01746916beddbf9e856b5ee +Author: Heiko Schocher +Date: Wed Nov 19 10:10:30 2008 +0100 + + powerpc: 83xx: add missing TIMING_CFG1_CASLAT_* defines + + Signed-off-by: Heiko Schocher + Signed-off-by: Kim Phillips + +commit 2f2a5c3714d17f4ead18b713128b7226e0e822f4 +Author: Howard Gregory +Date: Tue Nov 4 14:55:33 2008 +0800 + + mpc83xx: Improve the performance of DDR memory + + modify the CAS timings. my understanding is that these + settings decrease various wait times in the DDR interface. + Because these wait times are in clock cycles, and the DDR + clock on the 8315 RDB runs slower than on some other 83xx + platforms, we can dial down these values without a problem, + thereby decreasing the latency of memory a little. + + Signed-off-by: Howard Gregory + Signed-off-by: Dave Liu + Signed-off-by: Kim Phillips + +commit 8000b086b33a5a81f3f390f37e178db7956dc08b +Author: Kyungmin Park +Date: Fri Oct 24 14:55:33 2008 +0200 + + ARM: Add Apollon UBI support + + To enable UBI on Apollon you need to uncomment the CONFIG_SYS_USE_UBI + macro. + + Signed-off-by: Kyungmin Park + Signed-off-by: Stefan Roese + +commit 694a0b3f1c0accd0de94b89555155d69f8022824 +Author: Kyungmin Park +Date: Wed Nov 19 11:47:05 2008 +0100 + + UBI: Add UBI command support + + This patch adds these UBI commands: + + ubi part [nand|onenand] [part] - Show or set current partition + ubi info [l[ayout]] -Display volume and UBI layout information + ubi create[vol] volume [size] [type] - Create volume name with size + ubi write[vol] address volume size - Write volume from address with size + ubi read[vol] address volume [size] - Read volume to address with size + ubi remove[vol] volume - Remove volume + + Signed-off-by: Kyungmin Park + Signed-off-by: Stefan Roese + +commit 58be3a1056d88c6d05f3e914389282807e69923a +Author: Kyungmin Park +Date: Wed Nov 19 16:38:24 2008 +0100 + + UBI: Add basic UBI support to U-Boot (Part 8/8) + + This patch adds basic UBI (Unsorted Block Image) support to U-Boot. + It's based on the Linux UBI version and basically has a "OS" + translation wrapper that defines most Linux specific calls + (spin_lock() etc.) into no-ops. Some source code parts have been + uncommented by "#ifdef UBI_LINUX". This makes it easier to compare + this version with the Linux version and simplifies future UBI + ports/bug-fixes from the Linux version. + + Signed-off-by: Kyungmin Park + Signed-off-by: Stefan Roese + +commit 47ae6693f54f80455ae32c2e0d995e0e4bdc15b9 +Author: Kyungmin Park +Date: Wed Nov 19 16:36:36 2008 +0100 + + UBI: Add basic UBI support to U-Boot (Part 7/8) + + This patch adds basic UBI (Unsorted Block Image) support to U-Boot. + It's based on the Linux UBI version and basically has a "OS" + translation wrapper that defines most Linux specific calls + (spin_lock() etc.) into no-ops. Some source code parts have been + uncommented by "#ifdef UBI_LINUX". This makes it easier to compare + this version with the Linux version and simplifies future UBI + ports/bug-fixes from the Linux version. + + Signed-off-by: Kyungmin Park + Signed-off-by: Stefan Roese + +commit 7e6ee7ad27de5216db1baef76f38c3429c8f4a2a +Author: Kyungmin Park +Date: Wed Nov 19 16:32:36 2008 +0100 + + UBI: Add basic UBI support to U-Boot (Part 6/8) + + This patch adds basic UBI (Unsorted Block Image) support to U-Boot. + It's based on the Linux UBI version and basically has a "OS" + translation wrapper that defines most Linux specific calls + (spin_lock() etc.) into no-ops. Some source code parts have been + uncommented by "#ifdef UBI_LINUX". This makes it easier to compare + this version with the Linux version and simplifies future UBI + ports/bug-fixes from the Linux version. + + Signed-off-by: Kyungmin Park + Signed-off-by: Stefan Roese + +commit c91a719daa331b5856109313371e4ece5ec06d96 +Author: Kyungmin Park +Date: Wed Nov 19 16:28:06 2008 +0100 + + UBI: Add basic UBI support to U-Boot (Part 5/8) + + This patch adds basic UBI (Unsorted Block Image) support to U-Boot. + It's based on the Linux UBI version and basically has a "OS" + translation wrapper that defines most Linux specific calls + (spin_lock() etc.) into no-ops. Some source code parts have been + uncommented by "#ifdef UBI_LINUX". This makes it easier to compare + this version with the Linux version and simplifies future UBI + ports/bug-fixes from the Linux version. + + Signed-off-by: Kyungmin Park + Signed-off-by: Stefan Roese + +commit f412fefa079c6aa9a9763f6869bf787ea6bf6e1b +Author: Kyungmin Park +Date: Wed Nov 19 16:27:23 2008 +0100 + + UBI: Add basic UBI support to U-Boot (Part 4/8) + + This patch adds basic UBI (Unsorted Block Image) support to U-Boot. + It's based on the Linux UBI version and basically has a "OS" + translation wrapper that defines most Linux specific calls + (spin_lock() etc.) into no-ops. Some source code parts have been + uncommented by "#ifdef UBI_LINUX". This makes it easier to compare + this version with the Linux version and simplifies future UBI + ports/bug-fixes from the Linux version. + + Signed-off-by: Kyungmin Park + Signed-off-by: Stefan Roese + +commit 2d262c4853cb5b6ddce1a28a9641f2de3688d7ea +Author: Kyungmin Park +Date: Wed Nov 19 16:26:54 2008 +0100 + + UBI: Add basic UBI support to U-Boot (Part 3/8) + + This patch adds basic UBI (Unsorted Block Image) support to U-Boot. + It's based on the Linux UBI version and basically has a "OS" + translation wrapper that defines most Linux specific calls + (spin_lock() etc.) into no-ops. Some source code parts have been + uncommented by "#ifdef UBI_LINUX". This makes it easier to compare + this version with the Linux version and simplifies future UBI + ports/bug-fixes from the Linux version. + + Signed-off-by: Kyungmin Park + Signed-off-by: Stefan Roese + +commit 961df83361aff9a14f226214224eb8a06e05ba24 +Author: Kyungmin Park +Date: Wed Nov 19 16:25:44 2008 +0100 + + UBI: Add basic UBI support to U-Boot (Part 2/8) + + This patch adds basic UBI (Unsorted Block Image) support to U-Boot. + It's based on the Linux UBI version and basically has a "OS" + translation wrapper that defines most Linux specific calls + (spin_lock() etc.) into no-ops. Some source code parts have been + uncommented by "#ifdef UBI_LINUX". This makes it easier to compare + this version with the Linux version and simplifies future UBI + ports/bug-fixes from the Linux version. + + Signed-off-by: Kyungmin Park + Signed-off-by: Stefan Roese + +commit f399d4a281713d5ef2d764f05d545fe61e3bd569 +Author: Kyungmin Park +Date: Wed Nov 19 16:23:06 2008 +0100 + + UBI: Add basic UBI support to U-Boot (Part 1/8) + + This patch adds basic UBI (Unsorted Block Image) support to U-Boot. + It's based on the Linux UBI version and basically has a "OS" + translation wrapper that defines most Linux specific calls + (spin_lock() etc.) into no-ops. Some source code parts have been + uncommented by "#ifdef UBI_LINUX". This makes it easier to compare + this version with the Linux version and simplifies future UBI + ports/bug-fixes from the Linux version. + + Signed-off-by: Kyungmin Park + Signed-off-by: Stefan Roese + +commit e29c22f5abe6e0f4baa6251efed6074cdfc3db79 +Author: Kyungmin Park +Date: Wed Nov 19 16:20:36 2008 +0100 + + MTD: Add MTD paritioning infrastructure + + This MTD part infrastructure will be used by the upcoming + UBI support. + + Signed-off-by: Kyungmin Park + Signed-off-by: Stefan Roese + +commit 9b827cf1720acda2473afa516956eab6f7cca9a1 +Author: Selvamuthukumar +Date: Thu Oct 16 22:54:03 2008 +0530 + + Align end of bss by 4 bytes + + Most of the bss initialization loop increments 4 bytes + at a time. And the loop end is checked for an 'equal' + condition. Make the bss end address aligned by 4, so + that the loop will end as expected. + + Signed-off-by: Selvamuthukumar + Signed-off-by: Wolfgang Denk + +commit 3f510db522d160179dff3ddcce9b18f6241c2c24 +Author: Becky Bruce +Date: Mon Nov 10 19:45:35 2008 -0600 + + mpc8641: fix address-cells default in old .dts detection + + address-cells defaults to 2, not 1; so in the unlikely + event that it isn't specified, this patch is required + for correct operation. + + Signed-off-by: Becky Bruce + +commit d025aa4b20a0618a2bada0132a9a0a4afb717f1a +Author: Becky Bruce +Date: Fri Oct 31 17:14:39 2008 -0500 + + lib_ppc: Move trap_init to occur earlier + + Doing trap_init immediately once we're running from RAM + means we're no longer dependent on the physical location of + the flash on non-BookE platforms. Before trap_init, those + platforms switch to real mode and go to 0xfff00100 on exception. + After the switch, they go to 0x00000100 This makes it easier to + move the flash location. + + Signed-off-by: Becky Bruce + +commit d52082b12c6e545705a19433a2f4142526536189 +Author: Becky Bruce +Date: Fri Nov 7 13:46:19 2008 -0600 + + mpc8641: Try to detect old .dts files + + Since we've changed the memory map of the board, be nice and + add some checking to try to catch out-of-date .dts files. We do + this by checking the CCSRBAR location in the .dts and comparing + it to the CCSRBAR location in u-boot. If they don't match, a + warning msg is printed. This isn't foolproof, but it's simple and + will catch most of the cases where an out-of-date .dts is present, + including all of the cases where a new u-boot is used with an old + standard MPC8641 .dts file as supplied with Linux. + + Signed-off-by: Becky Bruce + +commit 8db0400a27839f91c047dcb83f4a0f09e054a180 +Author: Becky Bruce +Date: Thu Nov 6 13:04:09 2008 -0600 + + toplevel Makefile: Add MPC8641HPCN_36BIT target + + This will enable CONFIG_PHYS_36BIT for MPC8641HPCN. + + Signed-off-by: Becky Bruce + +commit 3111d32c494e8251b90917447796a7206b757e1e +Author: Becky Bruce +Date: Thu Nov 6 17:37:35 2008 -0600 + + mpc8641: Support 36-bit physical addressing + + This patch creates a memory map with all the devices + in 36-bit physical space, in addition to the 32-bit map. + The CCSR relocation is moved (again, sorry) to + allow for the physical address to be 36 bits - this + requires translation to be enabled. With 36-bit physical + addressing enabled, we are no longer running with VA=PA + translations. This means we have to distinguish between + the two in the config file. The existing region name is + used to indicate the virtual address, and a _PHYS variety + is created to represent the physical address. + + Large physical addressing is not enabled by default. + Set CONFIG_PHYS_64BIT in the config file to turn this on. + + Signed-off-by: Becky Bruce + +commit c759a01a0022de9378a3a761f49786f87684c916 +Author: Becky Bruce +Date: Thu Nov 6 17:36:04 2008 -0600 + + mpc8641: Change 32-bit memory map + + The memory map on the 8641hpcn is modified to look more like + the 85xx boards; this is a step towards a more standardized + layout going forward. As part of this change, we now relocate + the flash. + + The regions for some of the mappings were far larger than they + needed to be. I have reduced the mappings to match the + actual sizes supported by the hardware. + + In addition I have removed the comments at the head + of the BAT blocks in the config file, rather than updating + them. These get horribly out of date, and it's a simple + matter to look at the defines to see what they are set to + since everything is right here in the same file. + + Documentation has been changed to reflect the new map, as this + change is user visible, and affects the OS which runs post-uboot. + + Signed-off-by: Becky Bruce + +commit bf9a8c34309ed9276258295db9e9212aabb2531a +Author: Becky Bruce +Date: Wed Nov 5 14:55:35 2008 -0600 + + mpc86xx: Change early FLASH mapping to 1M at CONFIG_MONITOR_BASE_EARLY + + We define CONFIG_MONITOR_BASE_EARLY to define the initial location + of the bootpage in flash. Use this to create an early mapping + definition for the FLASH, and change the early_bats code to use this. + + This change facilitates the relocation of the flash since the early + mappings are no longer tied to the final location of the flash. + + Signed-off-by: Becky Bruce + +commit c1e1cf69547b138173f87a7f81c42a5d8dbfde3d +Author: Becky Bruce +Date: Wed Nov 5 14:55:34 2008 -0600 + + mpc86xx: Use SRR0/1/rfi to enable address translation, not blr + + Using a mtmsr/blr means that you have to be executing at the + same virtual address once you enable translation. This is + unnecessarily restrictive, and is not really how this is + usually done. Change it to use the more common mtspr SRR0/SRR1 + and rfi method. + + Signed-off-by: Becky Bruce + +commit 6bf98b1362f0cb237620355ed3e6762fff82388d +Author: Becky Bruce +Date: Wed Nov 5 14:55:33 2008 -0600 + + mpc8641: make DIAG_ADDR == FLASH_BASE + + Currently, that's what it is, but it's hardcoded. + + Signed-off-by: Becky Bruce + +commit 170deacb1ddc39164bdb68f3963e0c0456a5369b +Author: Becky Bruce +Date: Wed Nov 5 14:55:32 2008 -0600 + + mpc8641: Drop imaginary second flash bank, map 8MB + + There's a lot of setup and foo for the second flash + bank. The problem is, this board doesn't actually have one. + Clean this up. Also, the flash is 8M in size. Get rid + of the confusing aliased overmapping, and just map 8M. + + Signed-off-by: Becky Bruce + +commit 0f2d66027bfc60dc7eea2f096af8891988c5abe4 +Author: Becky Bruce +Date: Wed Nov 5 14:55:31 2008 -0600 + + mpc8641: only define CONFIG_ENV_SIZE once + + It's currently defined twice inside in an if/else block, but + both halves set the same value. Move the define outside + the if. + + Signed-off-by: Becky Bruce + +commit 24bfb48c35fed6ad1f047e3e4a27df302482cd93 +Author: Becky Bruce +Date: Wed Nov 5 14:55:30 2008 -0600 + + mpc86xx: Move setup_bats into cpu_init_f + + In order to later allow for a physical relocation of the + flash, setup_bats, which sets up the final BAT mapping + for the board, needs to happen *after* init_laws(). + Otherwise, there will be no window programmed for the flash + at the new physical location at the point when we change + the mmu translation. + + Signed-off-by: Becky Bruce + +commit 05df3e5a638be8c5b0899eae1766bbe8e4b92c17 +Author: Becky Bruce +Date: Wed Nov 5 14:55:29 2008 -0600 + + mpc8641: Remove extra "0" from BR2 define + + Signed-off-by: Becky Bruce + +commit edf3fe7d39a1ee07353128af5221422ce9ccfad6 +Author: Richard Retanubun +Date: Thu Oct 23 09:08:18 2008 -0400 + + drivers/qe/uec_phy.c: Added PHY-less (fixed PHY) driver. + + Copied over the fixed PHY driver as used in pp4xx/4xx_enet.c. + This adds support for PHY-less MAC connections to the UEC. + + Signed-off-by: Richard Retanubun + Signed-off-by: Ben Warren + +commit 54bdcc9fb6670afde9c26dcf364f582879bf21d6 +Author: TsiChung Liew +Date: Thu Oct 23 16:27:24 2008 +0000 + + ColdFire: Add mii driver in drivers/net + + All CF platforms' mii.c are consolidated into one + + Signed-off-by: TsiChung Liew + Signed-off-by: Ben Warren + +commit 25a859066b3af1070eb69f12022113c0a91bd813 +Author: Ben Warren +Date: Mon Oct 27 23:53:17 2008 -0700 + + Moved initialization of PPC4xx EMAC to cpu_eth_init() + + Removed initialization of the driver from net/eth.c + + Signed-off-by: Ben Warren + Acked-by: Stefan Roese + +commit 4d03a4e20e58552cb96d61a0e8b56cdb6cc60126 +Author: Ben Warren +Date: Sun Nov 9 21:29:23 2008 -0800 + + Moved PPC4xx EMAC driver to drivers/net + + Also changed path in all linker scripts that reference this driver + + Signed-off-by: Ben Warren + Acked-by: Stefan Roese + +commit 96e21f86e8266ed40759e5495ee461265d7f6d28 +Author: Ben Warren +Date: Mon Oct 27 23:50:15 2008 -0700 + + Changed PPC4xx EMAC driver to require CONFIG_PPC4xx_EMAC + + All in-tree IBM/AMCC PPC4xx boards using the EMAC get this new CONFIG + + Signed-off-by: Ben Warren + Acked-by: Stefan Roese + +commit 9eb79bd8856bcab896ed5e1f1bca159807a124dd +Author: Ben Warren +Date: Thu Oct 23 22:02:49 2008 -0700 + + Moved initialization of MPC8XX SCC to cpu_eth_init() + + Removed initialization of the driver from net/eth.c + + Signed-off-by: Ben Warren + +commit a9bec96d6359ac9f90a852962bf3040cad9e0256 +Author: Ben Warren +Date: Wed Oct 22 23:47:51 2008 -0700 + + Moved initialization of MPC8220 FEC to cpu_eth_init() + + Removed initialization of the driver from net/eth.c + + Signed-off-by: Ben Warren + +commit 0e8454e990385a58f708c2fc26d31ac041c7a6c5 +Author: Ben Warren +Date: Wed Oct 22 23:32:48 2008 -0700 + + Moved initialization of QE Ethernet controller to cpu_eth_init() + + Removed initialization of the driver from net/eth.c + + Signed-off-by: Ben Warren + +commit 3456a148276d5494b53ee40242efb6462d163504 +Author: Ben Warren +Date: Wed Oct 22 23:20:29 2008 -0700 + + Moved initialization of FCC Ethernet controller to cpu_eth_init + + Affected boards: + Several MPC8xx boards + Several MPC8260/MPC8272 boards + Several MPC85xx boards + + Removed initialization of the driver from net/eth.c + + Signed-off-by: Ben Warren + +commit 62e15b497f5c6334c059512678c8db7940ae4c61 +Author: Ben Warren +Date: Thu Oct 30 22:15:35 2008 -0700 + + Fix typo in cpu/mpc85xx/cpu.c + + CONFIG_MPC85xx_FEC -> CONFIG_MPC85XX_FEC + + Signed-off-by: Ben Warren + +commit 5dfb3ee3f54e2382a08d72906f0e79ecf944f6e3 +Author: Shinya Kuribayashi +Date: Sun Oct 19 12:08:50 2008 +0900 + + net: Move initialization of Au1x00 SoC ethernet MAC to cpu_eth_init + + This patch will move au1x00_eth_initialize from net/eth.c to cpu_eth_init + as a part of ongoing eth_initialize cleanup work. The function ret value + is also fixed as it should be negative on fail. + + Signed-off-by: Shinya Kuribayashi + Signed-off-by: Ben Warren + +commit cc94074ecac1885d18ddb683eb934b3c0268aa5b +Author: Ben Warren +Date: Fri Sep 5 01:55:22 2008 -0400 + + Moved initialization of IXP4XX_NPE Ethernet controller to cpu_eth_init() + + Also, removed the driver initialization from net/eth.c + + Signed-off-by: Ben Warren + +commit f2a7806fc23e82d30c8548911369e0c530607354 +Author: Clive Stubbings +Date: Mon Oct 27 15:05:00 2008 +0000 + + xilinx_emaclite buffer overrun + + Patch to fix buffer allocation size and alignment. Buffer needs to be u32 aligned and + PKTSIZE_ALIGN bytes long. + + Acked-by: Michal Simek + + Signed-off-by: Ben Warren + +commit 0115b1953718a2969f6469d3d5da51ba11e12d42 +Author: richardretanubun +Date: Fri Sep 26 08:59:12 2008 -0400 + + NET: QE: UEC: Make uec_miiphy_read() and uec_miiphy_write() use the devname arg. + + The current uec_miiphy_read and uec_miiphy_write hardcode access devlist[0] + This patch makes these function use the devname argument that is passed in to + allow access to the phy registers of other devices in devlist[]. + + Signed-of-by: Richard Retanubun + + Signed-off-by: Ben Warren + +commit 44dcb7332033db8de2810f2fffcae3084f15c8d4 +Author: richardretanubun +Date: Mon Oct 6 15:31:43 2008 -0400 + + Adds two more ethernet interface to 83xx + + Fixed compiler warning "declared but unused" eth5_uec_info and eth6_uec_info. + Signed-off-by: Richard Retanubun + Signed-off-by: Ben Warren + +commit d8003fa03733901b73d6c4667b4d80fc8eb1ddd3 +Author: Stelian Pop +Date: Fri Nov 7 13:54:31 2008 +0100 + + AT91: Replace AT91_BASE_EMAC by the board specific values. + + AT91_BASE_EMAC is never used outside the board specific files, + so replace its usage by the board specific AT91xxx_BASE_EMAC. + + Signed-off-by: Stelian Pop + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit c91e17affa175ce06afa89b04752301eb4a61666 +Author: Stelian Pop +Date: Fri Nov 7 12:09:21 2008 +0100 + + AT91: Replace (undefined) AT91_ID_US* by the board specific values. + + AT91_ID_US0 / AT91_ID_US1 / AT91_ID_US2 were used but never defined. + Since they are never used outside the board specific files, they can + be replaced by the board specific AT91xxx_ID_US0 / AT91xxx_ID_US1 / + AT91xxx_ID_US2. + + Bug spotted by Jesus Alvarez . + + Signed-off-by: Stelian Pop + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 28962f5a2de81bc0eed1c0b08c6bfaa1cc134ea2 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sat Nov 1 10:47:59 2008 +0100 + + Makefile/at91sam9: move some at91sam9 to the correct subsection for arm926ejs + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 1079432e04ccf71aa3684181186182cd63512f19 +Author: Sergey Lapin +Date: Fri Oct 31 12:28:43 2008 +0100 + + Custom AFEB9260 board support + + This patch provides support for AFEB9260 board, a product of + OpenSource hardware and software. Some commertial projects + are made with this design. A board is basically AT91SAM9260-EK + with some modifications and different peripherals and different + parts used. Main purpose of this project is to gain experience in + hardware design. + More info: http://groups.google.com/group/arm9fpga-evolution-board + (In Russian only, sorry). + Subversion repository: svn://194.85.238.22/home/users/george/svn/arm9eb + + Signed-off-by: Sergey Lapin + +commit 26eecd24f97130e56e9c2c2af0e714e05bce6e00 +Author: Tomohiro Masubuchi +Date: Tue Oct 21 13:17:16 2008 +0900 + + Change to use "do_div" macro + + Signed-off-by: Tomohiro Masubuchi + +commit e352495318d8056a00faa21b633b3e4374bfbf52 +Author: Roman Mashak +Date: Wed Oct 22 16:00:26 2008 -0400 + + ARM926EJ-S: relocate OMAP specific 'cpuinfo.c' into OMAP directory + + OMAP identification is implemented in 'cpuinfo.c' and located in ARM926EJ-S directory. + It makes sense to place this file in OMAP specific subdirectory, i.e. cpu/arm926ejs/omap + + Signed-off-by: Roman Mashak + +commit 248b2c367210c06dbd5fbdecf27e97fbe9d05fdb +Author: Roman Mashak +Date: Tue Oct 21 03:01:41 2008 -0700 + + ARM/Versatile port: Removed unused functions + + Removal of never used functions. + + Signed-off-by: Roman Mashak + +commit 1266df887781c779deaf6d05eea2ef90a470cb34 +Author: Becky Bruce +Date: Mon Nov 3 15:44:01 2008 -0600 + + powerpc: change 86xx SMP boot method + + We put the bootpg for the secondary cpus into memory and use + BPTR to get to it. This is a step towards converting to the + ePAPR boot methodology. Also, the code is written to + deal properly with more than 4GB of RAM. + + Signed-off-by: Becky Bruce + +commit b5431560682d8f318fbc49db87cfe13ab41d2ee4 +Author: Becky Bruce +Date: Fri Oct 31 17:13:49 2008 -0500 + + 8641HPCN: Config file cleanup + + There are several items in the config file that were hardcoded + but that should really be based on other config options, since + the regions are contiguous and depend on being so. This cleans + that up a bit. Also, add BR_PHYS_ADDR() macro to convert + addresses into the proper format for BR registers. + + Signed-off-by: Becky Bruce + +commit 4c77de3f144ca088c3867bd6240718c10f5a9d69 +Author: Becky Bruce +Date: Fri Oct 31 17:13:32 2008 -0500 + + 86xx: Make dram_size a phys_size_t + + It's currently a long and should be phys_size_t. + + Signed-off-by: Becky Bruce + +commit 104992fc541302a6bac74448e01e7fdad20abca0 +Author: Becky Bruce +Date: Sun Nov 2 18:19:32 2008 -0600 + + powerpc 86xx: Handle CCSR relocation earlier + + Currently, the CCSR gets relocated while translation is + enabled, meaning we need 2 BAT translations to get to both the + old location and the new location. Also, the DEFAULT + CCSR location has a dependency on the BAT that maps the + FLASH region. Moving the relocation removes this unnecessary + dependency. This makes it easier and more intutive to + modify the board's memory map. + + Swap BATs 3 and 4 on 8610 so that all 86xx boards use the same + BAT for CCSR space. + + Signed-off-by: Becky Bruce + +commit af5d100e8d5cd49d69d52d20f1181eb06ddb4ddf +Author: Becky Bruce +Date: Fri Oct 31 17:14:14 2008 -0500 + + mpc8641: Make PCI and RIO mutually exclusive, fix non-PCI build + + You can't actually have both, and with some coming changes to + change the memory map for the board and support 36-bit physical, + we need the extra BAT that is being consumed by having both. + + I also make non-PCI configs build cleanly, for the sake of sanity. + + Signed-off-by: Becky Bruce + +commit 98693b85d42ff438375dc6d6dcadc70eb7b050bb +Author: Becky Bruce +Date: Fri Oct 31 17:14:00 2008 -0500 + + mpc8641: Stop supporting non-PCI_PNP configs + + We don't actually ever do this, remove the code so we + can stop maintaining it. + + Signed-off-by: Becky Bruce + +commit e4f69d1bd21a12049744989d2dd6b5199c9b8f23 +Author: TsiChung Liew +Date: Fri Oct 24 12:59:12 2008 +0000 + + ColdFire: Fix M5329EVB and M5373EVB nand issue + + Fix compilation issue caused by a few mismatches. + Provide proper nand chip select enable/disable in + nand_hwcontrol() rather than in board_nand_init() + just enable once. Remove redundant local nand driver + functions - nand_read_byte(), nand_write_byte() and + nand_dev_ready() to use common nand driver. + + Signed-off-by: TsiChung Liew + +commit 1b2708442224a551a0b865b52710306333888932 +Author: TsiChung Liew +Date: Wed Oct 22 11:55:30 2008 +0000 + + ColdFire: Fix compilation error + + The error was caused by the change for strmhz() in cpu.c. + A few of them were one extra close parenthesis. + + Signed-off-by: TsiChung Liew + +commit 536e7dac16769954915a484e682a2efb28699133 +Author: TsiChung Liew +Date: Wed Oct 22 11:38:21 2008 +0000 + + ColdFire: Add MCF5301x CPU and M53017EVB support + + Signed-off-by: TsiChung Liew + +commit a21d0c2cc9add8894d971ab791f4032f077db817 +Author: TsiChung Liew +Date: Tue Oct 21 15:37:02 2008 +0000 + + ColdFire: Add SBF support for M52277EVB + + Add serial boot support + + Signed-off-by: TsiChung Liew + +commit b202816c61042c183fe67d097a5893b0f2dafba0 +Author: TsiChung Liew +Date: Tue Oct 21 14:19:26 2008 +0000 + + ColdFire: Use CFI driver for M5272C3 + + Signed-off-by: TsiChung Liew + +commit f3962d3f574e5a1cffacd4e9bc48713060a2a314 +Author: TsiChung Liew +Date: Tue Oct 21 13:47:54 2008 +0000 + + ColdFire: Relocate FEC's GPIO and mii functions protocols + + Place FEC pin assignments in cpu_init.c from platform's + mii.c + + Signed-off-by: TsiChung Liew + +commit 6e80f5aa09f8d41bac50b38dc7488ecd22107802 +Author: TsiChung Liew +Date: Tue Oct 21 12:15:44 2008 +0000 + + ColdFire: Remove platforms mii.c file + + Will use mcfmii.c driver in drivers/net rather than + keep creating new mii.c for each future platform. + Remove EB+MCF-EV123, cobra5272, idmr, M5235EVB, + M5271EVB, M5272C3, M5275EVB, M5282EVB, M5329EVB, + M5373EVB, M54451EVB, M54455EVB, M547xEVB, and M548xEVB's + mii.c + + Signed-off-by: TsiChung Liew + +commit 012522fef3b382469125beb46a315ab4dee02fb0 +Author: TsiChung Liew +Date: Tue Oct 21 10:03:07 2008 +0000 + + ColdFire: Modules header files cleanup + + Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG, + MDHA, SKHA, INTC, and FlexBus structures and + definitions in immap_5xxx.h to more unify modules + header files. Append DSPI support for m547x_8x. + SSI cleanup. Remove USB Host structure from immap_539.h. + Apply changes to use FlexBus structures in mcf52x2's + cpu_init.c and platform configuration files. + + Signed-off-by: TsiChung Liew + +commit ac2331aee99ad36be0fcfed8c49922e3c61b576d +Author: TsiChung Liew +Date: Tue Oct 21 08:52:36 2008 +0000 + + ColdFire: Remove linker file + + Each different build for M54455EVB and M5235EVB will + create a u-boot.lds linker file. It is redundant to + keep the u-boot.lds + + Signed-off-by: TsiChung Liew + +commit 0829323073c505556ed5f5073f91adb504584d45 +Author: Peter Tyser +Date: Fri Oct 31 11:26:44 2008 -0500 + + ppc: Fix compile warnings when !CONFIG_OF_LIBFDT + + Signed-off-by: Peter Tyser + +commit a80b21d5127583171d6e9bc7f722947641898012 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Fri Oct 31 12:12:12 2008 +0100 + + common/Makefile: create others group for non core, environment and command files + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 60c68d9c1c6d18ce02c862a05718fd94f97c13d0 +Author: Wolfgang Denk +Date: Fri Oct 31 01:13:37 2008 +0100 + + TQM8260: use CFI flash driver instead of custom driver. + + Signed-off-by: Wolfgang Denk + +commit 20d04774f4ef3f6e38974636e0e36ae0f0b5501f +Author: Andy Fleming +Date: Thu Oct 30 17:35:30 2008 -0500 + + Consolidate MAX/MIN definitions + + There were several, now there is one (two if you count the lower-case + versions). + + Signed-off-by: Andy Fleming + +commit 298e476c66fd88d0bc4f0371118652d2b5de4e8a +Author: Heiko Schocher +Date: Thu Oct 30 09:23:09 2008 +0100 + + mgsuvd: remove unused defines in config file. + + Signed-off-by: Heiko Schocher + +commit 3cbd823116ea8b7c654e275a8c2fca87cd1f5dc5 +Author: Wolfgang Denk +Date: Sun Nov 2 16:14:22 2008 +0100 + + Coding Style cleanup, update CHANGELOG + + Signed-off-by: Wolfgang Denk + commit a47f957ab523019992fdef857af01bd71c58a4da Author: Alessandro Rubini Date: Fri Oct 31 22:33:21 2008 +0100 diff --git a/board/afeb9260/partition.c b/board/afeb9260/partition.c index 0b5dc5e06..be08f295f 100644 --- a/board/afeb9260/partition.c +++ b/board/afeb9260/partition.c @@ -34,4 +34,3 @@ dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, {0x00008400, 0x00041FFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"}, }; - diff --git a/common/cmd_ubi.c b/common/cmd_ubi.c index 4c358924e..5c31f7b49 100644 --- a/common/cmd_ubi.c +++ b/common/cmd_ubi.c @@ -601,7 +601,7 @@ static int do_ubi(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(ubi, 6, 1, do_ubi, "ubi - ubi commands\n", - "part [nand|nor|onenand] [part]" + "part [nand|nor|onenand] [part]" " - Show or set current partition\n" "ubi info [l[ayout]]" " - Display volume and ubi layout information\n" diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 18308c8a7..66f9164d5 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -131,7 +131,7 @@ void cpu_init_f(void) mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ mbar2_writeByte(MCFSIM_SPURVEC, 0x00); - /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); *//* Enable a 1 cycle pre-drive cycle on CS1 */ + /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */ /* FlexBus Chipselect */ init_fbcs(); diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 6645cb882..63cc8dbcd 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -982,5 +982,3 @@ unlock_ram_in_cache: blr #endif #endif - - diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 1f0b56cb7..d09c4c215 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -706,4 +706,3 @@ int cpu_eth_init(bd_t *bis) #endif return 0; } - diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 4b5349ead..f2b8908b9 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -727,7 +727,7 @@ _start: ori r2,r2,0xffff mfdcr r1,ISRAM1_DPC and r1,r1,r2 /* Disable parity check */ - mtdcr ISRAM1_DPC,r1 + mtdcr ISRAM1_DPC,r1 mfdcr r1,ISRAM1_PMEG and r1,r1,r2 /* Disable pwr mgmt */ mtdcr ISRAM1_PMEG,r1 diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index f12dedf89..a27de5a7e 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -434,4 +434,3 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) send_stop(); return(failures); } - diff --git a/drivers/mtd/ubi/crc32.c b/drivers/mtd/ubi/crc32.c index 5273ca3e0..a7e26b045 100644 --- a/drivers/mtd/ubi/crc32.c +++ b/drivers/mtd/ubi/crc32.c @@ -97,7 +97,7 @@ u32 crc32_le(u32 crc, unsigned char const *p, size_t len) # else # define DO_CRC(x) crc = tab[ ((crc >> 24) ^ (x)) & 255] ^ (crc<<8) # endif - //printf("Crc32_le crc=%x\n",crc); + /* printf("Crc32_le crc=%x\n",crc); */ crc = __cpu_to_le32(crc); /* Align it */ if((((long)b)&3 && len)){ diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c index 2d44f232a..842389400 100644 --- a/drivers/mtd/ubi/io.c +++ b/drivers/mtd/ubi/io.c @@ -186,7 +186,7 @@ retry: if (read != len && err == -EBADMSG) { ubi_assert(0); printk("%s[%d] not here\n", __func__, __LINE__); -// err = -EIO; +/* err = -EIO; */ } } else { ubi_assert(len == read); diff --git a/drivers/mtd/ubi/vmt.c b/drivers/mtd/ubi/vmt.c index a87a2f367..061da649e 100644 --- a/drivers/mtd/ubi/vmt.c +++ b/drivers/mtd/ubi/vmt.c @@ -260,7 +260,7 @@ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req) goto out_unlock; } - /* Calculate how many eraseblocks are requested */ + /* Calculate how many eraseblocks are requested */ vol->usable_leb_size = ubi->leb_size - ubi->leb_size % req->alignment; bytes = req->bytes; if (do_div(bytes, vol->usable_leb_size)) diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index d0e3cda6c..f9f10021b 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -490,7 +490,7 @@ #endif /* Memory Bank 1 (RESET) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x7f817200 //0x03017200 +#define CONFIG_SYS_EBC_PB1AP 0x7f817200 /* 0x03017200 */ #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_RESET_BASE | 0x1c000) /* Memory Bank 4 (FPGA / 32Bit) initialization */ diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index 90e553d74..d63a1a07f 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -167,4 +167,3 @@ #endif #endif - diff --git a/include/linux/crc32.h b/include/linux/crc32.h index e1331571e..ac4aed1c7 100644 --- a/include/linux/crc32.h +++ b/include/linux/crc32.h @@ -6,10 +6,10 @@ #define _LINUX_CRC32_H #include -//#include +/* #include */ extern u32 crc32_le(u32 crc, unsigned char const *p, size_t len); -//extern u32 crc32_be(u32 crc, unsigned char const *p, size_t len); +/* extern u32 crc32_be(u32 crc, unsigned char const *p, size_t len); */ #define crc32(seed, data, length) crc32_le(seed, (unsigned char const *)data, length) @@ -21,7 +21,7 @@ extern u32 crc32_le(u32 crc, unsigned char const *p, size_t len); * is in bit nr 0], thus it must be reversed before use. Except for * nics that bit swap the result internally... */ -//#define ether_crc(length, data) bitrev32(crc32_le(~0, data, length)) -//#define ether_crc_le(length, data) crc32_le(~0, data, length) +/* #define ether_crc(length, data) bitrev32(crc32_le(~0, data, length)) */ +/* #define ether_crc_le(length, data) crc32_le(~0, data, length) */ #endif /* _LINUX_CRC32_H */ diff --git a/include/linux/mtd/partitions.h b/include/linux/mtd/partitions.h index b41e5f564..10166757b 100644 --- a/include/linux/mtd/partitions.h +++ b/include/linux/mtd/partitions.h @@ -76,9 +76,9 @@ struct device; struct device_node; int __devinit of_mtd_parse_partitions(struct device *dev, - struct mtd_info *mtd, - struct device_node *node, - struct mtd_partition **pparts); + struct mtd_info *mtd, + struct device_node *node, + struct mtd_partition **pparts); #endif #endif diff --git a/include/linux/mtd/ubi.h b/include/linux/mtd/ubi.h index a017891ac..4b3e06ce5 100644 --- a/include/linux/mtd/ubi.h +++ b/include/linux/mtd/ubi.h @@ -21,7 +21,7 @@ #ifndef __LINUX_UBI_H__ #define __LINUX_UBI_H__ -//#include +/* #include */ #include #include diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h index 095dfc1b2..b4152192a 100644 --- a/include/ubi_uboot.h +++ b/include/ubi_uboot.h @@ -56,7 +56,7 @@ do { \ #define ubi_sysfs_close(...) do { } while (0) static inline int is_power_of_2(unsigned long n) { - return (n != 0 && ((n & (n - 1)) == 0)); + return (n != 0 && ((n & (n - 1)) == 0)); } /* FIXME */ From 4a0f7538c5c0805fd9a791967bbabacc41deadd9 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 16 Dec 2008 14:41:02 +0100 Subject: [PATCH 047/188] Makefile: fix dependency problem with parallel builds Parallel builds (using "make -jN") would occasionally fail with error messages like include/autoconf.mk:212: *** missing separator. Stop. Line numbers and affected boards were changing. Obviously some Makefiles included autoconf.mk while it was still being written to. As a fix, we now write to a temporary file first and then rename it, so that it is really ready to use as soon as it appears. Signed-off-by: Wolfgang Denk --- Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index d6cd91a51..1fd03a032 100644 --- a/Makefile +++ b/Makefile @@ -463,7 +463,8 @@ $(obj)include/autoconf.mk: $(obj)include/config.h set -e ; \ : Extract the config macros ; \ $(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h | \ - sed -n -f tools/scripts/define2mk.sed > $@ + sed -n -f tools/scripts/define2mk.sed > $@.tmp && \ + mv $@.tmp $@ sinclude $(obj)include/autoconf.mk.dep From aa1bcca3d2e22af4dea9f02132f9b56a30378ded Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 16 Dec 2008 14:44:06 +0100 Subject: [PATCH 048/188] post/Makefile: fix dependency problem with parallel builds Parallel builds (using "make -jN") would occasionally fail with error messages like ppc_4xxFP-objdump: string.o: File format not recognized or post/libpost.a(cpu.o): In function `cpu_post_test': /home/wd/git/u-boot/work/post/lib_ppc/cpu.c:130: undefined reference to `cpu_post_test_string' or similar. We now make sure to run the 'postdeps" step before attempting to build the specific POST libraries. Signed-off-by: Wolfgang Denk --- post/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/post/Makefile b/post/Makefile index 666a89649..769e9c639 100644 --- a/post/Makefile +++ b/post/Makefile @@ -45,7 +45,7 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) LIB := $(obj)$(LIB) -all: postdeps $(LIB) +all: $(LIB) postdeps: @for lib in $(SPLIB-y) ; do \ @@ -57,7 +57,7 @@ $(GPLIB): $(obj).depend $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) # specific POST libraries -$(SPLIB): $(obj).depend +$(SPLIB): $(obj).depend postdeps $(MAKE) -C $(dir $(subst $(obj),,$@)) # the POST lib archive From 6cdadcb3f1b6eac4a1c4256acaa1438413f95351 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 16 Dec 2008 16:22:50 +0100 Subject: [PATCH 049/188] trab: make trab_fkt standalone code independent of libgcc Use our own local functions in lib_arm/ instead. Signed-off-by: Wolfgang Denk --- board/trab/Makefile | 3 ++- board/trab/trab_fkt.c | 6 ++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/board/trab/Makefile b/board/trab/Makefile index 6dfcb8709..30e5fbbb3 100644 --- a/board/trab/Makefile +++ b/board/trab/Makefile @@ -51,7 +51,8 @@ $(obj)trab_fkt.srec: $(OBJS_FKT) $(LIB) $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e trab_fkt $^ $(LIB) \ -L$(obj)../../examples -lstubs \ -L$(obj)../../lib_generic -lgeneric \ - -L$(gcclibdir) -lgcc + $(obj)../../lib_arm/div0.o \ + $(obj)../../lib_arm/_*.o $(OBJCOPY) -O srec $(<:.o=) $@ $(obj)trab_fkt.bin: $(obj)trab_fkt.srec diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c index 93b9490e1..53cdb5a31 100644 --- a/board/trab/trab_fkt.c +++ b/board/trab/trab_fkt.c @@ -294,6 +294,12 @@ int trab_fkt (int argc, char *argv[]) return 1; } +void hang (void) +{ + puts ("### ERROR ### Please RESET the board ###\n"); + for (;;); +} + int do_info (void) { printf ("Stand-alone application for TRAB board function test\n"); From b1ffecec37b57a59c139042267faac458e5324e9 Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Wed, 3 Dec 2008 23:04:37 -0600 Subject: [PATCH 050/188] powerpc: fix io.h build warning with CONFIG_PHYS_64BIT Casting a pointer to a phys_addr_t when it's an unsigned long long on a 32-bit system without first casting to a non-pointer type generates a compiler warning. Fix this. Signed-off-by: Becky Bruce --- include/asm-ppc/io.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index c00de452d..64cb746b1 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -300,7 +300,7 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) static inline phys_addr_t virt_to_phys(void * vaddr) { - return (phys_addr_t)(vaddr); + return (phys_addr_t)((unsigned long)vaddr); } #endif From 584eedab66d0828f2d571a24b10526c4e65f547b Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Thu, 11 Dec 2008 05:51:57 +0300 Subject: [PATCH 051/188] jffs2: include instead of defining own min_t Include header for min_t definition instead of providing our own one. Removes warnings in case of OneNAND support enabled. Although I thinks it's a bit silly to include just for min_t... Signed-off-by: Ilya Yanok Acked-by: Stefan Roese --- fs/jffs2/jffs2_1pass.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index be7c1a190..11b66ab4b 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -119,6 +119,7 @@ #include #include #include +#include #include "jffs2_private.h" @@ -1408,11 +1409,6 @@ dump_dirents(struct b_lists *pL) } #endif -#define min_t(type, x, y) ({ \ - type __min1 = (x); \ - type __min2 = (y); \ - __min1 < __min2 ? __min1: __min2; }) - #define DEFAULT_EMPTY_SCAN_SIZE 4096 static inline uint32_t EMPTY_SCAN_SIZE(uint32_t sector_size) From ff49ea8977b56916edd5b1766d9939010e30b181 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Tue, 16 Dec 2008 14:24:16 -0600 Subject: [PATCH 052/188] NAND: Mark the BBT as scanned prior to calling scan_bbt. Otherwise, recursion can occur if scan_bbt does not find a bad block table, and tries to write one, and the attempt to erase the BBT area causes a bad block check. Signed-off-by: Scott Wood --- drivers/mtd/nand/nand_base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index ba05b762e..94a65d4e7 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -460,8 +460,8 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, struct nand_chip *chip = mtd->priv; if (!(chip->options & NAND_BBT_SCANNED)) { - chip->scan_bbt(mtd); chip->options |= NAND_BBT_SCANNED; + chip->scan_bbt(mtd); } if (!chip->bbt) From 45ca04f2377361593151d2d4da51f8ba4832d233 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 16 Dec 2008 22:32:25 +0100 Subject: [PATCH 053/188] board/trab/memory.c: Fix compile problems. Apply changes from commit 44b4dbed to board/trab/memory.c, too. Actually we'd need a major cleanup here - as it turns out, board/trab/memory.c is more or less a verbatim copy of post/drivers/memory.c ... but then, trab is EOL anyway,r so this is not worth the effort. Signed-off-by: Wolfgang Denk --- board/trab/memory.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/trab/memory.c b/board/trab/memory.c index 8fb3d2c12..895b68ef7 100644 --- a/board/trab/memory.c +++ b/board/trab/memory.c @@ -184,7 +184,7 @@ * * For other processors, let the compiler generate the best code it can. */ -static void move64(unsigned long long *src, unsigned long long *dest) +static void move64(const unsigned long long *src, unsigned long long *dest) { #if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X) asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ @@ -231,12 +231,12 @@ static int memory_post_dataline(unsigned long long * pmem) int ret = 0; for ( i = 0; i < num_patterns; i++) { - move64((unsigned long long *)&(pattern[i]), pmem++); + move64(&(pattern[i]), pmem++); /* * Put a different pattern on the data lines: otherwise they * may float long enough to read back what we wrote. */ - move64((unsigned long long *)&otherpattern, pmem--); + move64(&otherpattern, pmem--); move64(pmem, &temp64); #ifdef INJECT_DATA_ERRORS From 9e2a79b4c585ad31138fb90b68fd0234d64a8da8 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 16 Dec 2008 23:13:46 +0100 Subject: [PATCH 054/188] include/configs/at91cap9adk.h: fix typo. Signed-off-by: Wolfgang Denk --- include/configs/at91cap9adk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index 363df67b5..b2baf1b34 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -32,7 +32,7 @@ #define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define AT91_MASTER_CLOCK 100000000 /* peripheral */ #define AT91_CPU_CLOCK 200000000 /* cpu */ -#define CONFUG_SYS_AT91_PLLB 0x10073e01 /* PLLB settings for USB */ +#define CONFIG_SYS_AT91_PLLB 0x10073e01 /* PLLB settings for USB */ #define CONFIG_SYS_HZ 1000000 /* 1us resolution */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ From aced78d852d0b009e8aaa1445af8cb40861ee549 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 16 Dec 2008 23:48:27 +0100 Subject: [PATCH 055/188] Prepare 2009.01-rc1 Signed-off-by: Wolfgang Denk --- CHANGELOG | 102 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ Makefile | 6 ++-- 2 files changed, 105 insertions(+), 3 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 0c9c0479c..9af36c123 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,105 @@ +commit 9e2a79b4c585ad31138fb90b68fd0234d64a8da8 +Author: Wolfgang Denk +Date: Tue Dec 16 23:13:46 2008 +0100 + + include/configs/at91cap9adk.h: fix typo. + + Signed-off-by: Wolfgang Denk + +commit 45ca04f2377361593151d2d4da51f8ba4832d233 +Author: Wolfgang Denk +Date: Tue Dec 16 22:32:25 2008 +0100 + + board/trab/memory.c: Fix compile problems. + + Apply changes from commit 44b4dbed to board/trab/memory.c, too. + + Actually we'd need a major cleanup here - as it turns out, + board/trab/memory.c is more or less a verbatim copy of + post/drivers/memory.c ... but then, trab is EOL anyway,r + so this is not worth the effort. + + Signed-off-by: Wolfgang Denk + +commit 584eedab66d0828f2d571a24b10526c4e65f547b +Author: Ilya Yanok +Date: Thu Dec 11 05:51:57 2008 +0300 + + jffs2: include instead of defining own min_t + + Include header for min_t definition instead of + providing our own one. Removes warnings in case of OneNAND support + enabled. + + Although I thinks it's a bit silly to include + just for min_t... + + Signed-off-by: Ilya Yanok + Acked-by: Stefan Roese + +commit b1ffecec37b57a59c139042267faac458e5324e9 +Author: Becky Bruce +Date: Wed Dec 3 23:04:37 2008 -0600 + + powerpc: fix io.h build warning with CONFIG_PHYS_64BIT + + Casting a pointer to a phys_addr_t when it's an unsigned long long + on a 32-bit system without first casting to a non-pointer type + generates a compiler warning. Fix this. + + Signed-off-by: Becky Bruce + +commit 6cdadcb3f1b6eac4a1c4256acaa1438413f95351 +Author: Wolfgang Denk +Date: Tue Dec 16 16:22:50 2008 +0100 + + trab: make trab_fkt standalone code independent of libgcc + + Use our own local functions in lib_arm/ instead. + + Signed-off-by: Wolfgang Denk + +commit aa1bcca3d2e22af4dea9f02132f9b56a30378ded +Author: Wolfgang Denk +Date: Tue Dec 16 14:44:06 2008 +0100 + + post/Makefile: fix dependency problem with parallel builds + + Parallel builds (using "make -jN") would occasionally fail with error + messages like + ppc_4xxFP-objdump: string.o: File format not recognized + or + post/libpost.a(cpu.o): In function `cpu_post_test': + /home/wd/git/u-boot/work/post/lib_ppc/cpu.c:130: undefined reference to `cpu_post_test_string' + or similar. We now make sure to run the 'postdeps" step before + attempting to build the specific POST libraries. + + Signed-off-by: Wolfgang Denk + +commit 4a0f7538c5c0805fd9a791967bbabacc41deadd9 +Author: Wolfgang Denk +Date: Tue Dec 16 14:41:02 2008 +0100 + + Makefile: fix dependency problem with parallel builds + + Parallel builds (using "make -jN") would occasionally fail with error + messages like + include/autoconf.mk:212: *** missing separator. Stop. + Line numbers and affected boards were changing. Obviously some + Makefiles included autoconf.mk while it was still being written to. + As a fix, we now write to a temporary file first and then rename it, + so that it is really ready to use as soon as it appears. + + Signed-off-by: Wolfgang Denk + +commit 455ae7e87f67c44e6aea68865c83acadd3fcd36c +Author: Wolfgang Denk +Date: Tue Dec 16 01:02:17 2008 +0100 + + Coding style cleanup, update CHANGELOG. + + Signed-off-by: Wolfgang Denk + commit 84bc72d90c505fec3ef4b693995407a0bd4064e5 Author: Mike Frysinger Date: Thu Dec 11 18:39:08 2008 -0500 diff --git a/Makefile b/Makefile index 1fd03a032..4df48129b 100644 --- a/Makefile +++ b/Makefile @@ -21,10 +21,10 @@ # MA 02111-1307 USA # -VERSION = 2008 -PATCHLEVEL = 10 +VERSION = 2009 +PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = +EXTRAVERSION = -rc1 ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else From 13095b2f07dacb1f863772266c1789d47a523a8a Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 16 Dec 2008 22:10:30 +0100 Subject: [PATCH 056/188] MIPS: qemu_mips: move env storage just after u-boot Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Shinya Kuribayashi --- include/configs/qemu-mips.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index f028d1ac6..844446205 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -150,7 +150,7 @@ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) /* Address and size of Primary Environment Sector */ #define CONFIG_ENV_SIZE 0x8000 From 16cdf816779f5b602a9b3b4d2ea4dea05095c35b Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 16 Dec 2008 22:10:31 +0100 Subject: [PATCH 057/188] MIPS: qemu_mips: update doc to use all disk and boot linux kernel Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Shinya Kuribayashi --- doc/README.qemu_mips | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/doc/README.qemu_mips b/doc/README.qemu_mips index 2fdd2b03a..8fa4907cb 100644 --- a/doc/README.qemu_mips +++ b/doc/README.qemu_mips @@ -17,12 +17,47 @@ create image: start it: # qemu-system-mips -M mips -pflash flash -monitor null -nographic +Ide Disk + +# dd of=ide bs=1k cout=100k if=/dev/zero + +# sfdisk -C 261 -d ide +# partition table of ide +unit: sectors + + ide1 : start= 63, size= 32067, Id=83 + ide2 : start= 32130, size= 32130, Id=83 + ide3 : start= 64260, size= 4128705, Id=83 + ide4 : start= 0, size= 0, Id= 0 + +# Generate uImage +# tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage +# Copy to Flash +# dd if=uImage bs=1k conv=notrunc seek=224 of=flash +# Copy to ide +# dd if=uImage bs=512 conv=notrunc seek=63 of=ide + +# Generate ext2 on part 2 +# Attached as loop device ide offset = 32130 * 512 +# losetup -o 16450560 -f ide +# Format as ext2 ( arg2 : nb blocks) +# mke2fs /dev/loop0 16065 +# losetup -d /dev/loop0 +# Mount and copy uImage and initrd.gz to it +# mount -o loop,offset=16450560 -t ext2 ide /mnt +# Umount it +# umount /mnt + +Now you can boot from flash, ide, ide+ext2 and tfp + +# qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide + II) How to debug U-Boot In order to debug U-Boot you need to start qemu with gdb server support (-s) and waiting the connection to start the CPU (-S) -# qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic +# qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide in an other console you start gdb From b616f2b545f73757669b37386f0b37bb61fc6797 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Mon, 8 Sep 2008 22:27:18 +0200 Subject: [PATCH 058/188] MIPS: qemu_mips: update doc to generate and to use qemu flash, ide file Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Shinya Kuribayashi --- doc/README.qemu_mips | 67 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 58 insertions(+), 9 deletions(-) diff --git a/doc/README.qemu_mips b/doc/README.qemu_mips index 8fa4907cb..398526424 100644 --- a/doc/README.qemu_mips +++ b/doc/README.qemu_mips @@ -17,7 +17,28 @@ create image: start it: # qemu-system-mips -M mips -pflash flash -monitor null -nographic -Ide Disk +2) Download kernel + initrd + +On ftp://ftp.denx.de/pub/contrib/Jean-Christophe_Plagniol-Villard/qemu_mips/ +you can downland + +#config to build the kernel +qemu_mips_defconfig +#patch to fix mips interupt init on 2.6.24.y kernel +qemu_mips_kernel.patch +initrd.gz +vmlinux +vmlinux.bin +System.map + +4) Generate uImage + +# tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage + +5) Copy uImage to Flash +# dd if=uImage bs=1k conv=notrunc seek=224 of=flash + +6) Generate Ide Disk # dd of=ide bs=1k cout=100k if=/dev/zero @@ -30,14 +51,12 @@ unit: sectors ide3 : start= 64260, size= 4128705, Id=83 ide4 : start= 0, size= 0, Id= 0 -# Generate uImage -# tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage -# Copy to Flash -# dd if=uImage bs=1k conv=notrunc seek=224 of=flash -# Copy to ide +7) Copy to ide + # dd if=uImage bs=512 conv=notrunc seek=63 of=ide -# Generate ext2 on part 2 +8) Generate ext2 on part 2 on Copy uImage and initrd.gz + # Attached as loop device ide offset = 32130 * 512 # losetup -o 16450560 -f ide # Format as ext2 ( arg2 : nb blocks) @@ -45,10 +64,40 @@ unit: sectors # losetup -d /dev/loop0 # Mount and copy uImage and initrd.gz to it # mount -o loop,offset=16450560 -t ext2 ide /mnt +# mkdir /mnt/boot +# cp {initrd.gz,uImage} /mnt/boot/ # Umount it # umount /mnt -Now you can boot from flash, ide, ide+ext2 and tfp +9) Set Environment + +setenv rd_start 0x80800000 +setenv rd_size 2663940 +setenv kernel BFC38000 +setenv oad_addr 80500000 +setenv load_addr2 80F00000 +setenv kernel_flash BFC38000 +setenv load_addr_hello 80200000 +setenv bootargs 'root=/dev/ram0 init=/bin/sh' +setenv load_rd_ext2 'ide res; ext2load ide 0:2 ${rd_start} /boot/initrd.gz' +setenv load_rd_tftp 'tftp ${rd_start} /initrd.gz' +setenv load_kernel_hda 'ide res; diskboot ${load_addr} 0:2' +setenv load_kernel_ext2 'ide res; ext2load ide 0:2 ${load_addr} /boot/uImage' +setenv load_kernel_tftp 'tftp ${load_addr} /qemu_mips/uImage' +setenv boot_ext2_ext2 'run load_rd_ext2; run load_kernel_ext2; run addmisc; bootm ${load_addr}' +setenv boot_ext2_flash 'run load_rd_ext2; run addmisc; bootm ${kernel_flash}' +setenv boot_ext2_hda 'run load_rd_ext2; run load_kernel_hda; run addmisc; bootm ${load_addr}' +setenv boot_ext2_tftp 'run load_rd_ext2; run load_kernel_tftp; run addmisc; bootm ${load_addr}' +setenv boot_tftp_hda 'run load_rd_tftp; run load_kernel_hda; run addmisc; bootm ${load_addr}' +setenv boot_tftp_ext2 'run load_rd_tftp; run load_kernel_ext2; run addmisc; bootm ${load_addr}' +setenv boot_tftp_flash 'run load_rd_tftp; run addmisc; bootm ${kernel_flash}' +setenv boot_tftp_tftp 'run load_rd_tftp; run load_kernel_tftp; run addmisc; bootm ${load_addr}' +setenv load_hello_tftp 'tftp ${load_addr_hello} /examples/hello_world.bin' +setenv go_tftp 'run load_hello_tftp; go ${load_addr_hello}' +setenv addmisc 'setenv bootargs ${bootargs} console=ttyS0,${baudrate} rd_start=${rd_start} rd_size=${rd_size} ethaddr=${ethaddr}' +setenv bootcmd 'run boot_tftp_flash' + +10) Now you can boot from flash, ide, ide+ext2 and tfp # qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide @@ -64,7 +113,7 @@ in an other console you start gdb 1) Debugging of U-Boot Before Relocation Before relocation, the addresses in the ELF file can be used without any problems -buy connecting to the gdb server localhost:1234 +by connecting to the gdb server localhost:1234 # mipsel-unknown-linux-gnu-gdb u-boot GNU gdb 6.6 From 92c78a3bbcb2ce508b4bf1c4a1e0940406a024bb Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Wed, 17 Dec 2008 16:43:18 +0100 Subject: [PATCH 059/188] avr32: Remove second definition of virt_to_phys() The second definition introduced by 65e43a1063 conflicts with the existing one. Also, convert the existing definition to use phys_addr_t. The volatile qualifier is still needed due to brain damage elsewhere. Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/io.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h index d22cd3561..50967ac7e 100644 --- a/include/asm-avr32/io.h +++ b/include/asm-avr32/io.h @@ -76,12 +76,12 @@ extern void __readwrite_bug(const char *fn); #include /* virt_to_phys will only work when address is in P1 or P2 */ -static __inline__ unsigned long virt_to_phys(volatile void *address) +static inline phys_addr_t virt_to_phys(volatile void *address) { return PHYSADDR(address); } -static __inline__ void * phys_to_virt(unsigned long address) +static inline void *phys_to_virt(phys_addr_t address) { return (void *)P1SEGADDR(address); } @@ -125,9 +125,4 @@ static inline void unmap_physmem(void *vaddr, unsigned long len) } -static inline phys_addr_t virt_to_phys(void * vaddr) -{ - return (phys_addr_t)(vaddr); -} - #endif /* __ASM_AVR32_IO_H */ From 7a8979591171676417ab36852d8811a8c46accd8 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Wed, 29 Oct 2008 12:39:26 -0500 Subject: [PATCH 060/188] pci/fsl_pci_init: Enable inbound PCI config cycles Add fsl_pci_config_unlock() function to enable a PCI/PCIe interface configured in agent/endpoint mode to respond to inbound PCI configuration cycles. Signed-off-by: Peter Tyser --- drivers/pci/fsl_pci_init.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 1db42fd8d..db68f2600 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -37,6 +37,11 @@ DECLARE_GLOBAL_DATA_PTR; #include #include +/* Freescale-specific PCI config registers */ +#define FSL_PCI_PBFR 0x44 +#define FSL_PCIE_CAP_ID 0x4c +#define FSL_PCIE_CFG_RDY 0x4b0 + void pciauto_prescan_setup_bridge(struct pci_controller *hose, pci_dev_t dev, int sub_bus); void pciauto_postscan_setup_bridge(struct pci_controller *hose, @@ -306,6 +311,30 @@ void fsl_pci_init(struct pci_controller *hose) } } +/* Enable inbound PCI config cycles for agent/endpoint interface */ +void fsl_pci_config_unlock(struct pci_controller *hose) +{ + pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); + u8 agent; + u8 pcie_cap; + u16 pbfr; + + pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent); + if (!agent) + return; + + pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + if (pcie_cap != 0x0) { + /* PCIe - set CFG_READY bit of Configuration Ready Register */ + pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1); + } else { + /* PCI - clear ACL bit of PBFR */ + pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr); + pbfr &= ~0x20; + pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr); + } +} + #ifdef CONFIG_OF_BOARD_SETUP #include #include From e92739d34e2d6b6aca93b2598248210710897ce8 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Wed, 17 Dec 2008 16:36:21 -0600 Subject: [PATCH 061/188] Add support for PCA953x I2C gpio devices Initial support for NXP's 4 and 8 bit I2C gpio expanders (eg pca9537, pca9557, etc). The CONFIG_PCA953X define enables support for the devices while the CONFIG_CMD_PCA953X define enables the pca953x command. The CONFIG_CMD_PCA953X_INFO define enables an 'info' sub-command which provides summary information for the given pca953x device. Signed-off-by: Peter Tyser --- Makefile | 2 + README | 9 ++ drivers/gpio/Makefile | 47 +++++++++ drivers/gpio/pca953x.c | 227 +++++++++++++++++++++++++++++++++++++++++ include/pca953x.h | 39 +++++++ 5 files changed, 324 insertions(+) create mode 100644 drivers/gpio/Makefile create mode 100644 drivers/gpio/pca953x.c create mode 100644 include/pca953x.h diff --git a/Makefile b/Makefile index 4df48129b..0fc64902f 100644 --- a/Makefile +++ b/Makefile @@ -228,6 +228,7 @@ LIBS += drivers/bios_emulator/libatibiosemu.a LIBS += drivers/block/libblock.a LIBS += drivers/dma/libdma.a LIBS += drivers/fpga/libfpga.a +LIBS += drivers/gpio/libgpio.a LIBS += drivers/hwmon/libhwmon.a LIBS += drivers/i2c/libi2c.a LIBS += drivers/input/libinput.a @@ -407,6 +408,7 @@ TAG_SUBDIRS += disk TAG_SUBDIRS += common TAG_SUBDIRS += drivers/bios_emulator TAG_SUBDIRS += drivers/block +TAG_SUBDIRS += drivers/gpio TAG_SUBDIRS += drivers/hwmon TAG_SUBDIRS += drivers/i2c TAG_SUBDIRS += drivers/input diff --git a/README b/README index 2a553c274..eb86ebaf1 100644 --- a/README +++ b/README @@ -621,6 +621,8 @@ The following options need to be configured: CONFIG_CMD_MII * MII utility commands CONFIG_CMD_NAND * NAND support CONFIG_CMD_NET bootp, tftpboot, rarpboot + CONFIG_CMD_PCA953X * PCA953x I2C gpio commands + CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command CONFIG_CMD_PCI * pciinfo CONFIG_CMD_PCMCIA * PCMCIA support CONFIG_CMD_PING * send ICMP ECHO_REQUEST to network @@ -698,6 +700,13 @@ The following options need to be configured: Note that if the RTC uses I2C, then the I2C interface must also be configured. See I2C Support, below. +- GPIO Support: + CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO + CONFIG_PCA953X_INFO - enable pca953x info command + + Note that if the GPIO device uses I2C, then the I2C interface + must also be configured. See I2C Support, below. + - Timestamp Support: When CONFIG_TIMESTAMP is selected, the timestamp diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile new file mode 100644 index 000000000..dd618ed71 --- /dev/null +++ b/drivers/gpio/Makefile @@ -0,0 +1,47 @@ +# +# Copyright 2000-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libgpio.a + +COBJS-$(CONFIG_PCA953X) += pca953x.o + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################## diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c new file mode 100644 index 000000000..390d99ad3 --- /dev/null +++ b/drivers/gpio/pca953x.c @@ -0,0 +1,227 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Driver for NXP's 4 and 8 bit I2C gpio expanders (eg pca9537, pca9557, etc) + * TODO: support additional devices with more than 8-bits GPIO + */ + +#include +#include +#include + +/* Default to an address that hopefully won't corrupt other i2c devices */ +#ifndef CONFIG_SYS_I2C_PCA953X_ADDR +#define CONFIG_SYS_I2C_PCA953X_ADDR (~0) +#endif + +enum { + PCA953X_CMD_INFO, + PCA953X_CMD_DEVICE, + PCA953X_CMD_OUTPUT, + PCA953X_CMD_INPUT, + PCA953X_CMD_INVERT, +}; + +/* + * Modify masked bits in register + */ +static int pca953x_reg_write(uint8_t chip, uint addr, uint mask, uint data) +{ + uint8_t val; + + if (i2c_read(chip, addr, 1, &val, 1)) + return -1; + + val &= ~mask; + val |= data; + + return i2c_write(chip, addr, 1, &val, 1); +} + +/* + * Set output value of IO pins in 'mask' to corresponding value in 'data' + * 0 = low, 1 = high + */ +int pca953x_set_val(uint8_t chip, uint mask, uint data) +{ + return pca953x_reg_write(chip, PCA953X_OUT, mask, data); +} + +/* + * Set read polarity of IO pins in 'mask' to corresponding value in 'data' + * 0 = read pin value, 1 = read inverted pin value + */ +int pca953x_set_pol(uint8_t chip, uint mask, uint data) +{ + return pca953x_reg_write(chip, PCA953X_POL, mask, data); +} + +/* + * Set direction of IO pins in 'mask' to corresponding value in 'data' + * 0 = output, 1 = input + */ +int pca953x_set_dir(uint8_t chip, uint mask, uint data) +{ + return pca953x_reg_write(chip, PCA953X_CONF, mask, data); +} + +/* + * Read current logic level of all IO pins + */ +int pca953x_get_val(uint8_t chip) +{ + uint8_t val; + + if (i2c_read(chip, 0, 1, &val, 1)) + return -1; + + return (int)val; +} + +#ifdef CONFIG_CMD_PCA953X +#ifdef CONFIG_CMD_PCA953X_INFO +/* + * Display pca953x information + */ +static int pca953x_info(uint8_t chip) +{ + int i; + uint8_t data; + + printf("pca953x@ 0x%x:\n\n", chip); + printf("gpio pins: 76543210\n"); + printf("-------------------\n"); + + if (i2c_read(chip, PCA953X_CONF, 1, &data, 1)) + return -1; + printf("conf: "); + for (i = 7; i >= 0; i--) + printf("%c", data & (1 << i) ? 'i' : 'o'); + printf("\n"); + + if (i2c_read(chip, PCA953X_POL, 1, &data, 1)) + return -1; + printf("invert: "); + for (i = 7; i >= 0; i--) + printf("%c", data & (1 << i) ? '1' : '0'); + printf("\n"); + + if (i2c_read(chip, PCA953X_IN, 1, &data, 1)) + return -1; + printf("input: "); + for (i = 7; i >= 0; i--) + printf("%c", data & (1 << i) ? '1' : '0'); + printf("\n"); + + if (i2c_read(chip, PCA953X_OUT, 1, &data, 1)) + return -1; + printf("output: "); + for (i = 7; i >= 0; i--) + printf("%c", data & (1 << i) ? '1' : '0'); + printf("\n"); + + return 0; +} +#endif /* CONFIG_CMD_PCA953X_INFO */ + +cmd_tbl_t cmd_pca953x[] = { + U_BOOT_CMD_MKENT(device, 3, 0, (void *)PCA953X_CMD_DEVICE, "", ""), + U_BOOT_CMD_MKENT(output, 4, 0, (void *)PCA953X_CMD_OUTPUT, "", ""), + U_BOOT_CMD_MKENT(input, 3, 0, (void *)PCA953X_CMD_INPUT, "", ""), + U_BOOT_CMD_MKENT(invert, 4, 0, (void *)PCA953X_CMD_INVERT, "", ""), +#ifdef CONFIG_CMD_PCA953X_INFO + U_BOOT_CMD_MKENT(info, 2, 0, (void *)PCA953X_CMD_INFO, "", ""), +#endif +}; + +int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + static uint8_t chip = CONFIG_SYS_I2C_PCA953X_ADDR; + int val; + ulong ul_arg2 = 0; + ulong ul_arg3 = 0; + cmd_tbl_t *c; + + c = find_cmd_tbl(argv[1], cmd_pca953x, ARRAY_SIZE(cmd_pca953x)); + + /* All commands but "device" require 'maxargs' arguments */ + if (!c || !((argc == (c->maxargs)) || + (((int)c->cmd == PCA953X_CMD_DEVICE) && + (argc == (c->maxargs - 1))))) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* arg2 used as chip number or pin number */ + if (argc > 2) + ul_arg2 = simple_strtoul(argv[2], NULL, 16); + + /* arg3 used as pin or invert value */ + if (argc > 3) + ul_arg3 = simple_strtoul(argv[3], NULL, 16) & 0x1; + + switch ((int)c->cmd) { +#ifdef CONFIG_CMD_PCA953X_INFO + case PCA953X_CMD_INFO: + return pca953x_info(chip); +#endif + case PCA953X_CMD_DEVICE: + if (argc == 3) + chip = (uint8_t)ul_arg2; + printf("Current device address: 0x%x\n", chip); + return 0; + case PCA953X_CMD_INPUT: + pca953x_set_dir(chip, (1 << ul_arg2), + PCA953X_DIR_IN << ul_arg2); + val = (pca953x_get_val(chip) & (1 << ul_arg2)) != 0; + + printf("chip 0x%02x, pin 0x%lx = %d\n", chip, ul_arg2, val); + return val; + case PCA953X_CMD_OUTPUT: + pca953x_set_dir(chip, (1 << ul_arg2), + (PCA953X_DIR_OUT << ul_arg2)); + return pca953x_set_val(chip, (1 << ul_arg2), + (ul_arg3 << ul_arg2)); + case PCA953X_CMD_INVERT: + return pca953x_set_pol(chip, (1 << ul_arg2), + (ul_arg3 << ul_arg2)); + default: + /* We should never get here */ + return 1; + } +} + +U_BOOT_CMD( + pca953x, 5, 1, do_pca953x, + "pca953x - pca953x gpio access\n", + "device [dev]\n" + " - show or set current device address\n" +#ifdef CONFIG_CMD_PCA953X_INFO + "pca953x info\n" + " - display info for current chip\n" +#endif + "pca953x output pin 0|1\n" + " - set pin as output and drive low or high\n" + "pca953x invert pin 0|1\n" + " - disable/enable polarity inversion for reads\n" + "pca953x intput pin\n" + " - set pin as input and read value\n" +); + +#endif /* CONFIG_CMD_PCA953X */ diff --git a/include/pca953x.h b/include/pca953x.h new file mode 100644 index 000000000..6c2b58c56 --- /dev/null +++ b/include/pca953x.h @@ -0,0 +1,39 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __PCA953X_H_ +#define __PCA953X_H_ + +#define PCA953X_IN 0x00 +#define PCA953X_OUT 0x01 +#define PCA953X_POL 0x02 +#define PCA953X_CONF 0x03 + +#define PCA953X_OUT_LOW 0 +#define PCA953X_OUT_HIGH 1 +#define PCA953X_POL_NORMAL 0 +#define PCA953X_POL_INVERT 1 +#define PCA953X_DIR_OUT 0 +#define PCA953X_DIR_IN 1 + +int pca953x_set_val(u8 chip, uint mask, uint data); +int pca953x_set_pol(u8 chip, uint mask, uint data); +int pca953x_set_dir(u8 chip, uint mask, uint data); +int pca953x_get_val(u8 chip); + +#endif /* __PCA953X_H_ */ From ccf0fdd02b97323f8caae18d06cc9daeac2f192f Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Wed, 17 Dec 2008 16:36:23 -0600 Subject: [PATCH 062/188] XPedite5370 board support Initial support for Extreme Engineering Solutions XPedite5370 - a MPC8572-based 3U VPX single board computer with a PMC/XMC site. Signed-off-by: Peter Tyser --- MAINTAINERS | 3 + MAKEALL | 1 + Makefile | 3 + board/xes/common/Makefile | 56 +++ board/xes/common/fsl_8572_clk.c | 51 +++ board/xes/common/fsl_85xx_ddr.c | 93 +++++ board/xes/common/fsl_85xx_pci.c | 265 +++++++++++++ board/xes/xpedite5370/Makefile | 45 +++ board/xes/xpedite5370/config.mk | 35 ++ board/xes/xpedite5370/ddr.c | 270 +++++++++++++ board/xes/xpedite5370/law.c | 54 +++ board/xes/xpedite5370/tlb.c | 94 +++++ board/xes/xpedite5370/u-boot.lds | 145 +++++++ board/xes/xpedite5370/xpedite5370.c | 128 ++++++ include/configs/XPEDITE5370.h | 589 ++++++++++++++++++++++++++++ 15 files changed, 1832 insertions(+) create mode 100644 board/xes/common/Makefile create mode 100644 board/xes/common/fsl_8572_clk.c create mode 100644 board/xes/common/fsl_85xx_ddr.c create mode 100644 board/xes/common/fsl_85xx_pci.c create mode 100644 board/xes/xpedite5370/Makefile create mode 100644 board/xes/xpedite5370/config.mk create mode 100644 board/xes/xpedite5370/ddr.c create mode 100644 board/xes/xpedite5370/law.c create mode 100644 board/xes/xpedite5370/tlb.c create mode 100644 board/xes/xpedite5370/u-boot.lds create mode 100644 board/xes/xpedite5370/xpedite5370.c create mode 100644 include/configs/XPEDITE5370.h diff --git a/MAINTAINERS b/MAINTAINERS index f04879555..be10eb49a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -411,6 +411,9 @@ Rune Torgersen MPC8266ADS MPC8266 +Peter Tyser + + XPEDITE5370 MPC8572 David Updegraff diff --git a/MAKEALL b/MAKEALL index cc49a9808..a136bad7a 100755 --- a/MAKEALL +++ b/MAKEALL @@ -385,6 +385,7 @@ LIST_85xx=" \ TQM8548 \ TQM8555 \ TQM8560 \ + XPEDITE5370 \ " ######################################################################### diff --git a/Makefile b/Makefile index 0fc64902f..752a37066 100644 --- a/Makefile +++ b/Makefile @@ -2463,6 +2463,9 @@ TQM8560_config: unconfig echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; @$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc +XPEDITE5370_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5370 xes + ######################################################################### ## MPC86xx Systems ######################################################################### diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile new file mode 100644 index 000000000..c5cd6331e --- /dev/null +++ b/board/xes/common/Makefile @@ -0,0 +1,56 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif + +LIB = $(obj)lib$(VENDOR).a + +COBJS-$(CONFIG_MPC8572) += fsl_8572_clk.o +COBJS-$(CONFIG_MPC85xx) += fsl_85xx_ddr.o +COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xes/common/fsl_8572_clk.c b/board/xes/common/fsl_8572_clk.c new file mode 100644 index 000000000..f5df2dae8 --- /dev/null +++ b/board/xes/common/fsl_8572_clk.c @@ -0,0 +1,51 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config + */ +unsigned long get_board_sys_clk(ulong dummy) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 gpporcr = gur->gpporcr; + + if (gpporcr & 0x10000) + return 66666666; + else + return 50000000; +} + +/* + * Return DDR input clock - synchronous with SYSCLK or 66 MHz + */ +unsigned long get_board_ddr_clk(ulong dummy) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + + if (ddr_ratio == 0x7) + return get_board_sys_clk(dummy); + + return 66666666; +} diff --git a/board/xes/common/fsl_85xx_ddr.c b/board/xes/common/fsl_85xx_ddr.c new file mode 100644 index 000000000..30b476701 --- /dev/null +++ b/board/xes/common/fsl_85xx_ddr.c @@ -0,0 +1,93 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + + dram_size *= 0x100000; + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* Initialize and enable DDR ECC */ + ddr_enable_ecc(dram_size); +#endif + + return dram_size; +} + +#if defined(CONFIG_DDR_ECC) || (CONFIG_NUM_DDR_CONTROLLERS > 1) +void board_add_ram_info(int use_default) +{ +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + volatile ccsr_ddr_t *ddr1 = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); +#endif + + puts(" ("); + +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + /* Print interleaving information */ + if (ddr1->cs0_config & 0x20000000) { + switch ((ddr1->cs0_config >> 24) & 0xf) { + case 0: + puts("cache line"); + break; + case 1: + puts("page"); + break; + case 2: + puts("bank"); + break; + case 3: + puts("super-bank"); + break; + default: + puts("invalid"); + break; + } + } else { + puts("no"); + } + + puts(" interleaving"); +#endif + +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) && defined(CONFIG_DDR_ECC) + puts(", "); +#endif + +#if defined(CONFIG_DDR_ECC) + puts("ECC enabled"); +#endif + + puts(")"); +} +#endif /* CONFIG_DDR_ECC || CONFIG_NUM_DDR_CONTROLLERS > 1 */ diff --git a/board/xes/common/fsl_85xx_pci.c b/board/xes/common/fsl_85xx_pci.c new file mode 100644 index 000000000..b8e363ec9 --- /dev/null +++ b/board/xes/common/fsl_85xx_pci.c @@ -0,0 +1,265 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_init(struct pci_controller *hose); + +int first_free_busno = 0; + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif +#ifdef CONFIG_PCIE3 +static struct pci_controller pcie3_hose; +#endif + +/* Correlate host/agent POR bits to usable info. Table 4-14 */ +struct host_agent_cfg_t { + uchar pcie_root[3]; + uchar rio_host; +} host_agent_cfg[8] = { + {{0, 0, 0}, 0}, + {{0, 1, 1}, 1}, + {{1, 0, 1}, 0}, + {{1, 1, 0}, 1}, + {{0, 0, 1}, 0}, + {{0, 1, 0}, 1}, + {{1, 0, 0}, 0}, + {{1, 1, 1}, 1} +}; + +/* Correlate port width POR bits to usable info. Table 4-15 */ +struct io_port_cfg_t { + uchar pcie_width[3]; + uchar rio_width; +} io_port_cfg[16] = { + {{0, 0, 0}, 0}, + {{0, 0, 0}, 0}, + {{4, 0, 0}, 0}, + {{4, 4, 0}, 0}, + {{0, 0, 0}, 0}, + {{0, 0, 0}, 0}, + {{0, 0, 0}, 4}, + {{4, 2, 2}, 0}, + {{0, 0, 0}, 0}, + {{0, 0, 0}, 0}, + {{0, 0, 0}, 0}, + {{4, 0, 0}, 4}, + {{4, 0, 0}, 4}, + {{0, 0, 0}, 4}, + {{0, 0, 0}, 4}, + {{8, 0, 0}, 0}, +}; + +void pci_init_board(void) +{ + struct pci_controller *hose; + volatile ccsr_fsl_pci_t *pci; + int width; + int host; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + struct pci_region *r; + + debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", + devdisr, io_sel, host_agent); + +#ifdef CONFIG_PCIE1 + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; + hose = &pcie1_hose; + host = host_agent_cfg[host_agent].pcie_root[0]; + width = io_port_cfg[io_sel].pcie_width[0]; + r = hose->regions; + + if (width && !(devdisr & MPC85xx_DEVDISR_PCIE)) { + printf("\n PCIE1 connected as %s (x%d)", + host ? "Root Complex" : "End Point", width); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + printf("\n"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno = hose->last_busno+1; + printf(" PCIE1 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif /* CONFIG_PCIE1 */ + +#ifdef CONFIG_PCIE2 + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; + hose = &pcie2_hose; + host = host_agent_cfg[host_agent].pcie_root[1]; + width = io_port_cfg[io_sel].pcie_width[1]; + r = hose->regions; + + if (width && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { + printf("\n PCIE2 connected as %s (x%d)", + host ? "Root Complex" : "End Point", width); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + printf("\n"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCIE2_MEM_BASE, + CONFIG_SYS_PCIE2_MEM_PHYS, + CONFIG_SYS_PCIE2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCIE2_IO_BASE, + CONFIG_SYS_PCIE2_IO_PHYS, + CONFIG_SYS_PCIE2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno = hose->last_busno+1; + printf(" PCIE2 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ +#endif /* CONFIG_PCIE2 */ + +#ifdef CONFIG_PCIE3 + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; + hose = &pcie3_hose; + host = host_agent_cfg[host_agent].pcie_root[2]; + width = io_port_cfg[io_sel].pcie_width[2]; + r = hose->regions; + + if (width && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { + printf("\n PCIE3 connected as %s (x%d)", + host ? "Root Complex" : "End Point", width); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + printf("\n"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCIE3_MEM_BASE, + CONFIG_SYS_PCIE3_MEM_PHYS, + CONFIG_SYS_PCIE3_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCIE3_IO_BASE, + CONFIG_SYS_PCIE3_IO_PHYS, + CONFIG_SYS_PCIE3_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno = hose->last_busno+1; + printf(" PCIE3 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ +#endif /* CONFIG_PCIE3 */ +} + +#if defined(CONFIG_OF_BOARD_SETUP) +extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, + struct pci_controller *hose); + +void ft_board_pci_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_PCIE1 + ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); +#endif +#ifdef CONFIG_PCIE2 + ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); +#endif +#ifdef CONFIG_PCIE3 + ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); +#endif +} +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/xes/xpedite5370/Makefile b/board/xes/xpedite5370/Makefile new file mode 100644 index 000000000..919397c40 --- /dev/null +++ b/board/xes/xpedite5370/Makefile @@ -0,0 +1,45 @@ +# +# Copyright 2008 Extreme Engineering Solutions, Inc. +# Copyright 2007 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xes/xpedite5370/config.mk b/board/xes/xpedite5370/config.mk new file mode 100644 index 000000000..39469b22c --- /dev/null +++ b/board/xes/xpedite5370/config.mk @@ -0,0 +1,35 @@ +# +# Copyright 2008 Extreme Engineering Solutions, Inc. +# Copyright 2007-2008 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# xpedite5370 board +# +ifndef TEXT_BASE +TEXT_BASE = 0xfff80000 +endif + +PLATFORM_RELFLAGS += -mrelocatable + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8572=1 diff --git a/board/xes/xpedite5370/ddr.c b/board/xes/xpedite5370/ddr.c new file mode 100644 index 000000000..4d3f255d7 --- /dev/null +++ b/board/xes/xpedite5370/ddr.c @@ -0,0 +1,270 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include +#include + +static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, + sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0) + i2c_address = SPD_EEPROM_ADDRESS1; + if (ctrl_num == 1) + i2c_address = SPD_EEPROM_ADDRESS2; + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +/* + * There are four board-specific SDRAM timing parameters which must be + * calculated based on the particular PCB artwork. These are: + * 1.) CPO (Read Capture Delay) + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths and + * chip-specific internal delays. + * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay) + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths. + * Unless clock and DQ lanes are very different + * lengths (>2"), this should be set to the nominal value + * of 1/2 clock delay. + * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control) + * - DDR_SDRAM_CLK_CNTL register + * Source: Signal Integrity Simulations + * 4.) 2T Timing on Addr/Ctl + * - TIMING_CFG_2 register + * Source: Signal Integrity Simulations + * Usually only needed with heavy load/very high speed (>DDR2-800) + * + * ====== XPedite5370 DDR2-600 read delay calculations ====== + * + * See Freescale's App Note AN2583 as refrence. This document also + * contains the chip-specific delays for 8548E, 8572, etc. + * + * For MPC8572E + * Minimum chip delay (Ch 0): 1.372ns + * Maximum chip delay (Ch 0): 2.914ns + * Minimum chip delay (Ch 1): 1.220ns + * Maximum chip delay (Ch 1): 2.595ns + * + * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps + * + * Minimum delay calc (Ch 0): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps + * = 3808ps + * = 3.808ns + * + * Maximum delay calc (Ch 0): + * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly + * 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps + * = 6240ps + * = 6.240ns + * + * Minimum delay calc (Ch 1): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps + * = 3288ps + * = 3.288ns + * + * Maximum delay calc (Ch 1): + * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps + * = 5536ps + * = 5.536ns + * + * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target) + * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) + * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target) + * This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7) + * + * + * ====== XPedite5370 DDR2-800 read delay calculations ====== + * + * See Freescale's App Note AN2583 as refrence. This document also + * contains the chip-specific delays for 8548E, 8572, etc. + * + * For MPC8572E + * Minimum chip delay (Ch 0): 1.372ns + * Maximum chip delay (Ch 0): 2.914ns + * Minimum chip delay (Ch 1): 1.220ns + * Maximum chip delay (Ch 1): 2.595ns + * + * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps + * + * Minimum delay calc (Ch 0): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps + * = 3341ps + * = 3.341ns + * + * Maximum delay calc (Ch 0): + * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly + * 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps + * = 5673ps + * = 5.673ns + * + * Minimum delay calc (Ch 1): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps + * = 2822ps + * = 2.822ns + * + * Maximum delay calc (Ch 1): + * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps + * = 4968ps + * = 4.968ns + * + * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target) + * This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9) + * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target) + * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) + * + * Write latency (WR_DATA_DELAY) is calculated by doing the following: + * + * The DDR SDRAM specification requires DQS be received no sooner than + * 75% of an SDRAM clock period—and no later than 125% of a clock + * period—from the capturing clock edge of the command/address at the + * SDRAM. + * + * Based on the above tracelengths, the following are calculated: + * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns + * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns + * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns + * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns + * + * Difference in arrival time CLK vs. DQS: + * Ch. 0 0.072ns + * Ch. 1 0.138ns + * + * Both of these values are much less than 25% of the clock + * period at DDR2-600 or DDR2-800, so no additional delay is needed over + * the 1/2 cycle which normally aligns the first DQS transition + * exactly WL (CAS latency minus one cycle) after the CAS strobe. + * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's + * terminology corresponds to exactly one clock period delay after + * the CAS strobe. (due to the fact that the "delay" is referenced + * from the *falling* edge of the CLK, just after the rising edge + * which the CAS strobe is latched on. + */ + +typedef struct board_memctl_options { + uint16_t datarate_mhz_low; + uint16_t datarate_mhz_high; + uint8_t clk_adjust; + uint8_t cpo_override; + uint8_t write_data_delay; +} board_memctl_options_t; + +static struct board_memctl_options bopts_ctrl[][2] = { + { + /* Controller 0 */ + { + /* DDR2 600/667 */ + .datarate_mhz_low = 500, + .datarate_mhz_high = 750, + .clk_adjust = 5, + .cpo_override = 8, + .write_data_delay = 2, + }, + { + /* DDR2 800 */ + .datarate_mhz_low = 750, + .datarate_mhz_high = 850, + .clk_adjust = 5, + .cpo_override = 9, + .write_data_delay = 2, + }, + }, + { + /* Controller 1 */ + { + /* DDR2 600/667 */ + .datarate_mhz_low = 500, + .datarate_mhz_high = 750, + .clk_adjust = 5, + .cpo_override = 7, + .write_data_delay = 2, + }, + { + /* DDR2 800 */ + .datarate_mhz_low = 750, + .datarate_mhz_high = 850, + .clk_adjust = 5, + .cpo_override = 8, + .write_data_delay = 2, + }, + }, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + struct board_memctl_options *bopts = bopts_ctrl[ctrl_num]; + sys_info_t sysinfo; + int i; + unsigned int datarate; + + get_sys_info(&sysinfo); + datarate = sysinfo.freqDDRBus / 1000 / 1000; + + for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { + if ((bopts[i].datarate_mhz_low <= datarate) && + (bopts[i].datarate_mhz_high >= datarate)) { + debug("controller %d:\n", ctrl_num); + debug(" clk_adjust = %d\n", bopts[i].clk_adjust); + debug(" cpo = %d\n", bopts[i].cpo_override); + debug(" write_data_delay = %d\n", + bopts[i].write_data_delay); + popts->clk_adjust = bopts[i].clk_adjust; + popts->cpo_override = bopts[i].cpo_override; + popts->write_data_delay = bopts[i].write_data_delay; + } + } + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/xes/xpedite5370/law.c b/board/xes/xpedite5370/law.c new file mode 100644 index 000000000..daee676c4 --- /dev/null +++ b/board/xes/xpedite5370/law.c @@ -0,0 +1,54 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_PCIE1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), +#endif +#ifdef CONFIG_SYS_PCIE2_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2), +#endif +#ifdef CONFIG_SYS_PCIE3_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite5370/tlb.c b/board/xes/xpedite5370/tlb.c new file mode 100644 index 000000000..caafa3011 --- /dev/null +++ b/board/xes/xpedite5370/tlb.c @@ -0,0 +1,94 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* W**G* - NOR flashes */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* *I*G* - NAND flash */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1M, 1), + +#ifdef CONFIG_PCIE1 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), +#endif + +#ifdef CONFIG_PCIE2 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), +#endif + +#ifdef CONFIG_PCIE3 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), +#endif + +#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3) + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_64M, 1), +#endif + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/xes/xpedite5370/u-boot.lds b/board/xes/xpedite5370/u-boot.lds new file mode 100644 index 000000000..cb399120d --- /dev/null +++ b/board/xes/xpedite5370/u-boot.lds @@ -0,0 +1,145 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } :text = 0xffff + + . = ADDR(.text) + 0x80000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xes/xpedite5370/xpedite5370.c b/board/xes/xpedite5370/xpedite5370.c new file mode 100644 index 000000000..487509527 --- /dev/null +++ b/board/xes/xpedite5370/xpedite5370.c @@ -0,0 +1,128 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +extern void ft_board_pci_setup(void *blob, bd_t *bd); + +int checkboard(void) +{ + char *s; + + printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME); + printf(" "); + s = getenv("board_rev"); + if (s) + printf("Rev %s, ", s); + s = getenv("serial#"); + if (s) + printf("Serial# %s, ", s); + s = getenv("board_cfg"); + if (s) + printf("Cfg %s", s); + printf("\n"); + + return 0; +} + +static void flash_cs_fixup(void) +{ + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + int flash_sel; + + /* + * Print boot dev and swap flash flash chip selects if booted from 2nd + * flash. Swapping chip selects presents user with a common memory + * map regardless of which flash was booted from. + */ + flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS)); + printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); + + if (flash_sel) { + lbc->br0 = CONFIG_SYS_BR1_PRELIM; + lbc->or0 = CONFIG_SYS_OR1_PRELIM; + + lbc->br1 = CONFIG_SYS_BR0_PRELIM; + lbc->or1 = CONFIG_SYS_OR0_PRELIM; + } +} + +int board_early_init_r(void) +{ + /* Initialize PCA9557 devices */ + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + + /* + * Remap NOR flash region to caching-inhibited + * so that flash can be erased/programmed properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* Invalidate existing TLB entry for NOR flash */ + disable_tlb(0); + set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1); + + flash_cs_fixup(); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_PCI + ft_board_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); +} +#endif + +#ifdef CONFIG_MP +extern void cpu_mp_lmb_reserve(struct lmb *lmb); + +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h new file mode 100644 index 000000000..3bc0fe8f6 --- /dev/null +++ b/include/configs/XPEDITE5370.h @@ -0,0 +1,589 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * xpedite5370 board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8572 1 +#define CONFIG_XPEDITE5370 1 +#define CONFIG_SYS_BOARD_NAME "XPedite5370" +#define CONFIG_NUM_CPUS 2 /* 2 Cores */ +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ +#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */ + +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +/* + * DDR config + */ +#define CONFIG_FSL_DDR2 +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ +#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ +#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM + +#ifndef __ASSEMBLY__ +extern unsigned long get_board_sys_clk(unsigned long dummy); +extern unsigned long get_board_ddr_clk(unsigned long dummy); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) + +/* + * Diagnostics + */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x20000000 + +/* + * Memory map + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable + * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable + * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable + * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable + * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable + * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable + * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable + * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable + * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable + */ + +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) + +/* + * NAND flash configuration + */ +#define CONFIG_SYS_NAND_BASE 0xef800000 +#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ + +/* + * NOR flash configuration + */ +#define CONFIG_SYS_FLASH_BASE 0xf8000000 +#define CONFIG_SYS_FLASH_BASE2 0xf0000000 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ + {0xf7f40000, 0xc0000} } +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +/* + * Chip select configuration + */ +/* NOR Flash 0 on CS0 */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | \ + BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ + OR_GPCM_CSNT | \ + OR_GPCM_XACS | \ + OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_8 | \ + OR_GPCM_TRLX | \ + OR_GPCM_EHTR | \ + OR_GPCM_EAD) + +/* NOR Flash 1 on CS1 */ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ + BR_PS_16 | \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM + +/* NAND flash on CS2 */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ + (2< " + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE + +/* PEX8518 slave I2C interface */ +#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 + +/* I2C DS1631 temperature sensor */ +#define CONFIG_SYS_I2C_DS1621_ADDR 0x48 +#define CONFIG_DTT_DS1621 +#define CONFIG_DTT_SENSORS { 0 } + +/* I2C EEPROM - AT24C128B */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 + +/* GPIO/EEPROM/SRAM */ +#define CONFIG_DS4510 +#define CONFIG_SYS_I2C_DS4510_ADDR 0x51 + +/* GPIO */ +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 +#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c +#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e +#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f +#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 + +/* + * PU = pulled high, PD = pulled low + * I = input, O = output, IO = input/output + */ +/* PCA9557 @ 0x18*/ +#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ +#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ +#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ +#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ +#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ +#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ +#define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */ +#define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */ + +/* PCA9557 @ 0x1c*/ +#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ +#define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */ +#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ +#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ +#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ +#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ +#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ +#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ + +/* PCA9557 @ 0x1e*/ +#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */ +#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */ + +/* PCA9557 @ 0x1f */ +#define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */ +#define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */ +#define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */ +#define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */ +#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +/* PCIE1 - VPX P1 */ +#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ + +/* PCIE2 - PEX8518 */ +#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ + +/* + * Networking options + */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_TSEC_TBI +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_ETHPRIME "eTSEC2" + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC1_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define CONFIG_HAS_ETH0 + +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_PHY_ADDR 2 +#define TSEC2_PHYIDX 0 +#define CONFIG_HAS_ETH1 + +/* + * Command configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DS4510 +#define CONFIG_CMD_DS4510_INFO +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SNTP + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ +#define CONFIG_PANIC_HANG /* do not reset board on panic */ +#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 +#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ + +/* + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ +#define CONFIG_ENV_SIZE 0x8000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) + +/* + * Flash memory map: + * fff80000 - ffffffff Pri U-Boot (512 KB) + * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) + * fff00000 - fff3ffff Pri FDT (256KB) + * fef00000 - ffefffff Pri OS image (16MB) + * f8000000 - feefffff Pri OS Use/Filesystem (111MB) + * + * f7f80000 - f7ffffff Sec U-Boot (512 KB) + * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) + * f7f00000 - f7f3ffff Sec FDT (256KB) + * f6f00000 - f7efffff Sec OS image (16MB) + * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) + */ +#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000) +#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000) +#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000) +#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000) +#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000) +#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000) + +#define CONFIG_PROG_UBOOT1 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_UBOOT2 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_BOOT_OS_NET \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "if test -n $fdtaddr; then " \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "bootm $osaddr - $fdtaddr; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi; " \ + "else; " \ + "bootm $osaddr; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS1 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS2 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT1 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT2 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=yes\0" \ + "download_cmd=tftp\0" \ + "console_args=console=ttyS0,115200\0" \ + "root_args=root=/dev/nfs rw\0" \ + "misc_args=ip=on\0" \ + "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ + "bootfile=/home/user/file\0" \ + "osfile=/home/user/uImage-XPedite5370\0" \ + "fdtfile=/home/user/xpedite5370.dtb\0" \ + "ubootfile=/home/user/u-boot.bin\0" \ + "fdtaddr=c00000\0" \ + "osaddr=0x1000000\0" \ + "loadaddr=0x1000000\0" \ + "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ + "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ + "prog_os1="CONFIG_PROG_OS1"\0" \ + "prog_os2="CONFIG_PROG_OS2"\0" \ + "prog_fdt1="CONFIG_PROG_FDT1"\0" \ + "prog_fdt2="CONFIG_PROG_FDT2"\0" \ + "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ + "bootcmd_flash1=run set_bootargs; " \ + "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ + "bootcmd_flash2=run set_bootargs; " \ + "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ + "bootcmd=run bootcmd_flash1\0" +#endif /* __CONFIG_H */ From 487dcb4fb89be0992bc06ec1341090017bd9cf2f Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Wed, 29 Oct 2008 12:39:27 -0500 Subject: [PATCH 063/188] 85xx: Enable inbound PCI config cycles for X-ES boards Update X-ES Freescale boards to allow inbound PCI configuration cycles when configured as agent/endpoint. Signed-off-by: Peter Tyser --- board/xes/common/fsl_85xx_pci.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/board/xes/common/fsl_85xx_pci.c b/board/xes/common/fsl_85xx_pci.c index b8e363ec9..4b048814e 100644 --- a/board/xes/common/fsl_85xx_pci.c +++ b/board/xes/common/fsl_85xx_pci.c @@ -29,6 +29,7 @@ #include extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_config_unlock(struct pci_controller *hose); extern void fsl_pci_init(struct pci_controller *hose); int first_free_busno = 0; @@ -138,6 +139,10 @@ void pci_init_board(void) fsl_pci_init(hose); + /* Unlock inbound PCI configuration cycles */ + if (!host) + fsl_pci_config_unlock(hose); + first_free_busno = hose->last_busno+1; printf(" PCIE1 on bus %02x - %02x\n", hose->first_busno, hose->last_busno); @@ -187,6 +192,11 @@ void pci_init_board(void) (int)&pci->cfg_data); fsl_pci_init(hose); + + /* Unlock inbound PCI configuration cycles */ + if (!host) + fsl_pci_config_unlock(hose); + first_free_busno = hose->last_busno+1; printf(" PCIE2 on bus %02x - %02x\n", hose->first_busno, hose->last_busno); @@ -237,6 +247,11 @@ void pci_init_board(void) (int)&pci->cfg_data); fsl_pci_init(hose); + + /* Unlock inbound PCI configuration cycles */ + if (!host) + fsl_pci_config_unlock(hose); + first_free_busno = hose->last_busno+1; printf(" PCIE3 on bus %02x - %02x\n", hose->first_busno, hose->last_busno); From 78bbc5ce151c5a484bb51bf1866b4a993ffc16ec Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 1 Dec 2008 13:47:13 -0600 Subject: [PATCH 064/188] XPedite5200 board support Initial support for Extreme Engineering Solutions XPedite5200 - a MPC8548-based PMC single board computer. Signed-off-by: Peter Tyser --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/xes/common/Makefile | 3 +- board/xes/common/fsl_85xx_pci.c | 103 ++++++++++++++++++++++++++++++-- 5 files changed, 106 insertions(+), 5 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index be10eb49a..60def0c34 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -413,6 +413,7 @@ Rune Torgersen Peter Tyser + XPEDITE5200 MPC8548 XPEDITE5370 MPC8572 David Updegraff diff --git a/MAKEALL b/MAKEALL index a136bad7a..5ce3f3112 100755 --- a/MAKEALL +++ b/MAKEALL @@ -385,6 +385,7 @@ LIST_85xx=" \ TQM8548 \ TQM8555 \ TQM8560 \ + XPEDITE5200 \ XPEDITE5370 \ " diff --git a/Makefile b/Makefile index 752a37066..c532e5b14 100644 --- a/Makefile +++ b/Makefile @@ -2463,6 +2463,9 @@ TQM8560_config: unconfig echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; @$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc +XPEDITE5200_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5200 xes + XPEDITE5370_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5370 xes diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile index c5cd6331e..e7620f447 100644 --- a/board/xes/common/Makefile +++ b/board/xes/common/Makefile @@ -29,9 +29,10 @@ endif LIB = $(obj)lib$(VENDOR).a +COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o COBJS-$(CONFIG_MPC8572) += fsl_8572_clk.o COBJS-$(CONFIG_MPC85xx) += fsl_85xx_ddr.o -COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o +COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/xes/common/fsl_85xx_pci.c b/board/xes/common/fsl_85xx_pci.c index 4b048814e..56f344795 100644 --- a/board/xes/common/fsl_85xx_pci.c +++ b/board/xes/common/fsl_85xx_pci.c @@ -34,6 +34,9 @@ extern void fsl_pci_init(struct pci_controller *hose); int first_free_busno = 0; +#ifdef CONFIG_PCI1 +static struct pci_controller pci1_hose; +#endif #ifdef CONFIG_PCIE1 static struct pci_controller pcie1_hose; #endif @@ -44,6 +47,7 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif +#ifdef CONFIG_MPC8572 /* Correlate host/agent POR bits to usable info. Table 4-14 */ struct host_agent_cfg_t { uchar pcie_root[3]; @@ -81,6 +85,38 @@ struct io_port_cfg_t { {{0, 0, 0}, 4}, {{8, 0, 0}, 0}, }; +#elif defined CONFIG_MPC8548 +/* Correlate host/agent POR bits to usable info. Table 4-12 */ +struct host_agent_cfg_t { + uchar pci_host[2]; + uchar pcie_root[1]; + uchar rio_host; +} host_agent_cfg[8] = { + {{1, 1}, {0}, 0}, + {{1, 1}, {1}, 0}, + {{1, 1}, {0}, 1}, + {{0, 0}, {0}, 0}, /* reserved */ + {{0, 1}, {1}, 0}, + {{1, 1}, {1}, 0}, + {{0, 1}, {1}, 1}, + {{1, 1}, {1}, 1} +}; + +/* Correlate port width POR bits to usable info. Table 4-13 */ +struct io_port_cfg_t { + uchar pcie_width[1]; + uchar rio_width; +} io_port_cfg[8] = { + {{0}, 0}, + {{0}, 0}, + {{0}, 0}, + {{4}, 4}, + {{4}, 4}, + {{0}, 4}, + {{0}, 4}, + {{8}, 0}, +}; +#endif void pci_init_board(void) { @@ -94,9 +130,65 @@ void pci_init_board(void) uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; struct pci_region *r; - debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", - devdisr, io_sel, host_agent); +#ifdef CONFIG_PCI1 + uint pci_spd_norm = (gur->pordevsr & MPC85xx_PORDEVSR_PCI1_SPD); + uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + uint pcix = gur->pordevsr & MPC85xx_PORDEVSR_PCI1; + uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000; + width = 0; /* Silence compiler warning... */ + io_sel &= 0xf; /* Silence compiler warning... */ + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; + hose = &pci1_hose; + host = host_agent_cfg[host_agent].pci_host[0]; + r = hose->regions; + + + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n", + pci_32 ? 32 : 64, + pcix ? "PCIX" : "PCI", + pci_spd_norm ? ">=" : "<=", + pcix ? freq * 2 : freq, + host ? "host" : "agent", + pci_arb ? "arbiter" : "external-arbiter"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno = hose->last_busno+1; + printf(" PCI1 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + } else { + printf(" PCI1: disabled\n"); + } +#elif defined CONFIG_MPC8548 + /* PCI1 not present on MPC8572 */ + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ +#endif #ifdef CONFIG_PCIE1 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; hose = &pcie1_hose; @@ -143,7 +235,7 @@ void pci_init_board(void) if (!host) fsl_pci_config_unlock(hose); - first_free_busno = hose->last_busno+1; + first_free_busno = hose->last_busno + 1; printf(" PCIE1 on bus %02x - %02x\n", hose->first_busno, hose->last_busno); } @@ -200,7 +292,6 @@ void pci_init_board(void) first_free_busno = hose->last_busno+1; printf(" PCIE2 on bus %02x - %02x\n", hose->first_busno, hose->last_busno); - } #else gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ @@ -267,6 +358,10 @@ extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, void ft_board_pci_setup(void *blob, bd_t *bd) { + /* TODO - make node name (eg pci0) dynamic */ +#ifdef CONFIG_PCI1 + ft_fsl_pci_setup(blob, "pci0", &pci1_hose); +#endif #ifdef CONFIG_PCIE1 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); #endif From ecf5b98c7a6a2e2256dfddd48fab26678dcd6b90 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 16 Dec 2008 14:59:20 -0600 Subject: [PATCH 065/188] 85xx: Add support to populate addr map based on TLB settings Signed-off-by: Kumar Gala --- cpu/mpc85xx/tlb.c | 34 ++++++++++++++++++++++++++++++++++ include/asm-ppc/mmu.h | 3 +++ lib_ppc/board.c | 8 ++++++++ 3 files changed, 45 insertions(+) diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index a2d16ae2f..5b5f7914f 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -26,6 +26,11 @@ #include #include #include +#ifdef CONFIG_ADDR_MAP +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; void set_tlb(u8 tlb, u32 epn, u64 rpn, u8 perms, u8 wimge, @@ -47,6 +52,11 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn, mtspr(MAS7, _mas7); #endif asm volatile("isync;msync;tlbwe;isync"); + +#ifdef CONFIG_ADDR_MAP + if ((tlb == 1) && (gd->flags & GD_FLG_RELOC)) + addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel); +#endif } void disable_tlb(u8 esel) @@ -67,6 +77,11 @@ void disable_tlb(u8 esel) mtspr(MAS7, _mas7); #endif asm volatile("isync;msync;tlbwe;isync"); + +#ifdef CONFIG_ADDR_MAP + if (gd->flags & GD_FLG_RELOC) + addrmap_set_entry(0, 0, 0, esel); +#endif } void invalidate_tlb(u8 tlb) @@ -91,6 +106,25 @@ void init_tlbs(void) return ; } +#ifdef CONFIG_ADDR_MAP +void init_addr_map(void) +{ + int i; + + for (i = 0; i < num_tlb_entries; i++) { + if (tlb_table[i].tlb == 0) + continue; + + addrmap_set_entry(tlb_table[i].epn, + tlb_table[i].rpn, + (1UL << ((tlb_table[i].tsize * 2) + 10)), + tlb_table[i].esel); + } + + return ; +} +#endif + unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) { unsigned int tlb_size; diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 8975e6c90..6d942d083 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -431,6 +431,9 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn, extern void disable_tlb(u8 esel); extern void invalidate_tlb(u8 tlb); extern void init_tlbs(void); +#ifdef CONFIG_ADDR_MAP +extern void init_addr_map(void); +#endif extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 289a32a64..61c29b563 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -75,6 +75,10 @@ #include #endif +#ifdef CONFIG_ADDR_MAP +#include +#endif + #ifdef CONFIG_SYS_UPDATE_FLASH_SIZE extern int update_flash_size (int flash_size); #endif @@ -694,6 +698,10 @@ void board_init_r (gd_t *id, ulong dest_addr) */ trap_init (dest_addr); +#if defined(CONFIG_ADDR_MAP) && defined(CONFIG_E500) + init_addr_map(); +#endif + #if defined(CONFIG_BOARD_EARLY_INIT_R) board_early_init_r (); #endif From 77c8115b1f1871811633eae77a5a700fac1f0e50 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 16 Dec 2008 14:59:21 -0600 Subject: [PATCH 066/188] ppc: Use addrmap in virt_to_phys and map_physmem. If we have addr map support enabled use the mapping functions to implement virt_to_phys() and map_physmem(). Signed-off-by: Kumar Gala --- include/asm-ppc/io.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index 64cb746b1..4ddad26e8 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -10,6 +10,10 @@ #include #include +#ifdef CONFIG_ADDR_MAP +#include +#endif + #define SIO_CONFIG_RA 0x398 #define SIO_CONFIG_RD 0x399 @@ -287,7 +291,11 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val) static inline void * map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { +#ifdef CONFIG_ADDR_MAP + return (void *)(addrmap_phys_to_virt(paddr)); +#else return (void *)((unsigned long)paddr); +#endif } /* @@ -300,7 +308,11 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) static inline phys_addr_t virt_to_phys(void * vaddr) { +#ifdef CONFIG_ADDR_MAP + return addrmap_virt_to_phys(vaddr); +#else return (phys_addr_t)((unsigned long)vaddr); +#endif } #endif From 9d94aff699eed38b286814fcbb335f3eb8516a0e Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 16 Dec 2008 14:59:22 -0600 Subject: [PATCH 067/188] NAND FSL elbc: Use virt_to_phys to determine which bank is in use The current code that determines which bank/chipselect is used for a given NAND instance only worked for 32-bit addresses and assumed a 1:1 mapping. This breaks in 36-bit physical configs. The proper way to handle this is to use the virt_to_phys() and BR_PHYS_ADDR() routinues to match the 34-bit lbc bus address with the the virtual address the NAND code uses. Signed-off-by: Kumar Gala Acked-by: Scott Wood --- drivers/mtd/nand/fsl_elbc_nand.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 367c7d7fc..3f318e02e 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -718,7 +718,7 @@ static void fsl_elbc_ctrl_init(void) int board_nand_init(struct nand_chip *nand) { struct fsl_elbc_mtd *priv; - uint32_t br, or; + uint32_t br = 0, or = 0; if (!elbc_ctrl) { fsl_elbc_ctrl_init(); @@ -737,11 +737,13 @@ int board_nand_init(struct nand_chip *nand) * if we could pass more than one datum to the NAND driver... */ for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) { + phys_addr_t base_addr = virt_to_phys(nand->IO_ADDR_R); + br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br); or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or); if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM && - (br & or & BR_BA) == (phys_addr_t)nand->IO_ADDR_R) + (br & or & BR_BA) == BR_PHYS_ADDR(base_addr)) break; } From 58ec4866ed916c7e422f5107bb27b0822084728e Mon Sep 17 00:00:00 2001 From: Trent Piepho Date: Wed, 3 Dec 2008 15:16:38 -0800 Subject: [PATCH 068/188] mpc8[56]xx: Put localbus clock in device tree Export the localbus frequency in the device tree, the same way the CPU, TB, CCB, and various other frequencies are exported in their respective device tree nodes. Some localbus devices need this information to be programed correctly, so it makes sense to export it along with the other frequencies. Unfortunately, when someone wrote the localbus dts bindings, they didn't bother to define what the "compatible" property should be. So it seems no one was quite sure what to put in their dts files. Based on current existing dts files in the kernel source, I've used "fsl,pq3-localbus" and "fsl,elbc" for MPC85xx, which are used by almost all of the 85xx devices, and are looked for by the Linux code. The eLBC is apparently not entirely backward compatible with the pq3 LBC and so eLBC equipped platforms like 8572 won't use pq3-localbus. For MPC86xx, I've used "fsl,elbc" which is used by some of the 86xx systems and is also looked for by the Linux code. On MPC8641, I've also used "fsl,mpc8641-localbus" as it is also commonly used in dts files, some of which don't use "fsl,elbc" or any other acceptable name to match on. Signed-off-by: Trent Piepho Acked-by: Kumar Gala Acked-by: Jon Loeliger --- cpu/mpc85xx/fdt.c | 8 +++++++- cpu/mpc86xx/fdt.c | 9 +++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 59aafb1be..69fab9952 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -28,11 +28,12 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + extern void ft_qe_setup(void *blob); #ifdef CONFIG_MP #include "mp.h" -DECLARE_GLOBAL_DATA_PTR; void ft_fixup_cpu(void *blob, u64 memory_limit) { @@ -231,6 +232,11 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", bd->bi_intfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); + + do_fixup_by_compat_u32(blob, "fsl,pq3-localbus", + "bus-frequency", gd->lbc_clk, 1); + do_fixup_by_compat_u32(blob, "fsl,elbc", + "bus-frequency", gd->lbc_clk, 1); #ifdef CONFIG_QE ft_qe_setup(blob); #endif diff --git a/cpu/mpc86xx/fdt.c b/cpu/mpc86xx/fdt.c index 3adfad98c..e277040bb 100644 --- a/cpu/mpc86xx/fdt.c +++ b/cpu/mpc86xx/fdt.c @@ -13,6 +13,8 @@ DECLARE_GLOBAL_DATA_PTR; +DECLARE_GLOBAL_DATA_PTR; + void ft_cpu_setup(void *blob, bd_t *bd) { #if (CONFIG_NUM_CPUS > 1) @@ -29,6 +31,13 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); +#if defined(CONFIG_MPC8641) + do_fixup_by_compat_u32(blob, "fsl,mpc8641-localbus", + "bus-frequency", gd->lbc_clk, 1); +#endif + do_fixup_by_compat_u32(blob, "fsl,elbc", + "bus-frequency", gd->lbc_clk, 1); + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) \ From a5d212a263c58cc746481bf1fc878510533ce7d6 Mon Sep 17 00:00:00 2001 From: Trent Piepho Date: Wed, 3 Dec 2008 15:16:34 -0800 Subject: [PATCH 069/188] mpc8xxx: LCRR[CLKDIV] is sometimes five bits On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho Acked-by: Kumar Gala Acked-by: Jon Loeliger --- board/freescale/mpc8540ads/mpc8540ads.c | 2 +- board/freescale/mpc8541cds/mpc8541cds.c | 2 +- board/freescale/mpc8548cds/mpc8548cds.c | 2 +- board/freescale/mpc8555cds/mpc8555cds.c | 2 +- board/freescale/mpc8560ads/mpc8560ads.c | 2 +- board/freescale/mpc8568mds/mpc8568mds.c | 2 +- board/mpc8540eval/mpc8540eval.c | 2 +- board/pm854/pm854.c | 2 +- board/pm856/pm856.c | 2 +- board/sbc8548/sbc8548.c | 2 +- board/socrates/socrates.c | 2 +- board/tqc/tqm85xx/tqm85xx.c | 2 +- cpu/mpc85xx/cpu.c | 2 +- cpu/mpc86xx/cpu.c | 2 +- include/asm-ppc/fsl_lbc.h | 5 ++++- 15 files changed, 18 insertions(+), 15 deletions(-) diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index a0b6fbd12..9e3f67768 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -133,7 +133,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 7e40c5c80..e6025c8a5 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -308,7 +308,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index c562fc9d9..90e89bc71 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -125,7 +125,7 @@ local_bus_init(void) sys_info_t sysinfo; get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & 0x0f) * 2; + clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 33685c19f..53d5a936a 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -308,7 +308,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 37308189d..ac7778e25 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -337,7 +337,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index bc93be80f..7a23b338a 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -188,7 +188,7 @@ local_bus_init(void) sys_info_t sysinfo; get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & 0x0f) * 2; + clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index fa0a33686..bf270f4ce 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -101,7 +101,7 @@ phys_size_t initdram (int board_type) #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ get_sys_info(&sysinfo); /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */ - if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) { + if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) { lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000; } else { lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff; diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index fed0ed431..5353d738b 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -150,7 +150,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index 932f1121e..b14a3d34b 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -306,7 +306,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 8c073cb4b..519b0f749 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -126,7 +126,7 @@ local_bus_init(void) sys_info_t sysinfo; get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & 0x0f) * 2; + clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index d83dc7d6a..df9696e69 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -156,7 +156,7 @@ void local_bus_init (void) uint lcrr = CONFIG_SYS_LBC_LCRR; get_sys_info (&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv; /* Disable PLL bypass for Local Bus Clock >= 66 MHz */ diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 73f1d01bd..cda8208ee 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -361,7 +361,7 @@ uint get_lbc_clock (void) { volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); sys_info_t sys_info; - ulong clkdiv = lbc->lcrr & 0x0f; + ulong clkdiv = lbc->lcrr & LCRR_CLKDIV; get_sys_info (&sys_info); diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 943602f92..59a9ac8d9 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -174,7 +174,7 @@ int checkcpu (void) lcrr = lbc->lcrr; } #endif - clkdiv = lcrr & 0x0f; + clkdiv = lcrr & LCRR_CLKDIV; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \ defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536) diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 4cace984d..0ff76e3f7 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -110,7 +110,7 @@ checkcpu(void) lcrr = lbc->lcrr; } #endif - clkdiv = lcrr & 0x0f; + clkdiv = lcrr & LCRR_CLKDIV; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { printf("LBC:%4lu MHz\n", sysinfo.freqSystemBus / 1000000 / clkdiv); diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index 51fc5c13b..e492c62a8 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -300,7 +300,10 @@ #define LCRR_EADC_2 0x00020000 #define LCRR_EADC_3 0x00030000 #define LCRR_EADC_4 0x00000000 -#define LCRR_CLKDIV 0x0000000F +/* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit + * should always be zero on older parts that have a four bit CLKDIV. + */ +#define LCRR_CLKDIV 0x0000001F #define LCRR_CLKDIV_SHIFT 0 #define LCRR_CLKDIV_2 0x00000002 #define LCRR_CLKDIV_4 0x00000004 From 181a3650113883728927928b3ac81ad6dade4b2c Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Wed, 3 Dec 2008 10:08:19 -0500 Subject: [PATCH 070/188] Set IVPR to kenrel entry point in second core boot page Assuming the OSes exception vectors start from the base of kernel address, and the kernel physical starting address can be relocated to an non-zero address. This patch enables the second core to have a valid IVPR for debugger before kernel setting IVPR in CAMP mode. Otherwise, IVPR is 0x0 and it is not a valid value for second core which runs kernel at different physical address other than 0x0. Signed-off-by: Haiying Wang --- cpu/mpc85xx/release.S | 1 + 1 file changed, 1 insertion(+) diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 7c3e8a172..54c936c3e 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -157,6 +157,7 @@ __secondary_start_page: mfspr r0,SPRN_PIR stw r0,ENTRY_PIR(r10) + mtspr IVPR,r12 /* * Coming here, we know the cpu has one TLB mapping in TLB1[0] * which maps 0xfffff000-0xffffffff one-to-one. We set up a From bd93105fa171184a71ca8b22be03dc2705cfbd3f Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Thu, 11 Dec 2008 15:47:49 -0500 Subject: [PATCH 071/188] sbc8548: don't enable the 3rd and 4th eTSEC These interfaces don't have usable connectors on the board, so don't bother enumerating or configuring them. Signed-off-by: Paul Gortmaker --- include/configs/sbc8548.h | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 528c81090..254d91f95 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -399,25 +399,16 @@ #define CONFIG_TSEC1_NAME "eTSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "eTSEC1" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC2" -#define CONFIG_TSEC4 -#define CONFIG_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 -#define TSEC3_PHY_ADDR 2 -#define TSEC4_PHY_ADDR 3 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC4_PHYIDX 0 + #define TSEC1_FLAGS TSEC_GIGABIT #define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) /* Options are: eTSEC[0-3] */ #define CONFIG_ETHPRIME "eTSEC0" @@ -507,10 +498,6 @@ #define CONFIG_ETHADDR 02:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD -#define CONFIG_HAS_ETH3 -#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD #endif #define CONFIG_IPADDR 192.168.0.55 From ad22f9273c6f24fbfa917e867680e9688e0c59c5 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Thu, 11 Dec 2008 15:47:51 -0500 Subject: [PATCH 072/188] sbc8548: enable command line editing by default. Lets make things a bit more user friendly. It isn't 1985 anymore. Signed-off-by: Paul Gortmaker --- include/configs/sbc8548.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 254d91f95..8a7b0da4d 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -455,6 +455,7 @@ /* * Miscellaneous configurable options */ +#define CONFIG_CMDLINE_EDITING /* undef to save memory */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ From 58da8890d5fbd074746037722a423de9ac408616 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Thu, 11 Dec 2008 15:47:50 -0500 Subject: [PATCH 073/188] sbc8548: use proper PHY address The values given for the PHY address were wrong, so the code read no valid PHY ID, and fell through to the generic PHY support, which would work on 1000M but would not auto negotiate down to 100M or 10M. Signed-off-by: Paul Gortmaker --- include/configs/sbc8548.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 8a7b0da4d..8141a46dc 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -401,8 +401,8 @@ #define CONFIG_TSEC2_NAME "eTSEC1" #undef CONFIG_MPC85XX_FEC -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHY_ADDR 0x19 +#define TSEC2_PHY_ADDR 0x1a #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 From f51f07eb58fad12de9294ba4ee6c09a0ddeaee03 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Tue, 16 Dec 2008 12:09:27 +0800 Subject: [PATCH 074/188] 85xx: Fix the boot window issue If one custom board is using the 8MB flash, it is set as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000. The current start.S code will be broken at switch_as. It is because the TLB1[15] is set as 16MB page size, EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000. For the 8MB flash case, the EPN = 0xefxxxxxx, RPN = 0xffxxxxxx. Assume the virt address of switch_as is 0xef7ff18c, the real address of the instruction at switch_as should be 0xff7ff18c. the 0xff7ff18c is out of the range of the default 8MB boot LAW window 0xff800000 - 0xffffffff. So when we switch to AS1 address space at switch_as, the core can't fetch the instruction at switch_as any more. It will cause broken issue. Signed-off-by: Dave Liu --- cpu/mpc85xx/start.S | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 8fa0ff7a8..80f96773e 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -184,19 +184,19 @@ _start_e500: mtspr DBCR0,r0 #endif - /* create a temp mapping in AS=1 to the boot window */ + /* create a temp mapping in AS=1 to the 4M boot window */ lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l - lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@h - ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@l + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l - /* Align the mapping to 16MB */ - lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@h - ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@l + lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l - lis r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ + lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l mtspr MAS0,r6 mtspr MAS1,r7 From 446c381e3e16f19857b72ea0d06241267b8b9d58 Mon Sep 17 00:00:00 2001 From: Trent Piepho Date: Wed, 3 Dec 2008 15:16:35 -0800 Subject: [PATCH 075/188] mpc8568: Double local bus clock divider The clock divider for the MPC8568 local bus should be doubled, like the other newer MPC85xx chips. Since there are now more chips with a 2x divider than a 1x, and any new 85xx chips will probably be 2x, invert the sense of the #if so that it lists the 1x chips instead of the 2x ones. Signed-off-by: Trent Piepho Acked-by: Kumar Gala Acked-by: Jon Loeliger --- cpu/mpc85xx/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 59a9ac8d9..89800b884 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -176,8 +176,8 @@ int checkcpu (void) #endif clkdiv = lcrr & LCRR_CLKDIV; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { -#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \ - defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536) +#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ + !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) /* * Yes, the entire PQ38 family use the same * bit-representation for twice the clock divider values. From 9863d6aca11405e1e0d8aba2045d78aeec4d4ee7 Mon Sep 17 00:00:00 2001 From: Trent Piepho Date: Wed, 3 Dec 2008 15:16:36 -0800 Subject: [PATCH 076/188] mpc86xx: Double local bus clock divider The local bus clock divider should be doubled for both 8610 and 8641. Signed-off-by: Trent Piepho Acked-by: Kumar Gala Acked-by: Jon Loeliger --- cpu/mpc86xx/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 0ff76e3f7..a179fb3d0 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -112,6 +112,7 @@ checkcpu(void) #endif clkdiv = lcrr & LCRR_CLKDIV; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { + clkdiv *= 2; printf("LBC:%4lu MHz\n", sysinfo.freqSystemBus / 1000000 / clkdiv); } else { From ada591d2a0ecff5f9bc5ed1ebf310f439c3d0a28 Mon Sep 17 00:00:00 2001 From: Trent Piepho Date: Wed, 3 Dec 2008 15:16:37 -0800 Subject: [PATCH 077/188] mpc8[56]xx: Put localbus clock in sysinfo and gd Currently MPC85xx and MPC86xx boards just calculate the localbus frequency and print it out, but don't save it. This changes where its calculated and stored to be more consistent with the CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock. The localbus frequency is added to sysinfo and calculated when sysinfo is set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are. get_clocks() copies the frequency into the global data, as the other frequencies are, into a new field that is only enabled for MPC85xx and MPC86xx. checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency from sysinfo, like the other frequencies, instead of calculating it on the spot. Signed-off-by: Trent Piepho Acked-by: Kumar Gala Acked-by: Jon Loeliger --- cpu/mpc85xx/cpu.c | 31 +++++-------------------------- cpu/mpc85xx/speed.c | 27 +++++++++++++++++++++++++++ cpu/mpc86xx/cpu.c | 22 ++++------------------ cpu/mpc86xx/speed.c | 19 +++++++++++++++++++ include/asm-ppc/global_data.h | 3 +++ include/e500.h | 1 + include/mpc86xx.h | 1 + 7 files changed, 60 insertions(+), 44 deletions(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 89800b884..15ba7f1c5 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -77,8 +77,6 @@ struct cpu_type *identify_cpu(u32 ver) int checkcpu (void) { sys_info_t sysinfo; - uint lcrr; /* local bus clock ratio register */ - uint clkdiv; /* clock divider portion of lcrr */ uint pvr, svr; uint fam; uint ver; @@ -165,30 +163,11 @@ int checkcpu (void) break; } -#if defined(CONFIG_SYS_LBC_LCRR) - lcrr = CONFIG_SYS_LBC_LCRR; -#else - { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); - - lcrr = lbc->lcrr; - } -#endif - clkdiv = lcrr & LCRR_CLKDIV; - if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { -#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ - !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) - /* - * Yes, the entire PQ38 family use the same - * bit-representation for twice the clock divider values. - */ - clkdiv *= 2; -#endif - printf("LBC:%-4s MHz\n", - strmhz(buf1, sysinfo.freqSystemBus / clkdiv)); - } else { - printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr); - } + if (sysinfo.freqLocalBus > LCRR_CLKDIV) + printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); + else + printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", + sysinfo.freqLocalBus); #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 1e0f4838b..0d55228b6 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -28,6 +28,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -37,6 +38,7 @@ void get_sys_info (sys_info_t * sysInfo) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint plat_ratio,e500_ratio,half_freqSystemBus; + uint lcrr_div; plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; @@ -60,6 +62,30 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; } #endif + +#if defined(CONFIG_SYS_LBC_LCRR) + /* We will program LCRR to this value later */ + lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; +#else + { + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV; + } +#endif + if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { +#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ + !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) + /* + * Yes, the entire PQ38 family use the same + * bit-representation for twice the clock divider values. + */ + lcrr_div *= 2; +#endif + sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div; + } else { + /* In case anyone cares what the unknown value is */ + sysInfo->freqLocalBus = lcrr_div; + } } @@ -82,6 +108,7 @@ int get_clocks (void) gd->cpu_clk = sys_info.freqProcessor; gd->bus_clk = sys_info.freqSystemBus; gd->mem_clk = sys_info.freqDDRBus; + gd->lbc_clk = sys_info.freqLocalBus; /* * The base clock for I2C depends on the actual SOC. Unfortunately, diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index a179fb3d0..35680238d 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -39,8 +39,6 @@ checkcpu(void) uint pvr, svr; uint ver; uint major, minor; - uint lcrr; /* local bus clock ratio register */ - uint clkdiv; /* clock divider portion of lcrr */ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; @@ -100,23 +98,11 @@ checkcpu(void) printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); -#if defined(CONFIG_SYS_LBC_LCRR) - lcrr = CONFIG_SYS_LBC_LCRR; -#else - { - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile ccsr_lbc_t *lbc = &immap->im_lbc; - - lcrr = lbc->lcrr; - } -#endif - clkdiv = lcrr & LCRR_CLKDIV; - if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { - clkdiv *= 2; - printf("LBC:%4lu MHz\n", - sysinfo.freqSystemBus / 1000000 / clkdiv); + if (sysinfo.freqLocalBus > LCRR_CLKDIV) { + printf("LBC:%4lu MHz\n", sysinfo.freqLocalBus / 1000000); } else { - printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr); + printf("LBC: unknown (LCRR[CLKDIV] = 0x%02x)\n", + sysinfo.freqLocalBus); } puts(" L2: "); diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index 415ac9db8..64a3479d7 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -28,6 +28,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -39,6 +40,7 @@ void get_sys_info(sys_info_t *sysInfo) volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; uint plat_ratio, e600_ratio; + uint lcrr_div; plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; @@ -90,6 +92,22 @@ void get_sys_info(sys_info_t *sysInfo) sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus; break; } + +#if defined(CONFIG_SYS_LBC_LCRR) + /* We will program LCRR to this value later */ + lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; +#else + { + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV; + } +#endif + if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { + sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2); + } else { + /* In case anyone cares what the unknown value is */ + sysInfo->freqLocalBus = lcrr_div; + } } @@ -105,6 +123,7 @@ int get_clocks(void) get_sys_info(&sys_info); gd->cpu_clk = sys_info.freqProcessor; gd->bus_clk = sys_info.freqSystemBus; + gd->lbc_clk = sys_info.freqLocalBus; /* * The base clock for I2C depends on the actual SOC. Unfortunately, diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index aade097fa..2bb50b47f 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -89,6 +89,9 @@ typedef struct global_data { #if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8536) u32 sdhc_clk; #endif +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) + u32 lbc_clk; +#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */ #if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) u32 i2c1_clk; u32 i2c2_clk; diff --git a/include/e500.h b/include/e500.h index 1971eee29..9d3c8417c 100644 --- a/include/e500.h +++ b/include/e500.h @@ -13,6 +13,7 @@ typedef struct unsigned long freqProcessor; unsigned long freqSystemBus; unsigned long freqDDRBus; + unsigned long freqLocalBus; } MPC85xx_SYS_INFO; #endif /* _ASMLANGUAGE */ diff --git a/include/mpc86xx.h b/include/mpc86xx.h index f119d5bb1..a6fdea352 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -84,6 +84,7 @@ typedef struct { unsigned long freqProcessor; unsigned long freqSystemBus; + unsigned long freqLocalBus; } MPC86xx_SYS_INFO; #define l1icache_enable icache_enable From fea91edee8ae0295e3c30b1ff544df51f4d668e1 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 2 Dec 2008 21:58:04 +0100 Subject: [PATCH 078/188] usb_kbd: fix usb_kbd_deregister when DEVICE_DEREGISTER not enable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Remy Böhmer --- common/usb_kbd.c | 4 ++++ include/devices.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/common/usb_kbd.c b/common/usb_kbd.c index cf1456095..89e6ee7e5 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -211,7 +211,11 @@ int drv_usb_kbd_init(void) /* deregistering the keyboard */ int usb_kbd_deregister(void) { +#ifdef CONFIG_SYS_DEVICE_DEREGISTER return device_deregister(DEVNAME); +#else + return 1; +#endif } /************************************************************************** diff --git a/include/devices.h b/include/devices.h index 6b78d5888..20ddfc434 100644 --- a/include/devices.h +++ b/include/devices.h @@ -91,7 +91,9 @@ extern char *stdio_names[MAX_FILES]; */ int device_register (device_t * dev); int devices_init (void); +#ifdef CONFIG_SYS_DEVICE_DEREGISTER int device_deregister(char *devname); +#endif struct list_head* device_get_list(void); device_t* device_get_by_name(char* name); device_t* device_clone(device_t *dev); From 1f03cbfae221b24ba1341a0a3f62ff01c5c874df Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Tue, 23 Dec 2008 16:32:00 -0600 Subject: [PATCH 079/188] XPedite5200 board support cleanup Signed-off-by: Peter Tyser --- board/xes/common/actl_nand.c | 65 ++++ board/xes/common/fsl_85xx_pci.c | 6 +- board/xes/xpedite5200/Makefile | 55 +++ board/xes/xpedite5200/config.mk | 34 ++ board/xes/xpedite5200/ddr.c | 91 +++++ board/xes/xpedite5200/law.c | 51 +++ board/xes/xpedite5200/tlb.c | 85 +++++ board/xes/xpedite5200/u-boot.lds | 145 ++++++++ board/xes/xpedite5200/xpedite5200.c | 125 +++++++ include/configs/XPEDITE5200.h | 546 ++++++++++++++++++++++++++++ 10 files changed, 1200 insertions(+), 3 deletions(-) create mode 100644 board/xes/common/actl_nand.c create mode 100644 board/xes/xpedite5200/Makefile create mode 100644 board/xes/xpedite5200/config.mk create mode 100644 board/xes/xpedite5200/ddr.c create mode 100644 board/xes/xpedite5200/law.c create mode 100644 board/xes/xpedite5200/tlb.c create mode 100644 board/xes/xpedite5200/u-boot.lds create mode 100644 board/xes/xpedite5200/xpedite5200.c create mode 100644 include/configs/XPEDITE5200.h diff --git a/board/xes/common/actl_nand.c b/board/xes/common/actl_nand.c new file mode 100644 index 000000000..465aeb099 --- /dev/null +++ b/board/xes/common/actl_nand.c @@ -0,0 +1,65 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * This driver support NAND devices which have address lines + * connected as ALE and CLE inputs. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Hardware specific access to control-lines + */ +static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W; + + if (ctrl & NAND_CTRL_CHANGE) { + IO_ADDR_W = (ulong)this->IO_ADDR_W; + + IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE | + CONFIG_SYS_NAND_ACTL_ALE | + CONFIG_SYS_NAND_ACTL_NCE); + if (ctrl & NAND_CLE) + IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE; + if (ctrl & NAND_NCE) + IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE; + + this->IO_ADDR_W = (void *)IO_ADDR_W; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = nand_addr_hwcontrol; + nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY; + + return 0; +} diff --git a/board/xes/common/fsl_85xx_pci.c b/board/xes/common/fsl_85xx_pci.c index 56f344795..cd65a7341 100644 --- a/board/xes/common/fsl_85xx_pci.c +++ b/board/xes/common/fsl_85xx_pci.c @@ -179,7 +179,7 @@ void pci_init_board(void) fsl_pci_init(hose); - first_free_busno = hose->last_busno+1; + first_free_busno = hose->last_busno + 1; printf(" PCI1 on bus %02x - %02x\n", hose->first_busno, hose->last_busno); } else { @@ -289,7 +289,7 @@ void pci_init_board(void) if (!host) fsl_pci_config_unlock(hose); - first_free_busno = hose->last_busno+1; + first_free_busno = hose->last_busno + 1; printf(" PCIE2 on bus %02x - %02x\n", hose->first_busno, hose->last_busno); } @@ -343,7 +343,7 @@ void pci_init_board(void) if (!host) fsl_pci_config_unlock(hose); - first_free_busno = hose->last_busno+1; + first_free_busno = hose->last_busno + 1; printf(" PCIE3 on bus %02x - %02x\n", hose->first_busno, hose->last_busno); } diff --git a/board/xes/xpedite5200/Makefile b/board/xes/xpedite5200/Makefile new file mode 100644 index 000000000..02fe8fcd2 --- /dev/null +++ b/board/xes/xpedite5200/Makefile @@ -0,0 +1,55 @@ +# +# Copyright 2008 Extreme Engineering Solutions, Inc. +# Copyright 2004 Freescale Semiconductor. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xes/xpedite5200/config.mk b/board/xes/xpedite5200/config.mk new file mode 100644 index 000000000..be5a5c32c --- /dev/null +++ b/board/xes/xpedite5200/config.mk @@ -0,0 +1,34 @@ +# +# Copyright 2008 Extreme Engineering Solutions, Inc. +# Copyright 2004, 2007 Freescale Semiconductor. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# xpedite5200 board +# +ifndef TEXT_BASE +TEXT_BASE = 0xfff80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1 +PLATFORM_CPPFLAGS += -mrelocatable diff --git a/board/xes/xpedite5200/ddr.c b/board/xes/xpedite5200/ddr.c new file mode 100644 index 000000000..c5616d546 --- /dev/null +++ b/board/xes/xpedite5200/ddr.c @@ -0,0 +1,91 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +static void +get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); + + /* We use soldered memory, but use an SPD EEPROM to describe it. + * The SPD has an unspecified dimm type, but the DDR2 initialization + * code requires a specific type to be specified. This sets the type + * as a standard unregistered SO-DIMM. */ + if (spd->dimm_type == 0) { + spd->dimm_type = 0x4; + ((uchar *)spd)[63] += 0x4; + } +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + + if (ctrl_num) { + printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) + get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 7; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 9; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/xes/xpedite5200/law.c b/board/xes/xpedite5200/law.c new file mode 100644 index 000000000..386f9c587 --- /dev/null +++ b/board/xes/xpedite5200/law.c @@ -0,0 +1,51 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ + SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#if CONFIG_SYS_PCI1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_8M, LAW_TRGT_IF_PCI_1), +#endif +#if CONFIG_SYS_PCI2_MEM_PHYS + SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite5200/tlb.c b/board/xes/xpedite5200/tlb.c new file mode 100644 index 000000000..bd7bff820 --- /dev/null +++ b/board/xes/xpedite5200/tlb.c @@ -0,0 +1,85 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* W**G* - NOR flashes */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* *I*G* - NAND flash */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1M, 1), + +#if CONFIG_PCI1 + /* *I*G* - PCI MEM */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), +#endif + +#if CONFIG_PCI2 + /* *I*G* - PCI MEM */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), +#endif + +#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2) + /* *I*G* - PCI IO */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_16M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/xes/xpedite5200/u-boot.lds b/board/xes/xpedite5200/u-boot.lds new file mode 100644 index 000000000..bd952d20f --- /dev/null +++ b/board/xes/xpedite5200/u-boot.lds @@ -0,0 +1,145 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2004, 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } :text = 0xffff + + . = ADDR(.text) + 0x80000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xes/xpedite5200/xpedite5200.c b/board/xes/xpedite5200/xpedite5200.c new file mode 100644 index 000000000..e266d1dd8 --- /dev/null +++ b/board/xes/xpedite5200/xpedite5200.c @@ -0,0 +1,125 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2004, 2007 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern void ft_board_pci_setup(void *blob, bd_t *bd); + +int checkboard(void) +{ + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + + char *s; + + printf("Board: X-ES %s PMC\n", CONFIG_SYS_BOARD_NAME); + printf(" "); + s = getenv("board_rev"); + if (s) + printf("Rev %s, ", s); + s = getenv("serial#"); + if (s) + printf("Serial# %s, ", s); + s = getenv("board_cfg"); + if (s) + printf("Cfg %s", s); + printf("\n"); + + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ + ecm->eedr = 0xffffffff; /* Clear ecm errors */ + ecm->eeer = 0xffffffff; /* Enable ecm errors */ + + return 0; +} + +static void flash_cs_fixup(void) +{ + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + int flash_sel; + + /* + * Print boot dev and swap flash flash chip selects if booted from 2nd + * flash. Swapping chip selects presents user with a common memory + * map regardless of which flash was booted from. + */ + flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + CONFIG_SYS_PCA953X_FLASH_PASS_CS)); + printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); + + if (flash_sel) { + lbc->br0 = CONFIG_SYS_BR1_PRELIM; + lbc->or0 = CONFIG_SYS_OR1_PRELIM; + + lbc->br1 = CONFIG_SYS_BR0_PRELIM; + lbc->or1 = CONFIG_SYS_OR0_PRELIM; + } +} + +int board_early_init_r(void) +{ + /* Initialize PCA9557 devices */ + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); + + /* + * Remap NOR flash region to caching-inhibited + * so that flash can be erased/programmed properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* Invalidate existing TLB entry for NOR flash */ + disable_tlb(0); + set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1); + + flash_cs_fixup(); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_PCI + ft_board_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); +} +#endif diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h new file mode 100644 index 000000000..1df6855cc --- /dev/null +++ b/include/configs/XPEDITE5200.h @@ -0,0 +1,546 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2004-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * xpedite5200 board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8548 1 +#define CONFIG_XPEDITE5200 1 +#define CONFIG_SYS_BOARD_NAME "XPedite5200" +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ +#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */ + +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCI1 1 /* PCI controller 1 */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +/* + * DDR config + */ +#define CONFIG_FSL_DDR2 +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS 0x54 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM + +#define CONFIG_SYS_CLK_FREQ 66666666 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) + +/* + * Diagnostics + */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x20000000 + +/* + * Memory map + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable + * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable + * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable + * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable + * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable + * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable + * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable + */ + +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) + +/* + * NAND flash configuration + */ +#define CONFIG_SYS_NAND_BASE 0xef800000 +#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_NAND_ACTL +#define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */ +#define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */ +#define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */ +#define CONFIG_SYS_NAND_ACTL_DELAY 25 + +/* + * NOR flash configuration + */ +#define CONFIG_SYS_FLASH_BASE 0xfc000000 +#define CONFIG_SYS_FLASH_BASE2 0xf8000000 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ + {0xfbf40000, 0xc0000} } +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +/* + * Chip select configuration + */ +/* NOR Flash 0 on CS0 */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | \ + BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_8) + +/* NOR Flash 1 on CS1 */ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ + BR_PS_16 | \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM + +/* NAND flash on CS2 */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ + BR_PS_8 | \ + BR_V) + +/* NAND flash on CS2 */ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ + OR_GPCM_BCTLD | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_4 | \ + OR_GPCM_TRLX | \ + OR_GPCM_EHTR) + +/* NAND flash on CS3 */ +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ + BR_PS_8 | \ + BR_V) +#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM + +/* + * Use L1 as initial stack + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 +#define CONFIG_SYS_INIT_RAM_END 0x4000 + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} +#define CONFIG_BAUDRATE 115200 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE + +/* I2C EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 + +/* GPIO */ +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 +#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19 +#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 + +/* PCA957 @ 0x18 */ +#define CONFIG_SYS_PCA953X_BRD_CFG0 0x01 +#define CONFIG_SYS_PCA953X_BRD_CFG1 0x02 +#define CONFIG_SYS_PCA953X_BRD_CFG2 0x04 +#define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08 +#define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10 +#define CONFIG_SYS_PCA953X_FLASH_WP 0x20 +#define CONFIG_SYS_PCA953X_MONARCH 0x40 +#define CONFIG_SYS_PCA953X_EREADY 0x80 + +/* PCA957 @ 0x19 */ +#define CONFIG_SYS_PCA953X_P14_IO0 0x01 +#define CONFIG_SYS_PCA953X_P14_IO1 0x02 +#define CONFIG_SYS_PCA953X_P14_IO2 0x04 +#define CONFIG_SYS_PCA953X_P14_IO3 0x08 +#define CONFIG_SYS_PCA953X_P14_IO4 0x10 +#define CONFIG_SYS_PCA953X_P14_IO5 0x20 +#define CONFIG_SYS_PCA953X_P14_IO6 0x40 +#define CONFIG_SYS_PCA953X_P14_IO7 0x80 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */ + +/* + * Networking options + */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC1_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define CONFIG_HAS_ETH0 + +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC2_PHY_ADDR 2 +#define TSEC2_PHYIDX 0 +#define CONFIG_HAS_ETH1 + +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" +#define TSEC3_FLAGS TSEC_GIGABIT +#define TSEC3_PHY_ADDR 3 +#define TSEC3_PHYIDX 0 +#define CONFIG_HAS_ETH2 + +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "eTSEC4" +#define TSEC4_FLAGS TSEC_GIGABIT +#define TSEC4_PHY_ADDR 4 +#define TSEC4_PHYIDX 0 +#define CONFIG_HAS_ETH3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY + +/* + * Command configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SNTP + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ +#define CONFIG_PANIC_HANG /* do not reset board on panic */ +#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 +#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ + +/* + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ +#define CONFIG_ENV_SIZE 0x8000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) + +/* + * Flash memory map: + * fff80000 - ffffffff Pri U-Boot (512 KB) + * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) + * fff00000 - fff3ffff Pri FDT (256KB) + * fef00000 - ffefffff Pri OS image (16MB) + * fc000000 - feefffff Pri OS Use/Filesystem (47MB) + * + * fbf80000 - fbffffff Sec U-Boot (512 KB) + * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB) + * fbf00000 - fbf3ffff Sec FDT (256KB) + * faf00000 - fbefffff Sec OS image (16MB) + * f8000000 - faefffff Sec OS Use/Filesystem (47MB) + */ +#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000) +#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xfbf80000) +#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000) +#define CONFIG_FDT2_ENV_ADDR MK_STR(0xfbf00000) +#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000) +#define CONFIG_OS2_ENV_ADDR MK_STR(0xfaf00000) + +#define CONFIG_PROG_UBOOT1 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_UBOOT2 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_BOOT_OS_NET \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "if test -n $fdtaddr; then " \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "bootm $osaddr - $fdtaddr; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi; " \ + "else; " \ + "bootm $osaddr; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS1 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS2 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT1 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT2 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=yes\0" \ + "download_cmd=tftp\0" \ + "console_args=console=ttyS0,115200\0" \ + "root_args=root=/dev/nfs rw\0" \ + "misc_args=ip=on\0" \ + "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ + "bootfile=/home/user/file\0" \ + "osfile=/home/user/uImage-XPedite5200\0" \ + "fdtfile=/home/user/xpedite5200.dtb\0" \ + "ubootfile=/home/user/u-boot.bin\0" \ + "fdtaddr=c00000\0" \ + "osaddr=0x1000000\0" \ + "loadaddr=0x1000000\0" \ + "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ + "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ + "prog_os1="CONFIG_PROG_OS1"\0" \ + "prog_os2="CONFIG_PROG_OS2"\0" \ + "prog_fdt1="CONFIG_PROG_FDT1"\0" \ + "prog_fdt2="CONFIG_PROG_FDT2"\0" \ + "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ + "bootcmd_flash1=run set_bootargs; " \ + "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ + "bootcmd_flash2=run set_bootargs; " \ + "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ + "bootcmd=run bootcmd_flash1\0" +#endif /* __CONFIG_H */ From d9011f9b75561a0bd9254934c2bb2bc799d4f645 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Tue, 23 Dec 2008 16:32:01 -0600 Subject: [PATCH 080/188] 85xx: Enable inbound PCI config cycles for X-ES boards cleanup Signed-off-by: Peter Tyser --- board/xes/common/fsl_85xx_pci.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/xes/common/fsl_85xx_pci.c b/board/xes/common/fsl_85xx_pci.c index cd65a7341..9673a02b5 100644 --- a/board/xes/common/fsl_85xx_pci.c +++ b/board/xes/common/fsl_85xx_pci.c @@ -179,6 +179,10 @@ void pci_init_board(void) fsl_pci_init(hose); + /* Unlock inbound PCI configuration cycles */ + if (!host) + fsl_pci_config_unlock(hose); + first_free_busno = hose->last_busno + 1; printf(" PCI1 on bus %02x - %02x\n", hose->first_busno, hose->last_busno); From 0668236bafaa1c11c521652a2facebc74beecbf0 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 30 Dec 2008 22:56:11 +0100 Subject: [PATCH 081/188] README: update mailing list name and hits to patch submission. Signed-off-by: Wolfgang Denk --- README | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/README b/README index 2a553c274..3674ca105 100644 --- a/README +++ b/README @@ -3731,7 +3731,7 @@ MPC826x processors), on others (parts of) the data cache can be locked as (mis-) used as memory, etc. Chris Hallinan posted a good summary of these issues to the - u-boot-users mailing list: + U-Boot mailing list: Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)? From: "Chris Hallinan" @@ -3941,7 +3941,7 @@ int main (int argc, char *argv[]) Download latest U-Boot source; - Subscribe to u-boot-users mailing list; + Subscribe to u-boot mailing list; if (clueless) { email ("Hi, I am new to U-Boot, how do I get started?"); @@ -4018,10 +4018,11 @@ Since the number of patches for U-Boot is growing, we need to establish some rules. Submissions which do not conform to these rules may be rejected, even when they contain important and valuable stuff. -Patches shall be sent to the u-boot-users mailing list. - Please see http://www.denx.de/wiki/U-Boot/Patches for details. +Patches shall be sent to the u-boot mailing list ; +see http://lists.denx.de/mailman/listinfo/u-boot + When you send a patch, please include the following information with it: @@ -4084,7 +4085,7 @@ Notes: disabled must not need more memory than the old code without your modification. -* Remember that there is a size limit of 40 kB per message on the - u-boot-users mailing list. Bigger patches will be moderated. If - they are reasonable and not bigger than 100 kB, they will be - acknowledged. Even bigger patches should be avoided. +* Remember that there is a size limit of 100 kB per message on the + u-boot mailing list. Bigger patches will be moderated. If they are + reasonable and not too big, they will be acknowledged. But patches + bigger than the size limit should be avoided. From e12d9a8fb48d24176efffccc072b445e60a3afe4 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 3 Jan 2009 17:22:24 +0100 Subject: [PATCH 082/188] at91: Fix Atmel's at91sam9 boards out of tree build introduced in commit 89a7a87f084c Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Makefile b/Makefile index c532e5b14..0f8b52066 100644 --- a/Makefile +++ b/Makefile @@ -2602,6 +2602,7 @@ at91sam9260ek_nandflash_config \ at91sam9260ek_dataflash_cs0_config \ at91sam9260ek_dataflash_cs1_config \ at91sam9260ek_config : unconfig + @mkdir -p $(obj)include @if [ "$(findstring _nandflash,$@)" ] ; then \ echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ $(XECHO) "... with environment variable in NAND FLASH" ; \ @@ -2618,6 +2619,7 @@ at91sam9261ek_nandflash_config \ at91sam9261ek_dataflash_cs0_config \ at91sam9261ek_dataflash_cs3_config \ at91sam9261ek_config : unconfig + @mkdir -p $(obj)include @if [ "$(findstring _nandflash,$@)" ] ; then \ echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ $(XECHO) "... with environment variable in NAND FLASH" ; \ @@ -2634,6 +2636,7 @@ at91sam9263ek_nandflash_config \ at91sam9263ek_dataflash_config \ at91sam9263ek_dataflash_cs0_config \ at91sam9263ek_config : unconfig + @mkdir -p $(obj)include @if [ "$(findstring _nandflash,$@)" ] ; then \ echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ $(XECHO) "... with environment variable in NAND FLASH" ; \ @@ -2647,6 +2650,7 @@ at91sam9rlek_nandflash_config \ at91sam9rlek_dataflash_config \ at91sam9rlek_dataflash_cs0_config \ at91sam9rlek_config : unconfig + @mkdir -p $(obj)include @if [ "$(findstring _nandflash,$@)" ] ; then \ echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ $(XECHO) "... with environment variable in NAND FLASH" ; \ From 9ffd53db870a7da134f9a1ae76894a6b31237be5 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 6 Jan 2009 21:15:57 +0100 Subject: [PATCH 083/188] fix bmp_logo.h make dependencies to allow parallel build Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 0f8b52066..74b185461 100644 --- a/Makefile +++ b/Makefile @@ -348,7 +348,7 @@ $(obj)u-boot: depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(OBJS): depend $(obj)include/autoconf.mk $(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@)) -$(LIBS): depend $(obj)include/autoconf.mk +$(LIBS): depend $(obj)include/autoconf.mk $(SUBDIRS) $(MAKE) -C $(dir $(subst $(obj),,$@)) $(LIBBOARD): depend $(LIBS) $(obj)include/autoconf.mk From 4e170b16625291aa10d0d9abc3f34e8a5945d157 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Tue, 6 Jan 2009 21:13:14 +0100 Subject: [PATCH 084/188] at91: add at91sam9xeek board support At91sam9xe is basically an at91sam9260 with embedded flash. We can manage it as another entry for at91sam9260 in the Makefile. Check documentation at : http://www.atmel.com/dyn/products/product_card.asp?part_id=4263 Signed-off-by: Nicolas Ferre Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- Makefile | 17 +++++++++++++++++ doc/README.at91 | 2 +- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 74b185461..ecde92b4c 100644 --- a/Makefile +++ b/Makefile @@ -2615,6 +2615,23 @@ at91sam9260ek_config : unconfig fi; @$(MKCONFIG) -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91 +at91sam9xeek_nandflash_config \ +at91sam9xeek_dataflash_cs0_config \ +at91sam9xeek_dataflash_cs1_config \ +at91sam9xeek_config : unconfig + @mkdir -p $(obj)include + @if [ "$(findstring _nandflash,$@)" ] ; then \ + echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ + $(XECHO) "... with environment variable in NAND FLASH" ; \ + elif [ "$(findstring dataflash_cs0,$@)" ] ; then \ + echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1" >>$(obj)include/config.h ; \ + $(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \ + else \ + echo "#define CONFIG_SYS_USE_DATAFLASH_CS1 1" >>$(obj)include/config.h ; \ + $(XECHO) "... with environment variable in SPI DATAFLASH CS1" ; \ + fi; + @$(MKCONFIG) -n at91sam9xeek -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91sam9 + at91sam9261ek_nandflash_config \ at91sam9261ek_dataflash_cs0_config \ at91sam9261ek_dataflash_cs3_config \ diff --git a/doc/README.at91 b/doc/README.at91 index 838769a90..4e3928a47 100644 --- a/doc/README.at91 +++ b/doc/README.at91 @@ -3,7 +3,7 @@ Atmel AT91 Evaluation kits http://atmel.com/dyn/products/tools.asp?family_id=605#1443 ------------------------------------------------------------------------------ -AT91SAM9260EK +AT91SAM9260EK & AT91SAM9XEEK ------------------------------------------------------------------------------ Memory map From d481c80d78f954133c035dae6c7d22de3625795d Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 3 Jan 2009 17:22:25 +0100 Subject: [PATCH 085/188] at91rm9200: rename lowlevel init value to CONFIG_SYS_ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/m501sk/memsetup.S | 134 ++++++++++++------------- cpu/arm920t/at91rm9200/lowlevel_init.S | 88 ++++++++-------- include/configs/at91rm9200dk.h | 46 ++++----- include/configs/cmc_pu2.h | 46 ++++----- include/configs/csb637.h | 46 ++++----- include/configs/mp2usb.h | 46 ++++----- 6 files changed, 203 insertions(+), 203 deletions(-) diff --git a/board/m501sk/memsetup.S b/board/m501sk/memsetup.S index 6aea723f9..1a3ca4ba3 100644 --- a/board/m501sk/memsetup.S +++ b/board/m501sk/memsetup.S @@ -41,50 +41,50 @@ /* flash */ #define MC_PUIA 0xFFFFFF10 -#define MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 #define MC_PUP 0xFFFFFF50 -#define MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 #define MC_PUER 0xFFFFFF54 -#define MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 #define MC_ASR 0xFFFFFF04 -#define MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 #define MC_AASR 0xFFFFFF08 -#define MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 #define EBI_CFGR 0xFFFFFF64 -#define EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 #define SMC_CSR0 0xFFFFFF70 -#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ /* clocks */ #define PLLAR 0xFFFFFC28 -#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ #define PLLBR 0xFFFFFC2C -#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ #define MCKR 0xFFFFFC30 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ -#define MCKR_VAL 0x00000202 +#define CONFIG_SYS_MCKR_VAL 0x00000202 /* sdram */ #define PIOC_ASR 0xFFFFF870 -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */ #define PIOC_BSR 0xFFFFF874 -#define PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 #define PIOC_PDR 0xFFFFF804 -#define PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 #define EBI_CSA 0xFFFFFF60 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ #define SDRC_CR 0xFFFFFF98 -#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ #define SDRC_MR 0xFFFFFF90 -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define SDRC_TR 0xFFFFFF94 -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ _TEXT_BASE: .word TEXT_BASE @@ -130,71 +130,71 @@ lowlevelinit: SMRDATA: .word MC_PUIA - .word MC_PUIA_VAL + .word CONFIG_SYS_MC_PUIA_VAL .word MC_PUP - .word MC_PUP_VAL + .word CONFIG_SYS_MC_PUP_VAL .word MC_PUER - .word MC_PUER_VAL + .word CONFIG_SYS_MC_PUER_VAL .word MC_ASR - .word MC_ASR_VAL + .word CONFIG_SYS_MC_ASR_VAL .word MC_AASR - .word MC_AASR_VAL + .word CONFIG_SYS_MC_AASR_VAL .word EBI_CFGR - .word EBI_CFGR_VAL + .word CONFIG_SYS_EBI_CFGR_VAL .word SMC_CSR0 - .word SMC_CSR0_VAL + .word CONFIG_SYS_SMC_CSR0_VAL .word PLLAR - .word PLLAR_VAL + .word CONFIG_SYS_PLLAR_VAL .word PLLBR - .word PLLBR_VAL + .word CONFIG_SYS_PLLBR_VAL .word MCKR - .word MCKR_VAL + .word CONFIG_SYS_MCKR_VAL /* SMRDATA is 80 bytes long */ /* here there's a delay of 100 */ SMRDATA1: .word PIOC_ASR - .word PIOC_ASR_VAL + .word CONFIG_SYS_PIOC_ASR_VAL .word PIOC_BSR - .word PIOC_BSR_VAL + .word CONFIG_SYS_PIOC_BSR_VAL .word PIOC_PDR - .word PIOC_PDR_VAL + .word CONFIG_SYS_PIOC_PDR_VAL .word EBI_CSA - .word EBI_CSA_VAL + .word CONFIG_SYS_EBI_CSA_VAL .word SDRC_CR - .word SDRC_CR_VAL + .word CONFIG_SYS_SDRC_CR_VAL .word SDRC_MR - .word SDRC_MR_VAL - .word SDRAM - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_MR_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL .word SDRC_MR - .word SDRC_MR_VAL1 - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_MR_VAL1 + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL .word SDRC_MR - .word SDRC_MR_VAL2 - .word SDRAM1 - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_MR_VAL2 + .word CONFIG_SYS_SDRAM1 + .word CONFIG_SYS_SDRAM_VAL .word SDRC_TR - .word SDRC_TR_VAL - .word SDRAM - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_TR_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL .word SDRC_MR - .word SDRC_MR_VAL3 - .word SDRAM - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_MR_VAL3 + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL /* SMRDATA1 is 176 bytes long */ #endif /* CONFIG_BOOTBINFUNC */ diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S index 66b07da08..736f1ea4d 100644 --- a/cpu/arm920t/at91rm9200/lowlevel_init.S +++ b/cpu/arm920t/at91rm9200/lowlevel_init.S @@ -135,71 +135,71 @@ LoopOsc: SMRDATA: .word MC_PUIA - .word MC_PUIA_VAL + .word CONFIG_SYS_MC_PUIA_VAL .word MC_PUP - .word MC_PUP_VAL + .word CONFIG_SYS_MC_PUP_VAL .word MC_PUER - .word MC_PUER_VAL + .word CONFIG_SYS_MC_PUER_VAL .word MC_ASR - .word MC_ASR_VAL + .word CONFIG_SYS_MC_ASR_VAL .word MC_AASR - .word MC_AASR_VAL + .word CONFIG_SYS_MC_AASR_VAL .word EBI_CFGR - .word EBI_CFGR_VAL + .word CONFIG_SYS_EBI_CFGR_VAL .word SMC_CSR0 - .word SMC_CSR0_VAL + .word CONFIG_SYS_SMC_CSR0_VAL .word PLLAR - .word PLLAR_VAL + .word CONFIG_SYS_PLLAR_VAL .word PLLBR - .word PLLBR_VAL + .word CONFIG_SYS_PLLBR_VAL .word MCKR - .word MCKR_VAL + .word CONFIG_SYS_MCKR_VAL /* SMRDATA is 80 bytes long */ /* here there's a delay of 100 */ SMRDATA1: .word PIOC_ASR - .word PIOC_ASR_VAL + .word CONFIG_SYS_PIOC_ASR_VAL .word PIOC_BSR - .word PIOC_BSR_VAL + .word CONFIG_SYS_PIOC_BSR_VAL .word PIOC_PDR - .word PIOC_PDR_VAL + .word CONFIG_SYS_PIOC_PDR_VAL .word EBI_CSA - .word EBI_CSA_VAL + .word CONFIG_SYS_EBI_CSA_VAL .word SDRC_CR - .word SDRC_CR_VAL + .word CONFIG_SYS_SDRC_CR_VAL .word SDRC_MR - .word SDRC_MR_VAL - .word SDRAM - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_MR_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL .word SDRC_MR - .word SDRC_MR_VAL1 - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_MR_VAL1 + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL .word SDRC_MR - .word SDRC_MR_VAL2 - .word SDRAM1 - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_MR_VAL2 + .word CONFIG_SYS_SDRAM1 + .word CONFIG_SYS_SDRAM_VAL .word SDRC_TR - .word SDRC_TR_VAL - .word SDRAM - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_TR_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL .word SDRC_MR - .word SDRC_MR_VAL3 - .word SDRAM - .word SDRAM_VAL + .word CONFIG_SYS_SDRC_MR_VAL3 + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL /* SMRDATA1 is 176 bytes long */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index 746f0ef10..c7e83ccfc 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -45,33 +45,33 @@ #ifndef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ /* clocks */ -#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ -#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ /* sdram */ -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ #else #define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h index cdd308d8b..d9acb470f 100644 --- a/include/configs/cmc_pu2.h +++ b/include/configs/cmc_pu2.h @@ -44,33 +44,33 @@ #ifndef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */ +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */ /* clocks */ -#define PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */ -#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */ +#define CONFIG_SYS_PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */ /* sdram */ -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR_VAL 0x3399c1d4 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x3399c1d4 /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ #else #define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/include/configs/csb637.h b/include/configs/csb637.h index 682db447d..2df77cfa7 100644 --- a/include/configs/csb637.h +++ b/include/configs/csb637.h @@ -45,33 +45,33 @@ #ifndef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ /* clocks */ -#define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */ -#define PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */ -#define MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */ +#define CONFIG_SYS_PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */ +#define CONFIG_SYS_MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */ /* sdram */ -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR_VAL 0x21914159 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x21914159 /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ #else #define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h index cbbdb0c77..fb10616c3 100644 --- a/include/configs/mp2usb.h +++ b/include/configs/mp2usb.h @@ -49,33 +49,33 @@ #ifndef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */ +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */ /* clocks */ -#define PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */ -#define PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */ -#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */ +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */ +#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */ /* sdram */ -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR_VAL 0x3211295A /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000020 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x3211295A /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000020 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ #else #define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ From 8a48686fac2030287765f1970ea046bd5734b733 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 3 Jan 2009 17:22:26 +0100 Subject: [PATCH 086/188] m501sk: move to the common memory setup Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/m501sk/Makefile | 2 - board/m501sk/memsetup.S | 200 --------------------------------------- include/configs/m501sk.h | 33 +++++++ 3 files changed, 33 insertions(+), 202 deletions(-) delete mode 100644 board/m501sk/memsetup.S diff --git a/board/m501sk/Makefile b/board/m501sk/Makefile index c562c600a..aec3d1c7c 100644 --- a/board/m501sk/Makefile +++ b/board/m501sk/Makefile @@ -27,8 +27,6 @@ LIB = $(obj)lib$(BOARD).a COBJS := m501sk.o eeprom.o -SOBJS := memsetup.o - SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/m501sk/memsetup.S b/board/m501sk/memsetup.S deleted file mode 100644 index 1a3ca4ba3..000000000 --- a/board/m501sk/memsetup.S +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the at91rm9200dk board by - * (C) Copyright 2004 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#ifdef CONFIG_BOOTBINFUNC -/* - * some parameters for the board - * - * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in - * turn is based on the boot.bin code from ATMEL - * - */ - -/* flash */ -#define MC_PUIA 0xFFFFFF10 -#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 -#define MC_PUP 0xFFFFFF50 -#define CONFIG_SYS_MC_PUP_VAL 0x00000000 -#define MC_PUER 0xFFFFFF54 -#define CONFIG_SYS_MC_PUER_VAL 0x00000000 -#define MC_ASR 0xFFFFFF04 -#define CONFIG_SYS_MC_ASR_VAL 0x00000000 -#define MC_AASR 0xFFFFFF08 -#define CONFIG_SYS_MC_AASR_VAL 0x00000000 -#define EBI_CFGR 0xFFFFFF64 -#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0 0xFFFFFF70 -#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define PLLAR 0xFFFFFC28 -#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ -#define PLLBR 0xFFFFFC2C -#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -#define MCKR 0xFFFFFC30 -/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ -#define CONFIG_SYS_MCKR_VAL 0x00000202 - -/* sdram */ -#define PIOC_ASR 0xFFFFF870 -#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */ -#define PIOC_BSR 0xFFFFF874 -#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR 0xFFFFF804 -#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA 0xFFFFFF60 -#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ -#define SDRC_CR 0xFFFFFF98 -#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ -#define SDRC_MR 0xFFFFFF90 -#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ -#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR 0xFFFFFF94 -#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ - -_TEXT_BASE: - .word TEXT_BASE - -.globl lowlevelinit -lowlevelinit: - /* memory control configuration */ - /* this isn't very elegant, but what the heck */ - ldr r0, =SMRDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - add r2, r0, #80 -0: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 0b - /* delay - this is all done by guess */ - ldr r0, =0x00010000 -1: - subs r0, r0, #1 - bhi 1b - ldr r0, =SMRDATA1 - ldr r1, _TEXT_BASE - sub r0, r0, r1 - add r2, r0, #176 -2: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 2b - - /* everything is fine now */ - mov pc, lr - - .ltorg - -SMRDATA: - .word MC_PUIA - .word CONFIG_SYS_MC_PUIA_VAL - .word MC_PUP - .word CONFIG_SYS_MC_PUP_VAL - .word MC_PUER - .word CONFIG_SYS_MC_PUER_VAL - .word MC_ASR - .word CONFIG_SYS_MC_ASR_VAL - .word MC_AASR - .word CONFIG_SYS_MC_AASR_VAL - .word EBI_CFGR - .word CONFIG_SYS_EBI_CFGR_VAL - .word SMC_CSR0 - .word CONFIG_SYS_SMC_CSR0_VAL - .word PLLAR - .word CONFIG_SYS_PLLAR_VAL - .word PLLBR - .word CONFIG_SYS_PLLBR_VAL - .word MCKR - .word CONFIG_SYS_MCKR_VAL - /* SMRDATA is 80 bytes long */ - /* here there's a delay of 100 */ -SMRDATA1: - .word PIOC_ASR - .word CONFIG_SYS_PIOC_ASR_VAL - .word PIOC_BSR - .word CONFIG_SYS_PIOC_BSR_VAL - .word PIOC_PDR - .word CONFIG_SYS_PIOC_PDR_VAL - .word EBI_CSA - .word CONFIG_SYS_EBI_CSA_VAL - .word SDRC_CR - .word CONFIG_SYS_SDRC_CR_VAL - .word SDRC_MR - .word CONFIG_SYS_SDRC_MR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word SDRC_MR - .word CONFIG_SYS_SDRC_MR_VAL1 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word SDRC_MR - .word CONFIG_SYS_SDRC_MR_VAL2 - .word CONFIG_SYS_SDRAM1 - .word CONFIG_SYS_SDRAM_VAL - .word SDRC_TR - .word CONFIG_SYS_SDRC_TR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word SDRC_MR - .word CONFIG_SYS_SDRC_MR_VAL3 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - /* SMRDATA1 is 176 bytes long */ -#endif /* CONFIG_BOOTBINFUNC */ diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h index f09214dce..eab37df22 100644 --- a/include/configs/m501sk.h +++ b/include/configs/m501sk.h @@ -41,6 +41,39 @@ #define CONFIG_INITRD_TAG 1 #define CONFIG_MENUPROMPT "." +/* + * LowLevel Init + */ +#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 +/* flash */ +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ + +/* clocks */ +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ +#define CONFIG_SYS_MCKR_VAL 0x00000202 + +/* sdram */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ /* * Size of malloc() pool From 3dd9395a0d7ce69a335d0e743c04b9caedd681d3 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 6 Jan 2009 21:41:59 +0100 Subject: [PATCH 087/188] at91rm9200: move define from lowlevel_init to header Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm920t/at91rm9200/lowlevel_init.S | 70 ++++++-------------- include/asm-arm/arch-at91rm9200/AT91RM9200.h | 27 ++++++++ 2 files changed, 49 insertions(+), 48 deletions(-) diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S index 736f1ea4d..0913284e7 100644 --- a/cpu/arm920t/at91rm9200/lowlevel_init.S +++ b/cpu/arm920t/at91rm9200/lowlevel_init.S @@ -38,33 +38,7 @@ * turn is based on the boot.bin code from ATMEL * */ - -/* flash */ -#define MC_PUIA 0xFFFFFF10 -#define MC_PUP 0xFFFFFF50 -#define MC_PUER 0xFFFFFF54 -#define MC_ASR 0xFFFFFF04 -#define MC_AASR 0xFFFFFF08 -#define EBI_CFGR 0xFFFFFF64 -#define SMC_CSR0 0xFFFFFF70 - -/* clocks */ -#define PLLAR 0xFFFFFC28 -#define PLLBR 0xFFFFFC2C -#define MCKR 0xFFFFFC30 - -#define AT91C_BASE_CKGR 0xFFFFFC20 -#define CKGR_MOR 0 - -/* sdram */ -#define PIOC_ASR 0xFFFFF870 -#define PIOC_BSR 0xFFFFF874 -#define PIOC_PDR 0xFFFFF804 -#define EBI_CSA 0xFFFFFF60 -#define SDRC_CR 0xFFFFFF98 -#define SDRC_MR 0xFFFFFF90 -#define SDRC_TR 0xFFFFFF94 - +#include _MTEXT_BASE: #undef START_FROM_MEM @@ -84,7 +58,7 @@ lowlevel_init: #else ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */ #endif - str r0, [r1, #CKGR_MOR] + str r0, [r1, #AT91C_CKGR_MOR] /* Add loop to compensate Main Oscillator startup time */ ldr r0, =0x00000010 LoopOsc: @@ -134,44 +108,44 @@ LoopOsc: .ltorg SMRDATA: - .word MC_PUIA + .word AT91C_MC_PUIA .word CONFIG_SYS_MC_PUIA_VAL - .word MC_PUP + .word AT91C_MC_PUP .word CONFIG_SYS_MC_PUP_VAL - .word MC_PUER + .word AT91C_MC_PUER .word CONFIG_SYS_MC_PUER_VAL - .word MC_ASR + .word AT91C_MC_ASR .word CONFIG_SYS_MC_ASR_VAL - .word MC_AASR + .word AT91C_MC_AASR .word CONFIG_SYS_MC_AASR_VAL - .word EBI_CFGR + .word AT91C_EBI_CFGR .word CONFIG_SYS_EBI_CFGR_VAL - .word SMC_CSR0 + .word AT91C_SMC_CSR0 .word CONFIG_SYS_SMC_CSR0_VAL - .word PLLAR + .word AT91C_PLLAR .word CONFIG_SYS_PLLAR_VAL - .word PLLBR + .word AT91C_PLLBR .word CONFIG_SYS_PLLBR_VAL - .word MCKR + .word AT91C_MCKR .word CONFIG_SYS_MCKR_VAL /* SMRDATA is 80 bytes long */ /* here there's a delay of 100 */ SMRDATA1: - .word PIOC_ASR + .word AT91C_PIOC_ASR .word CONFIG_SYS_PIOC_ASR_VAL - .word PIOC_BSR + .word AT91C_PIOC_BSR .word CONFIG_SYS_PIOC_BSR_VAL - .word PIOC_PDR + .word AT91C_PIOC_PDR .word CONFIG_SYS_PIOC_PDR_VAL - .word EBI_CSA + .word AT91C_EBI_CSA .word CONFIG_SYS_EBI_CSA_VAL - .word SDRC_CR + .word AT91C_SDRC_CR .word CONFIG_SYS_SDRC_CR_VAL - .word SDRC_MR + .word AT91C_SDRC_MR .word CONFIG_SYS_SDRC_MR_VAL .word CONFIG_SYS_SDRAM .word CONFIG_SYS_SDRAM_VAL - .word SDRC_MR + .word AT91C_SDRC_MR .word CONFIG_SYS_SDRC_MR_VAL1 .word CONFIG_SYS_SDRAM .word CONFIG_SYS_SDRAM_VAL @@ -189,15 +163,15 @@ SMRDATA1: .word CONFIG_SYS_SDRAM_VAL .word CONFIG_SYS_SDRAM .word CONFIG_SYS_SDRAM_VAL - .word SDRC_MR + .word AT91C_SDRC_MR .word CONFIG_SYS_SDRC_MR_VAL2 .word CONFIG_SYS_SDRAM1 .word CONFIG_SYS_SDRAM_VAL - .word SDRC_TR + .word AT91C_SDRC_TR .word CONFIG_SYS_SDRC_TR_VAL .word CONFIG_SYS_SDRAM .word CONFIG_SYS_SDRAM_VAL - .word SDRC_MR + .word AT91C_SDRC_MR .word CONFIG_SYS_SDRC_MR_VAL3 .word CONFIG_SYS_SDRAM .word CONFIG_SYS_SDRAM_VAL diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h index 95db0177c..00bae1c4d 100644 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -781,5 +781,32 @@ typedef struct _AT91S_PDC #define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ #define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ +#else +/* flash */ +#define AT91C_MC_PUIA 0xFFFFFF10 +#define AT91C_MC_PUP 0xFFFFFF50 +#define AT91C_MC_PUER 0xFFFFFF54 +#define AT91C_MC_ASR 0xFFFFFF04 +#define AT91C_MC_AASR 0xFFFFFF08 +#define AT91C_EBI_CFGR 0xFFFFFF64 +#define AT91C_SMC_CSR0 0xFFFFFF70 + +/* clocks */ +#define AT91C_PLLAR 0xFFFFFC28 +#define AT91C_PLLBR 0xFFFFFC2C +#define AT91C_MCKR 0xFFFFFC30 + +#define AT91C_BASE_CKGR 0xFFFFFC20 +#define AT91C_CKGR_MOR 0 + +/* sdram */ +#define AT91C_PIOC_ASR 0xFFFFF870 +#define AT91C_PIOC_BSR 0xFFFFF874 +#define AT91C_PIOC_PDR 0xFFFFF804 +#define AT91C_EBI_CSA 0xFFFFFF60 +#define AT91C_SDRC_CR 0xFFFFFF98 +#define AT91C_SDRC_MR 0xFFFFFF90 +#define AT91C_SDRC_TR 0xFFFFFF94 + #endif /* __ASSEMBLY__ */ #endif /* AT91RM9200_H */ From 509fc553bc6087a6f705b3bf52f3950d7d1eaa58 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sat, 11 Oct 2008 20:45:44 -0400 Subject: [PATCH 088/188] Blackfin: set proper LDRFLAGS for parallel booting LDRs In order to boot an LDR out of parallel flash, the ldr utility needs a few flags to tell it to generate the right header. Signed-off-by: Mike Frysinger --- board/bf533-ezkit/config.mk | 6 ++++++ board/bf533-stamp/config.mk | 6 ++++++ board/bf537-stamp/config.mk | 5 ++++- board/bf561-ezkit/config.mk | 6 ++++++ 4 files changed, 22 insertions(+), 1 deletion(-) diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk index de80ffe7b..984792476 100644 --- a/board/bf533-ezkit/config.mk +++ b/board/bf533-ezkit/config.mk @@ -1,4 +1,6 @@ # +# Copyright (c) 2005-2008 Analog Device Inc. +# # (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -23,3 +25,7 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk index de80ffe7b..984792476 100644 --- a/board/bf533-stamp/config.mk +++ b/board/bf533-stamp/config.mk @@ -1,4 +1,6 @@ # +# Copyright (c) 2005-2008 Analog Device Inc. +# # (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -23,3 +25,7 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk index 1b87d53dd..d9e884e0e 100644 --- a/board/bf537-stamp/config.mk +++ b/board/bf537-stamp/config.mk @@ -1,4 +1,6 @@ # +# Copyright (c) 2005-2008 Analog Device Inc. +# # (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -25,5 +27,6 @@ #TEXT_BASE = do-not-use-me # Set some default LDR flags based on boot mode. -LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 +LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk index de80ffe7b..77c888b3b 100644 --- a/board/bf561-ezkit/config.mk +++ b/board/bf561-ezkit/config.mk @@ -1,4 +1,6 @@ # +# Copyright (c) 2005-2008 Analog Device Inc. +# # (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -23,3 +25,7 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) From b9eecc342f767b50e1476fbc1aad7d88dd4ce5eb Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 24 Oct 2008 17:48:54 -0400 Subject: [PATCH 089/188] Blackfin: fix linker scripts to work with --gc-sections Make sure all .text sections get pulled in and the entry point is properly referenced so they don't get discarded when linking with --gc-sections. Signed-off-by: Mike Frysinger --- board/bf533-ezkit/u-boot.lds.S | 23 +++++++++++++---------- board/bf533-stamp/u-boot.lds.S | 19 +++++++++++-------- board/bf537-stamp/u-boot.lds.S | 19 +++++++++++-------- board/bf561-ezkit/u-boot.lds.S | 23 +++++++++++++---------- 4 files changed, 48 insertions(+), 36 deletions(-) diff --git a/board/bf533-ezkit/u-boot.lds.S b/board/bf533-ezkit/u-boot.lds.S index 70764acf1..da16726d8 100644 --- a/board/bf533-ezkit/u-boot.lds.S +++ b/board/bf533-ezkit/u-boot.lds.S @@ -28,6 +28,8 @@ #include #include #undef ALIGN +#undef ENTRY +#undef bfin /* If we don't actually load anything into L1 data, this will avoid * a syntax error. If we do actually load something into L1 data, @@ -50,11 +52,12 @@ MEMORY l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE } +ENTRY(_start) SECTIONS { .text : { - cpu/blackfin/start.o (.text) + cpu/blackfin/start.o (.text .text.*) #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within @@ -63,20 +66,20 @@ SECTIONS * it linked after the configuration sector. */ - cpu/blackfin/traps.o (.text) - cpu/blackfin/interrupt.o (.text) - cpu/blackfin/serial.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - board/bf533-ezkit/bf533-ezkit.o (.text) + cpu/blackfin/traps.o (.text .text.*) + cpu/blackfin/interrupt.o (.text .text.*) + cpu/blackfin/serial.o (.text .text.*) + common/dlmalloc.o (.text .text.*) + lib_generic/crc32.o (.text .text.*) + lib_generic/zlib.o (.text .text.*) + board/bf533-ezkit/bf533-ezkit.o (.text .text.*) . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text) + common/env_embedded.o (.text .text.*) #endif __initcode_start = .; - cpu/blackfin/initcode.o (.text) + cpu/blackfin/initcode.o (.text .text.*) __initcode_end = .; *(.text .text.*) diff --git a/board/bf533-stamp/u-boot.lds.S b/board/bf533-stamp/u-boot.lds.S index 187309f3f..76daa75c0 100644 --- a/board/bf533-stamp/u-boot.lds.S +++ b/board/bf533-stamp/u-boot.lds.S @@ -28,6 +28,8 @@ #include #include #undef ALIGN +#undef ENTRY +#undef bfin /* If we don't actually load anything into L1 data, this will avoid * a syntax error. If we do actually load something into L1 data, @@ -50,11 +52,12 @@ MEMORY l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE } +ENTRY(_start) SECTIONS { .text : { - cpu/blackfin/start.o (.text) + cpu/blackfin/start.o (.text .text.*) #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within @@ -63,18 +66,18 @@ SECTIONS * it linked after the configuration sector. */ - cpu/blackfin/traps.o (.text) - cpu/blackfin/interrupt.o (.text) - cpu/blackfin/serial.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) + cpu/blackfin/traps.o (.text .text.*) + cpu/blackfin/interrupt.o (.text .text.*) + cpu/blackfin/serial.o (.text .text.*) + common/dlmalloc.o (.text .text.*) + lib_generic/crc32.o (.text .text.*) . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text) + common/env_embedded.o (.text .text.*) #endif __initcode_start = .; - cpu/blackfin/initcode.o (.text) + cpu/blackfin/initcode.o (.text .text.*) __initcode_end = .; *(.text .text.*) diff --git a/board/bf537-stamp/u-boot.lds.S b/board/bf537-stamp/u-boot.lds.S index 187309f3f..76daa75c0 100644 --- a/board/bf537-stamp/u-boot.lds.S +++ b/board/bf537-stamp/u-boot.lds.S @@ -28,6 +28,8 @@ #include #include #undef ALIGN +#undef ENTRY +#undef bfin /* If we don't actually load anything into L1 data, this will avoid * a syntax error. If we do actually load something into L1 data, @@ -50,11 +52,12 @@ MEMORY l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE } +ENTRY(_start) SECTIONS { .text : { - cpu/blackfin/start.o (.text) + cpu/blackfin/start.o (.text .text.*) #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within @@ -63,18 +66,18 @@ SECTIONS * it linked after the configuration sector. */ - cpu/blackfin/traps.o (.text) - cpu/blackfin/interrupt.o (.text) - cpu/blackfin/serial.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) + cpu/blackfin/traps.o (.text .text.*) + cpu/blackfin/interrupt.o (.text .text.*) + cpu/blackfin/serial.o (.text .text.*) + common/dlmalloc.o (.text .text.*) + lib_generic/crc32.o (.text .text.*) . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text) + common/env_embedded.o (.text .text.*) #endif __initcode_start = .; - cpu/blackfin/initcode.o (.text) + cpu/blackfin/initcode.o (.text .text.*) __initcode_end = .; *(.text .text.*) diff --git a/board/bf561-ezkit/u-boot.lds.S b/board/bf561-ezkit/u-boot.lds.S index 99d6be634..3d0453e2f 100644 --- a/board/bf561-ezkit/u-boot.lds.S +++ b/board/bf561-ezkit/u-boot.lds.S @@ -28,6 +28,8 @@ #include #include #undef ALIGN +#undef ENTRY +#undef bfin /* If we don't actually load anything into L1 data, this will avoid * a syntax error. If we do actually load something into L1 data, @@ -50,11 +52,12 @@ MEMORY l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE } +ENTRY(_start) SECTIONS { .text : { - cpu/blackfin/start.o (.text) + cpu/blackfin/start.o (.text .text.*) #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within @@ -63,20 +66,20 @@ SECTIONS * it linked after the configuration sector. */ - cpu/blackfin/traps.o (.text) - cpu/blackfin/interrupt.o (.text) - cpu/blackfin/serial.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - board/bf561-ezkit/bf561-ezkit.o (.text) + cpu/blackfin/traps.o (.text .text.*) + cpu/blackfin/interrupt.o (.text .text.*) + cpu/blackfin/serial.o (.text .text.*) + common/dlmalloc.o (.text .text.*) + lib_generic/crc32.o (.text .text.*) + lib_generic/zlib.o (.text .text.*) + board/bf561-ezkit/bf561-ezkit.o (.text .text.*) . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text) + common/env_embedded.o (.text .text.*) #endif __initcode_start = .; - cpu/blackfin/initcode.o (.text) + cpu/blackfin/initcode.o (.text .text.*) __initcode_end = .; *(.text .text.*) From e7e684b10d73a303902208594c7c3e7e0d753282 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 24 Oct 2008 17:51:57 -0400 Subject: [PATCH 090/188] Blackfin: fix out-of-tree building with ldscripts Many of the Blackfin board linker scripts are preprocessed, so make sure we output the linker script into the build tree rather than the source tree. Signed-off-by: Mike Frysinger --- board/bf533-ezkit/Makefile | 7 +++---- board/bf533-ezkit/config.mk | 2 ++ board/bf533-stamp/Makefile | 7 +++---- board/bf533-stamp/config.mk | 2 ++ board/bf537-stamp/Makefile | 7 +++---- board/bf537-stamp/config.mk | 2 ++ board/bf561-ezkit/Makefile | 7 +++---- board/bf561-ezkit/config.mk | 2 ++ 8 files changed, 20 insertions(+), 16 deletions(-) diff --git a/board/bf533-ezkit/Makefile b/board/bf533-ezkit/Makefile index b2d7acffe..6a45b7cb2 100644 --- a/board/bf533-ezkit/Makefile +++ b/board/bf533-ezkit/Makefile @@ -35,12 +35,11 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -u-boot.lds: u-boot.lds.S - $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp - mv -f $@.tmp $@ +$(obj)u-boot.lds: u-boot.lds.S + $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk index 984792476..c8b9fb8c1 100644 --- a/board/bf533-ezkit/config.mk +++ b/board/bf533-ezkit/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds + # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile index 21f6ad1b4..5ae022885 100644 --- a/board/bf533-stamp/Makefile +++ b/board/bf533-stamp/Makefile @@ -35,12 +35,11 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -u-boot.lds: u-boot.lds.S - $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp - mv -f $@.tmp $@ +$(obj)u-boot.lds: u-boot.lds.S + $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk index 984792476..c8b9fb8c1 100644 --- a/board/bf533-stamp/config.mk +++ b/board/bf533-stamp/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds + # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile index e5481bfc5..e5ef9af5c 100644 --- a/board/bf537-stamp/Makefile +++ b/board/bf537-stamp/Makefile @@ -35,12 +35,11 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -u-boot.lds: u-boot.lds.S - $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp - mv -f $@.tmp $@ +$(obj)u-boot.lds: u-boot.lds.S + $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk index d9e884e0e..719b97e25 100644 --- a/board/bf537-stamp/config.mk +++ b/board/bf537-stamp/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds + # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 diff --git a/board/bf561-ezkit/Makefile b/board/bf561-ezkit/Makefile index a1a4433fc..e7ee24356 100644 --- a/board/bf561-ezkit/Makefile +++ b/board/bf561-ezkit/Makefile @@ -35,12 +35,11 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -u-boot.lds: u-boot.lds.S - $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp - mv -f $@.tmp $@ +$(obj)u-boot.lds: u-boot.lds.S + $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk index 77c888b3b..710809a9e 100644 --- a/board/bf561-ezkit/config.mk +++ b/board/bf561-ezkit/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds + # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) From 687f952e4119594ab913be11c90f7f018c2a7a79 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 11 Dec 2008 07:04:48 -0500 Subject: [PATCH 091/188] Blackfin: drop CONFIG_SPI handling in board init The eeprom SPI init functions are duplicated as the common code already executes these for us. Signed-off-by: Mike Frysinger --- lib_blackfin/board.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index fde4bbe0f..05e66e3c5 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -374,13 +374,6 @@ void board_init_r(gd_t * id, ulong dest_addr) mem_malloc_init(); malloc_bin_reloc(); -#ifdef CONFIG_SPI -# if ! defined(CONFIG_ENV_IS_IN_EEPROM) - spi_init_f(); -# endif - spi_init_r(); -#endif - #ifdef CONFIG_CMD_NAND puts("NAND: "); nand_init(); /* go init the NAND */ From 032a1c934ef4dc003281f57302b6e693062c1868 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 5 Jan 2009 16:09:44 -0500 Subject: [PATCH 092/188] bf537-stamp/nand: fix board_nand_init prototype The board_nand_init() function should return an int, not void. Signed-off-by: Mike Frysinger --- board/bf537-stamp/nand.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/board/bf537-stamp/nand.c b/board/bf537-stamp/nand.c index c597f2db1..20a7d0ef4 100644 --- a/board/bf537-stamp/nand.c +++ b/board/bf537-stamp/nand.c @@ -87,7 +87,7 @@ int bfin_device_ready(struct mtd_info *mtd) * Members with a "?" were not set in the merged testing-NAND branch, * so they are not set here either. */ -void board_nand_init(struct nand_chip *nand) +int board_nand_init(struct nand_chip *nand) { *PORT(CONFIG_NAND_GPIO_PORT, _FER) &= ~BFIN_NAND_READY; *PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY; @@ -97,5 +97,7 @@ void board_nand_init(struct nand_chip *nand) nand->ecc.mode = NAND_ECC_SOFT; nand->dev_ready = bfin_device_ready; nand->chip_delay = 30; + + return 0; } #endif From a9f3acbcd07da72b5446ce557531a3ed8b8beff0 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 12 Jan 2009 14:50:35 +0100 Subject: [PATCH 093/188] MPC86xx: fix build warnings Signed-off-by: Wolfgang Denk --- cpu/mpc86xx/cpu.c | 2 +- cpu/mpc86xx/fdt.c | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 35680238d..dc53bee58 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -101,7 +101,7 @@ checkcpu(void) if (sysinfo.freqLocalBus > LCRR_CLKDIV) { printf("LBC:%4lu MHz\n", sysinfo.freqLocalBus / 1000000); } else { - printf("LBC: unknown (LCRR[CLKDIV] = 0x%02x)\n", + printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); } diff --git a/cpu/mpc86xx/fdt.c b/cpu/mpc86xx/fdt.c index e277040bb..383b06b5a 100644 --- a/cpu/mpc86xx/fdt.c +++ b/cpu/mpc86xx/fdt.c @@ -13,8 +13,6 @@ DECLARE_GLOBAL_DATA_PTR; -DECLARE_GLOBAL_DATA_PTR; - void ft_cpu_setup(void *blob, bd_t *bd) { #if (CONFIG_NUM_CPUS > 1) From 79e436cad3b4a7db88408c3f05175028f30d700d Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Wed, 3 Dec 2008 22:36:26 -0600 Subject: [PATCH 094/188] sbc8641d: Fix PCI mapping concepts Rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. This makes the code easier to read and understand, and facilitates mapping changes going forward. Signed-off-by: Becky Bruce --- board/sbc8641d/law.c | 10 +++++----- board/sbc8641d/sbc8641d.c | 8 ++++---- include/configs/sbc8641d.h | 32 ++++++++++++++++++-------------- 3 files changed, 27 insertions(+), 23 deletions(-) diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c index de47fcd63..760c6935d 100644 --- a/board/sbc8641d/law.c +++ b/board/sbc8641d/law.c @@ -45,14 +45,14 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), - SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO) + SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO) }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 1471e581e..508bdc5dd 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -247,14 +247,14 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_BUS, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); @@ -290,14 +290,14 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI2_MEM_BASE, + CONFIG_SYS_PCI2_MEM_BUS, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI2_IO_BASE, + CONFIG_SYS_PCI2_IO_BUS, CONFIG_SYS_PCI2_IO_PHYS, CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 001294575..1008812b7 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -311,18 +311,22 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE +#define CONFIG_SYS_PCI1_IO_BUS 0xe2000000 +#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS +#define CONFIG_SYS_PCI1_IO_VIRT CONFIG_SYS_PCI1_IO_BUS #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS +#define CONFIG_SYS_PCI2_MEM_VIRT CONFIG_SYS_PCI2_MEM_BUS #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BASE 0xe3000000 -#define CONFIG_SYS_PCI2_IO_PHYS CONFIG_SYS_PCI2_IO_BASE +#define CONFIG_SYS_PCI2_IO_BUS 0xe3000000 +#define CONFIG_SYS_PCI2_IO_PHYS CONFIG_SYS_PCI2_IO_BUS +#define CONFIG_SYS_PCI2_IO_VIRT CONFIG_SYS_PCI2_IO_BUS #define CONFIG_SYS_PCI2_IO_SIZE 0x1000000 /* 16M */ #if defined(CONFIG_PCI) @@ -409,10 +413,10 @@ * 0xa000_0000 512M PCI-Express 2 Memory * Changed it for operating from 0xd0000000 */ -#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW \ +#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U /* @@ -452,10 +456,10 @@ * 0xe300_0000 16M PCI-Express 2 I/0 * Note that this is at 0xe0000000 */ -#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_BASE | BATL_PP_RW \ +#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U /* From 3e3fffe3baf3befde287fec1fcbfe55052fb8946 Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Wed, 3 Dec 2008 22:36:44 -0600 Subject: [PATCH 095/188] mpc8610hpcd: Fix PCI mapping concepts Rename _BASE to _BUS, as it's actually a PCI bus address, separate virtual and physical addresses into _VIRT and _PHYS, and use each appopriately. This makes the code easier to read and understand, and facilitates mapping changes going forward. Signed-off-by: Becky Bruce --- board/freescale/mpc8610hpcd/law.c | 4 ++-- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 12 ++++++------ include/configs/MPC8610HPCD.h | 24 ++++++++++++----------- 3 files changed, 21 insertions(+), 19 deletions(-) diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c index 2aad28aee..0fc838484 100644 --- a/board/freescale/mpc8610hpcd/law.c +++ b/board/freescale/mpc8610hpcd/law.c @@ -31,8 +31,8 @@ struct law_entry law_table[] = { #if !defined(CONFIG_SPD_EEPROM) SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1), #endif - SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2), diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 2792778e3..a2097a5af 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -266,14 +266,14 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); @@ -321,14 +321,14 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BASE, + CONFIG_SYS_PCIE2_MEM_BUS, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BASE, + CONFIG_SYS_PCIE2_IO_BUS, CONFIG_SYS_PCIE2_IO_PHYS, CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); @@ -370,14 +370,14 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_BUS, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 27517e5b1..4bd3e0bd3 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -273,11 +273,13 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x0000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ /* For RTL8139 */ @@ -285,18 +287,18 @@ #define _IO_BASE 0x00000000 /* controller 1, Base address 0xa000 */ -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ /* controller 2, Base Address 0x9000 */ -#define CONFIG_SYS_PCIE2_MEM_BASE 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE +#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 /* reuse mem LAW */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ @@ -364,7 +366,7 @@ #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U @@ -375,7 +377,7 @@ #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U From 9afc2ef0307aecf52482df67c31b75d5f9e66b47 Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Fri, 9 Jan 2009 16:00:55 +0800 Subject: [PATCH 096/188] Fix IO port selection issue on MPC8544DS and MPC8572DS boards The IO port selection is not correct on MPC8572DS and MPC8544DS board. This patch fixes this issue. For MPC8572 Port cfg_io_ports PCIE1 0x2, 0x3, 0x7, 0xb, 0xc, 0xf PCIE2 0x3, 0x7 PCIE3 0x7 For MPC8544 Port cfg_io_ports PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 PCIE2 0x4, 0x5, 0x6, 0x7 PCIE3 0x6, 0x7 Signed-off-by: Roy Zang --- board/freescale/mpc8544ds/mpc8544ds.c | 2 +- board/freescale/mpc8572ds/mpc8572ds.c | 8 +++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 14581abdd..13c55fd37 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -121,7 +121,7 @@ pci_init_board(void) volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; struct pci_controller *hose = &pcie3_hose; int pcie_ep = (host_agent == 1); - int pcie_configured = io_sel >= 1; + int pcie_configured = io_sel >= 6; struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index a14db5ad2..4733b82f0 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -166,7 +166,7 @@ void pci_init_board(void) struct pci_controller *hose = &pcie3_hose; int pcie_ep = (host_agent == 0) || (host_agent == 3) || (host_agent == 5) || (host_agent == 6); - int pcie_configured = io_sel >= 1; + int pcie_configured = (io_sel == 0x7); struct pci_region *r = hose->regions; u32 temp32; @@ -234,7 +234,7 @@ void pci_init_board(void) struct pci_controller *hose = &pcie2_hose; int pcie_ep = (host_agent == 2) || (host_agent == 4) || (host_agent == 6) || (host_agent == 0); - int pcie_configured = io_sel & 4; + int pcie_configured = (io_sel == 0x3) || (io_sel == 0x7); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -287,7 +287,9 @@ void pci_init_board(void) struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5); - int pcie_configured = io_sel & 6; + int pcie_configured = (io_sel == 0x2) || (io_sel == 0x3) || + (io_sel == 0x7) || (io_sel == 0xb) || + (io_sel == 0xc) || (io_sel == 0xf); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ From 028e116811d28a031660f1ad9e20ac1293b3c5c7 Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Fri, 9 Jan 2009 16:01:52 +0800 Subject: [PATCH 097/188] PCIE2 and PCIE3 are decided by corresponing bit in devdisr instead of PCIE1 bit PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of PCIE1 bit. On MPC8572DS board, PCIE refers to PCIE1. Signed-off-by: Roy Zang --- board/freescale/mpc8572ds/mpc8572ds.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 4733b82f0..c2487e5b8 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -170,7 +170,7 @@ void pci_init_board(void) struct pci_region *r = hose->regions; u32 temp32; - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ printf ("\n PCIE3 connected to ULI as %s (base address %x)", pcie_ep ? "End Point" : "Root Complex", (uint)pci); @@ -237,7 +237,7 @@ void pci_init_board(void) int pcie_configured = (io_sel == 0x3) || (io_sel == 0x7); struct pci_region *r = hose->regions; - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", pcie_ep ? "End Point" : "Root Complex", (uint)pci); From 6d3a10f73ece7ffb736890c10e023222612a4aa0 Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Fri, 9 Jan 2009 16:02:35 +0800 Subject: [PATCH 098/188] Change PCIE1&2 deciide logic on MPC8544DS board more readable The IO port selection for MPC8544DS board: Port cfg_io_ports PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 PCIE2 0x4, 0x5, 0x6, 0x7 PCIE3 0x6, 0x7 This patch changes the PCIE12 and PCIE2 logic more readable. Signed-off-by: Roy Zang --- board/freescale/mpc8544ds/mpc8544ds.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 13c55fd37..977731289 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -188,7 +188,7 @@ pci_init_board(void) volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 5); - int pcie_configured = io_sel & 6; + int pcie_configured = io_sel >= 2; struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -251,7 +251,7 @@ pci_init_board(void) volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; int pcie_ep = (host_agent == 3); - int pcie_configured = io_sel & 4; + int pcie_configured = io_sel >= 4; struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ From 950264317eb9594b2b5ee2fb65206200a1c6007a Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 13 Jan 2009 16:29:22 -0500 Subject: [PATCH 099/188] Change DDR tlb start entry to CONFIG param for 85xx So that we can locate the DDR tlb start entry to the value other than 8. By default, it is still 8. Signed-off-by: Haiying Wang --- cpu/mpc85xx/tlb.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 5b5f7914f..25fa9ee8f 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -125,6 +125,10 @@ void init_addr_map(void) } #endif +#ifndef CONFIG_SYS_DDR_TLB_START +#define CONFIG_SYS_DDR_TLB_START 8 +#endif + unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) { unsigned int tlb_size; @@ -171,7 +175,7 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) * Configure DDR TLB1 entries. * Starting at TLB1 8, use no more than 8 TLB1 entries. */ - ram_tlb_index = 8; + ram_tlb_index = CONFIG_SYS_DDR_TLB_START; ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; while (ram_tlb_address < (memsize_in_meg * 1024 * 1024) && ram_tlb_index < 16) { From b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 13 Jan 2009 16:29:28 -0500 Subject: [PATCH 100/188] Some changes of TLB entry setting for MPC8572DS - Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0 can not access PIXIS_BASE anymore (any access will cause DataTLBError exception) - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board. Signed-off-by: Haiying Wang --- board/freescale/mpc8572ds/tlb.c | 7 +++---- include/configs/MPC8572DS.h | 1 + 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index 8d1f646fa..829896ac0 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -41,10 +41,6 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 0), - /* TLB 1 */ /* *I*** - Covers boot page */ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, @@ -86,6 +82,9 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_4K, 1), }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 37c3f4200..6c7a36454 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -92,6 +92,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) /* DDR Setup */ +#define CONFIG_SYS_DDR_TLB_START 9 #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ From fceebb45a0b97e92f9889861f8c3b9cb885e706f Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 2 Jan 2009 12:16:35 +0100 Subject: [PATCH 101/188] ppc4xx: Enable auto RS485 mode on PLU405 boards This patch turns on the auto RS485 mode in the 2nd external uart on PLU405 boards. This is a special mode of the used Exar XR16C2850 uart. Because these boards only have a 485 physical layer connected it's a good idea to turn it on by default. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- board/esd/plu405/plu405.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index 61186a8d7..85057a268 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -104,6 +104,7 @@ int misc_init_r (void) unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); unsigned char *dst; + unsigned char fctr; ulong len = sizeof(fpgadata); int status; int index; @@ -203,6 +204,15 @@ int misc_init_r (void) out_8(duart0_mcr, 0x08); out_8(duart1_mcr, 0x08); + /* + * Enable auto RS485 mode in 2nd external uart + */ + out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */ + fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */ + fctr |= 0x08; /* enable RS485 mode */ + out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */ + out_8((void *)DUART1_BA + 3, 0); /* write LCR */ + return (0); } From f6a1f490d224c600a09137e58d1026d150b8e679 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 2 Jan 2009 12:17:36 +0100 Subject: [PATCH 102/188] ppc4xx: Cleanup CPCI405 board code This patch cleans up CPCI405 board support: - wrap long lines - unification of spaces in function calls - remove dead code Use correct io accessors on peripherals. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- board/esd/cpci405/cpci405.c | 307 +++++++++++++++++------------------- 1 file changed, 144 insertions(+), 163 deletions(-) diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index c5ccb348a..9bb5f6360 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -20,7 +20,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ - #include #include #include @@ -31,16 +30,16 @@ DECLARE_GLOBAL_DATA_PTR; -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/ -#if 0 -#define FPGA_DEBUG -#endif +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern void __ft_board_setup(void *blob, bd_t *bd); + +#undef FPGA_DEBUG /* fpga configuration data - generated by bin2cc */ const unsigned char fpgadata[] = { -#ifdef CONFIG_CPCI405_VER2 -# ifdef CONFIG_CPCI405AB +#if defined(CONFIG_CPCI405_VER2) +# if defined(CONFIG_CPCI405AB) # include "fpgadata_cpci405ab.c" # else # include "fpgadata_cpci4052.c" @@ -56,7 +55,7 @@ const unsigned char fpgadata[] = #include "../common/fpga.c" #include "../common/auto_update.h" -#ifdef CONFIG_CPCI405AB +#if defined(CONFIG_CPCI405AB) au_image_t au_image[] = { {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT}, {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR}, @@ -65,7 +64,7 @@ au_image_t au_image[] = { {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT}, }; #else -#ifdef CONFIG_CPCI405_VER2 +#if defined(CONFIG_CPCI405_VER2) au_image_t au_image[] = { {"cpci4052/preinst.img", 0, -1, AU_SCRIPT}, {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR}, @@ -91,7 +90,7 @@ int cpci405_version(void); int gunzip(void *, int, unsigned char *, unsigned long *); void lxt971_no_sleep(void); -int board_early_init_f (void) +int board_early_init_f(void) { #ifndef CONFIG_CPCI405_VER2 int index, len, i; @@ -100,18 +99,19 @@ int board_early_init_f (void) #ifdef FPGA_DEBUG /* set up serial port with default baudrate */ - (void) get_clocks (); + (void)get_clocks(); gd->baudrate = CONFIG_BAUDRATE; - serial_init (); + serial_init(); console_init_f(); #endif /* - * First pull fpga-prg pin low, to disable fpga logic (on version 2 board) + * First pull fpga-prg pin low, + * to disable fpga logic (on version 2 board) */ out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ - out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ + out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ + out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ out32(GPIO0_OR, 0); /* pull prg low */ /* @@ -124,39 +124,42 @@ int board_early_init_f (void) /* booting FPGA failed */ #ifndef FPGA_DEBUG /* set up serial port with default baudrate */ - (void) get_clocks (); + (void)get_clocks(); gd->baudrate = CONFIG_BAUDRATE; - serial_init (); + serial_init(); console_init_f(); #endif printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + printf("(Timeout: INIT not low after " + "asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + printf("(Timeout: INIT not high after " + "deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); + printf("(Timeout: DONE not high after " + "programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; - for (i=0; i<4; i++) { + for (i = 0; i < 4; i++) { len = fpgadata[index]; - printf("FPGA: %s\n", &(fpgadata[index+1])); - index += len+3; + printf("FPGA: %s\n", &(fpgadata[index + 1])); + index += len + 3; } - putc ('\n'); + putc('\n'); /* delayed reboot */ - for (i=20; i>0; i--) { + for (i = 20; i > 0; i--) { printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) + for (index = 0; index < 1000; index++) udelay(1000); } - putc ('\n'); + putc('\n'); do_reset(NULL, 0, 0, NULL); } } @@ -167,7 +170,7 @@ int board_early_init_f (void) * IRQ 16 405GP internally generated; active low; level sensitive * IRQ 17-24 RESERVED * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive + * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens. * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive @@ -177,7 +180,7 @@ int board_early_init_f (void) mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicer, 0x00000000); /* disable all ints */ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ -#ifdef CONFIG_CPCI405_6U +#if defined(CONFIG_CPCI405_6U) if (cpci405_version() == 3) { mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ } else { @@ -187,21 +190,20 @@ int board_early_init_f (void) mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ #endif mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicvcr, 0x00000001); /* set vect base=0, + * INT0 highest priority */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ return 0; } -/* ------------------------------------------------------------------------- */ - int ctermm2(void) { -#ifdef CONFIG_CPCI405_VER2 +#if defined(CONFIG_CPCI405_VER2) return 0; /* no, board is cpci405 */ #else - if ((*(unsigned char *)0xf0000400 == 0x00) && - (*(unsigned char *)0xf0000401 == 0x01)) + if ((in_8((void*)0xf0000400) == 0x00) && + (in_8((void*)0xf0000401) == 0x01)) return 0; /* no, board is cpci405 */ else return -1; /* yes, board is cterm-m2 */ @@ -228,8 +230,8 @@ int cpci405_version(void) mtdcr(cntrl0, cntrl0Reg | 0x03000000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000); - udelay(1000); /* wait some time before reading input */ - value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */ + udelay(1000); /* wait some time before reading input */ + value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */ /* * Restore GPIO settings @@ -263,7 +265,7 @@ int misc_init_r (void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; -#ifdef CONFIG_CPCI405_VER2 +#if defined(CONFIG_CPCI405_VER2) { unsigned char *dst; ulong len = sizeof(fpgadata); @@ -283,9 +285,10 @@ int misc_init_r (void) mtdcr(cntrl0, cntrl0Reg | 0x00300000); dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); + if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, + (uchar *)fpgadata, &len) != 0) { + printf("GUNZIP ERROR - must RESET board to recover\n"); + do_reset(NULL, 0, 0, NULL); } status = fpga_boot(dst, len); @@ -293,31 +296,34 @@ int misc_init_r (void) printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + printf("(Timeout: INIT not low after " + "asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + printf("(Timeout: INIT not high after " + "deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); + printf("(Timeout: DONE not high after " + "programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; - for (i=0; i<4; i++) { + for (i = 0; i < 4; i++) { len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; + printf("FPGA: %s\n", &(dst[index + 1])); + index += len + 3; } - putc ('\n'); + putc('\n'); /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) + for (i = 20; i > 0; i--) { + printf("Rebooting in %2d seconds \r", i); + for (index = 0; index < 1000; index++) udelay(1000); } - putc ('\n'); + putc('\n'); do_reset(NULL, 0, 0, NULL); } @@ -328,12 +334,12 @@ int misc_init_r (void) /* display infos on fpgaimage */ index = 15; - for (i=0; i<4; i++) { + for (i = 0; i < 4; i++) { len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; + printf("%s ", &(dst[index + 1])); + index += len + 3; } - putc ('\n'); + putc('\n'); free(dst); @@ -345,68 +351,48 @@ int misc_init_r (void) SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); udelay(1000); /* wait 1ms */ -#ifdef CONFIG_CPCI405_6U +#if defined(CONFIG_CPCI405_6U) +#error HIER GETH ES WEITER MIT IO ACCESSORS if (cpci405_version() == 3) { - volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR; - volatile unsigned char *leds = (unsigned char *)CONFIG_SYS_LED_ADDR; - /* * Enable outputs in fpga on version 3 board */ - *fpga_mode |= CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT; + out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, + in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | + CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT); /* * Set outputs to 0 */ - *leds = 0x00; + out_8((void*)CONFIG_SYS_LED_ADDR, 0x00); /* * Reset external DUART */ - *fpga_mode |= CONFIG_SYS_FPGA_MODE_DUART_RESET; + out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, + in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | + CONFIG_SYS_FPGA_MODE_DUART_RESET); udelay(100); - *fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_DUART_RESET); + out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, + in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) & + ~CONFIG_SYS_FPGA_MODE_DUART_RESET); } #endif } else { puts("\n*** U-Boot Version does not match Board Version!\n"); puts("*** CPCI-405 Version 1.x detected!\n"); - puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n"); + puts("*** Please use correct U-Boot version " + "(CPCI405 instead of CPCI4052)!\n\n"); } } - #else /* CONFIG_CPCI405_VER2 */ - -#if 0 /* test-only: code-plug now not relavant for ip-address any more */ - /* - * Generate last byte of ip-addr from code-plug @ 0xf0000400 - */ - if (ctermm2()) { - char str[32]; - unsigned char ipbyte = *(unsigned char *)0xf0000400; - - /* - * Only overwrite ip-addr with allowed values - */ - if ((ipbyte != 0x00) && (ipbyte != 0xff)) { - bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte; - sprintf(str, "%ld.%ld.%ld.%ld", - (bd->bi_ip_addr & 0xff000000) >> 24, - (bd->bi_ip_addr & 0x00ff0000) >> 16, - (bd->bi_ip_addr & 0x0000ff00) >> 8, - (bd->bi_ip_addr & 0x000000ff)); - setenv("ipaddr", str); - } - } -#endif - if (cpci405_version() >= 2) { puts("\n*** U-Boot Version does not match Board Version!\n"); puts("*** CPCI-405 Board Version 2.x detected!\n"); - puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n"); + puts("*** Please use correct U-Boot version " + "(CPCI4052 instead of CPCI405)!\n\n"); } - #endif /* CONFIG_CPCI405_VER2 */ /* @@ -415,46 +401,33 @@ int misc_init_r (void) cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | 0x00001000); - return (0); + return 0; } /* * Check Board Identity: */ -int checkboard (void) +int checkboard(void) { #ifndef CONFIG_CPCI405_VER2 int index; int len; #endif char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_r("serial#", str, sizeof(str)); unsigned short ver; - puts ("Board: "); + puts("Board: "); - if (i == -1) { - puts ("### No HW ID - assuming CPCI405"); - } else { + if (i == -1) + puts("### No HW ID - assuming CPCI405"); + else puts(str); - } ver = cpci405_version(); printf(" (Ver %d.x, ", ver); -#if 0 /* test-only */ - if (ver >= 2) { - volatile u16 *fpga_status = (u16 *)CONFIG_SYS_FPGA_BASE_ADDR + 1; - - if (*fpga_status & CONFIG_SYS_FPGA_STATUS_FLASH) { - puts ("FLASH Bank B, "); - } else { - puts ("FLASH Bank A, "); - } - } -#endif - if (ctermm2()) { char str[4]; @@ -465,32 +438,31 @@ int checkboard (void) setenv("boardid", str); printf("CTERM-M2 - Id=%s)", str); } else { - if (cpci405_host()) { - puts ("PCI Host Version)"); - } else { - puts ("PCI Adapter Version)"); - } + if (cpci405_host()) + puts("PCI Host Version)"); + else + puts("PCI Adapter Version)"); } #ifndef CONFIG_CPCI405_VER2 - puts ("\nFPGA: "); + puts("\nFPGA: "); /* display infos on fpgaimage */ index = 15; - for (i=0; i<4; i++) { + for (i = 0; i < 4; i++) { len = fpgadata[index]; - printf("%s ", &(fpgadata[index+1])); - index += len+3; + printf("%s ", &(fpgadata[index + 1])); + index += len + 3; } #endif - putc ('\n'); + putc('\n'); return 0; } void reset_phy(void) { -#ifdef CONFIG_LXT971_NO_SLEEP +#if defined(CONFIG_LXT971_NO_SLEEP) /* * Disable sleep mode in LXT971 @@ -499,25 +471,24 @@ void reset_phy(void) #endif } -#ifdef CONFIG_CPCI405_VER2 -#ifdef CONFIG_IDE_RESET - +#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET) void ide_set_reset(int on) { - volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR; - /* * Assert or deassert CompactFlash Reset Pin */ - if (on) { /* assert RESET */ - *fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_CF_RESET); - } else { /* release RESET */ - *fpga_mode |= CONFIG_SYS_FPGA_MODE_CF_RESET; + if (on) { /* assert RESET */ + out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, + in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) & + ~CONFIG_SYS_FPGA_MODE_CF_RESET); + } else { /* release RESET */ + out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, + in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | + CONFIG_SYS_FPGA_MODE_CF_RESET); } } -#endif /* CONFIG_IDE_RESET */ -#endif /* CONFIG_CPCI405_VER2 */ +#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */ #if defined(CONFIG_PCI) void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) @@ -552,15 +523,22 @@ int pci_pre_init(struct pci_controller *hose) } #endif /* defined(CONFIG_PCI) */ +#if defined(CONFIG_CPCI405AB) +#define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ + CONFIG_SYS_FPGA_MODE), \ + in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ + CONFIG_SYS_FPGA_MODE)) | \ + CONFIG_SYS_FPGA_MODE_1WIRE_DIR) -#ifdef CONFIG_CPCI405AB +#define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ + CONFIG_SYS_FPGA_MODE), \ + in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ + CONFIG_SYS_FPGA_MODE)) & \ + ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \ - |= CONFIG_SYS_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_SET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \ - &= ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_GET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_STATUS) \ - & CONFIG_SYS_FPGA_MODE_1WIRE) +#define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ + CONFIG_SYS_FPGA_STATUS)) & \ + CONFIG_SYS_FPGA_MODE_1WIRE) /* * Generate a 1-wire reset, return 1 if no presence detect was found, @@ -630,7 +608,7 @@ void OWWriteByte(int data) { int loop; - for (loop=0; loop<8; loop++) { + for (loop = 0; loop < 8; loop++) { OWWriteBit(data & 0x01); data >>= 1; } @@ -640,11 +618,10 @@ int OWReadByte(void) { int loop, result = 0; - for (loop=0; loop<8; loop++) { + for (loop = 0; loop < 8; loop++) { result >>= 1; - if (OWReadBit()) { + if (OWReadBit()) result |= 0x80; - } } return result; @@ -652,7 +629,7 @@ int OWReadByte(void) int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - volatile unsigned short val; + unsigned short val; int result; int i; unsigned char ow_id[6]; @@ -662,23 +639,25 @@ int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * Clear 1-wire bit (open drain with pull-up) */ - val = *(volatile unsigned short *)0xf0400000; - val &= ~0x1000; /* clear 1-wire bit */ - *(volatile unsigned short *)0xf0400000 = val; + val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + + CONFIG_SYS_FPGA_MODE)); + val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */ + out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + + CONFIG_SYS_FPGA_MODE), val); result = OWTouchReset(); - if (result != 0) { + if (result != 0) puts("No 1-wire device detected!\n"); - } OWWriteByte(0x33); /* send read rom command */ OWReadByte(); /* skip family code ( == 0x01) */ - for (i=0; i<6; i++) { + for (i = 0; i < 6; i++) ow_id[i] = OWReadByte(); - } ow_crc = OWReadByte(); /* read crc */ - sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]); + sprintf(str, "%08X%04X", + *(unsigned int *)&ow_id[0], + *(unsigned short *)&ow_id[4]); printf("Setting environment variable 'ow_id' to %s\n", str); setenv("ow_id", str); @@ -690,8 +669,8 @@ U_BOOT_CMD( NULL ); -#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */ -#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/ +#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */ +#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */ /* * Write backplane ip-address... @@ -706,12 +685,14 @@ int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) IPaddr_t ipaddr; buf = malloc(CONFIG_ENV_SIZE_2); - if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) { + if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, + (uchar *)buf, CONFIG_ENV_SIZE_2)) puts("\nError reading backplane EEPROM!\n"); - } else { - crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4); + else { + crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4); if (crc != *(ulong *)buf) { - printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf); + printf("ERROR: crc mismatch %08lx %08lx\n", + crc, *(ulong *)buf); return -1; } @@ -768,12 +749,12 @@ int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) memset(buf, 0, CONFIG_ENV_SIZE_2); sprintf(str, "bp_ip=%s", argv[1]); strcpy(buf+4, str); - crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4); + crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4); *(ulong *)buf = crc; - if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) { + if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, + 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) puts("\nError writing backplane EEPROM!\n"); - } free(buf); From 600fe46fb3dab7f07604f9009904f31584415114 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 2 Jan 2009 12:18:12 +0100 Subject: [PATCH 103/188] ppc4xx: Disable pci node in device tree on CPCI405 pci adapters Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- board/esd/cpci405/cpci405.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 9bb5f6360..bd569a629 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -21,6 +21,8 @@ * MA 02111-1307 USA */ #include +#include +#include #include #include #include @@ -523,6 +525,28 @@ int pci_pre_init(struct pci_controller *hose) } #endif /* defined(CONFIG_PCI) */ +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + int rc; + + __ft_board_setup(blob, bd); + + /* + * Disable PCI in adapter mode. + */ + if (!cpci405_host()) { + rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status", + "disabled", sizeof("disabled"), 1); + if (rc) { + printf("Unable to update property status in PCI node, " + "err=%s\n", + fdt_strerror(rc)); + } + } +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + #if defined(CONFIG_CPCI405AB) #define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ CONFIG_SYS_FPGA_MODE), \ From 3ba605d4beec649438539e7df97b5fedb26592fb Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 2 Jan 2009 12:18:49 +0100 Subject: [PATCH 104/188] ppc4xx: Add loadpci command to esd's CPCI4052 and CPCI405AB boards This patch adds esd's loadpci BSP command to CPCI4052 and CPCI405AB board. This requires CONFIG_CMD_BSP and CONFIG_PRAM. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- board/esd/cpci405/Makefile | 1 + include/configs/CPCI4052.h | 2 ++ include/configs/CPCI405AB.h | 3 +++ 3 files changed, 6 insertions(+) diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile index 3867bd809..7516c2280 100644 --- a/board/esd/cpci405/Makefile +++ b/board/esd/cpci405/Makefile @@ -29,6 +29,7 @@ endif LIB = $(obj)lib$(BOARD).a COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o +COBJS += ../common/cmd_loadpci.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index e231fa705..d0b4d1133 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -216,6 +216,8 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CONFIG_PRAM 0 /* use pram variable to overwrite */ + /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 2319c5872..69c8c6eee 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -92,6 +92,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING +#define CONFIG_CMD_BSP #define CONFIG_CMD_EEPROM @@ -212,6 +213,8 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ +#define CONFIG_PRAM 0 /* use pram variable to overwrite */ + /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is From e92c9a860e44c14513c8909ce4299e253a775eeb Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 14 Jan 2009 22:35:30 +0100 Subject: [PATCH 105/188] cpu/mpc824x/Makefile: fix warning with parallel builds Parallel builds would occasionally issue this build warning: ln: creating symbolic link `cpu/mpc824x/bedbug_603e.c': File exists Use "ln -sf" as quick work around for the issue. Signed-off-by: Wolfgang Denk --- cpu/mpc824x/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpu/mpc824x/Makefile b/cpu/mpc824x/Makefile index f249dd7c3..a57ad12c4 100644 --- a/cpu/mpc824x/Makefile +++ b/cpu/mpc824x/Makefile @@ -44,7 +44,7 @@ $(LIB): $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(obj)bedbug_603e.c: - ln -s $(src)../mpc8260/bedbug_603e.c $(obj)bedbug_603e.c + ln -sf $(src)../mpc8260/bedbug_603e.c $(obj)bedbug_603e.c ######################################################################### From 0e3ece33801e377be67ffa29f083421ad820f28b Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 14 Jan 2009 23:26:05 +0100 Subject: [PATCH 106/188] Prepare 2009.01-rc2 Update CHANGELOG. Signed-off-by: Wolfgang Denk --- CHANGELOG | 588 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 588 insertions(+) diff --git a/CHANGELOG b/CHANGELOG index 9af36c123..17c569167 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,579 @@ +commit e92c9a860e44c14513c8909ce4299e253a775eeb +Author: Wolfgang Denk +Date: Wed Jan 14 22:35:30 2009 +0100 + + cpu/mpc824x/Makefile: fix warning with parallel builds + + Parallel builds would occasionally issue this build warning: + + ln: creating symbolic link `cpu/mpc824x/bedbug_603e.c': File exists + + Use "ln -sf" as quick work around for the issue. + + Signed-off-by: Wolfgang Denk + +commit b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6 +Author: Haiying Wang +Date: Tue Jan 13 16:29:28 2009 -0500 + + Some changes of TLB entry setting for MPC8572DS + + - Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, + all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0 + can not access PIXIS_BASE anymore (any access will cause DataTLBError exception) + + - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board. + + Signed-off-by: Haiying Wang + +commit 950264317eb9594b2b5ee2fb65206200a1c6007a +Author: Haiying Wang +Date: Tue Jan 13 16:29:22 2009 -0500 + + Change DDR tlb start entry to CONFIG param for 85xx + + So that we can locate the DDR tlb start entry to the value other than 8. By + default, it is still 8. + + Signed-off-by: Haiying Wang + +commit 6d3a10f73ece7ffb736890c10e023222612a4aa0 +Author: Roy Zang +Date: Fri Jan 9 16:02:35 2009 +0800 + + Change PCIE1&2 deciide logic on MPC8544DS board more readable + + The IO port selection for MPC8544DS board: + Port cfg_io_ports + PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 + PCIE2 0x4, 0x5, 0x6, 0x7 + PCIE3 0x6, 0x7 + This patch changes the PCIE12 and PCIE2 logic more readable. + Signed-off-by: Roy Zang + +commit 028e116811d28a031660f1ad9e20ac1293b3c5c7 +Author: Roy Zang +Date: Fri Jan 9 16:01:52 2009 +0800 + + PCIE2 and PCIE3 are decided by corresponing bit in devdisr instead of PCIE1 bit + + PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of + PCIE1 bit. + On MPC8572DS board, PCIE refers to PCIE1. + Signed-off-by: Roy Zang + +commit 9afc2ef0307aecf52482df67c31b75d5f9e66b47 +Author: Roy Zang +Date: Fri Jan 9 16:00:55 2009 +0800 + + Fix IO port selection issue on MPC8544DS and MPC8572DS boards + + The IO port selection is not correct on MPC8572DS and MPC8544DS board. + This patch fixes this issue. + For MPC8572 + Port cfg_io_ports + PCIE1 0x2, 0x3, 0x7, 0xb, 0xc, 0xf + PCIE2 0x3, 0x7 + PCIE3 0x7 + + For MPC8544 + Port cfg_io_ports + PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 + PCIE2 0x4, 0x5, 0x6, 0x7 + PCIE3 0x6, 0x7 + Signed-off-by: Roy Zang + +commit 3e3fffe3baf3befde287fec1fcbfe55052fb8946 +Author: Becky Bruce +Date: Wed Dec 3 22:36:44 2008 -0600 + + mpc8610hpcd: Fix PCI mapping concepts + + Rename _BASE to _BUS, as it's actually a PCI bus address, + separate virtual and physical addresses into _VIRT and _PHYS, + and use each appopriately. This makes the code easier to read + and understand, and facilitates mapping changes going forward. + + Signed-off-by: Becky Bruce + +commit 79e436cad3b4a7db88408c3f05175028f30d700d +Author: Becky Bruce +Date: Wed Dec 3 22:36:26 2008 -0600 + + sbc8641d: Fix PCI mapping concepts + + Rename _BASE to _BUS, as it's actually a PCI bus address, + separate virtual and physical addresses into _VIRT and _PHYS, + and use each appopriately. This makes the code easier to read + and understand, and facilitates mapping changes going forward. + + Signed-off-by: Becky Bruce + +commit a9f3acbcd07da72b5446ce557531a3ed8b8beff0 +Author: Wolfgang Denk +Date: Mon Jan 12 14:50:35 2009 +0100 + + MPC86xx: fix build warnings + + Signed-off-by: Wolfgang Denk + +commit 032a1c934ef4dc003281f57302b6e693062c1868 +Author: Mike Frysinger +Date: Mon Jan 5 16:09:44 2009 -0500 + + bf537-stamp/nand: fix board_nand_init prototype + + The board_nand_init() function should return an int, not void. + + Signed-off-by: Mike Frysinger + +commit 687f952e4119594ab913be11c90f7f018c2a7a79 +Author: Mike Frysinger +Date: Thu Dec 11 07:04:48 2008 -0500 + + Blackfin: drop CONFIG_SPI handling in board init + + The eeprom SPI init functions are duplicated as the common code already + executes these for us. + + Signed-off-by: Mike Frysinger + +commit e7e684b10d73a303902208594c7c3e7e0d753282 +Author: Mike Frysinger +Date: Fri Oct 24 17:51:57 2008 -0400 + + Blackfin: fix out-of-tree building with ldscripts + + Many of the Blackfin board linker scripts are preprocessed, so make sure we + output the linker script into the build tree rather than the source tree. + + Signed-off-by: Mike Frysinger + +commit b9eecc342f767b50e1476fbc1aad7d88dd4ce5eb +Author: Mike Frysinger +Date: Fri Oct 24 17:48:54 2008 -0400 + + Blackfin: fix linker scripts to work with --gc-sections + + Make sure all .text sections get pulled in and the entry point is properly + referenced so they don't get discarded when linking with --gc-sections. + + Signed-off-by: Mike Frysinger + +commit 509fc553bc6087a6f705b3bf52f3950d7d1eaa58 +Author: Mike Frysinger +Date: Sat Oct 11 20:45:44 2008 -0400 + + Blackfin: set proper LDRFLAGS for parallel booting LDRs + + In order to boot an LDR out of parallel flash, the ldr utility needs a few + flags to tell it to generate the right header. + + Signed-off-by: Mike Frysinger + +commit 3dd9395a0d7ce69a335d0e743c04b9caedd681d3 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Tue Jan 6 21:41:59 2009 +0100 + + at91rm9200: move define from lowlevel_init to header + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 8a48686fac2030287765f1970ea046bd5734b733 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sat Jan 3 17:22:26 2009 +0100 + + m501sk: move to the common memory setup + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit d481c80d78f954133c035dae6c7d22de3625795d +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sat Jan 3 17:22:25 2009 +0100 + + at91rm9200: rename lowlevel init value to CONFIG_SYS_ + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 4e170b16625291aa10d0d9abc3f34e8a5945d157 +Author: Nicolas Ferre +Date: Tue Jan 6 21:13:14 2009 +0100 + + at91: add at91sam9xeek board support + + At91sam9xe is basically an at91sam9260 with embedded flash. We can manage + it as another entry for at91sam9260 in the Makefile. + + Check documentation at : + http://www.atmel.com/dyn/products/product_card.asp?part_id=4263 + + Signed-off-by: Nicolas Ferre + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 9ffd53db870a7da134f9a1ae76894a6b31237be5 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Tue Jan 6 21:15:57 2009 +0100 + + fix bmp_logo.h make dependencies to allow parallel build + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit e12d9a8fb48d24176efffccc072b445e60a3afe4 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sat Jan 3 17:22:24 2009 +0100 + + at91: Fix Atmel's at91sam9 boards out of tree build + + introduced in commit 89a7a87f084c + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + +commit 0668236bafaa1c11c521652a2facebc74beecbf0 +Author: Wolfgang Denk +Date: Tue Dec 30 22:56:11 2008 +0100 + + README: update mailing list name and hits to patch submission. + + Signed-off-by: Wolfgang Denk + +commit d9011f9b75561a0bd9254934c2bb2bc799d4f645 +Author: Peter Tyser +Date: Tue Dec 23 16:32:01 2008 -0600 + + 85xx: Enable inbound PCI config cycles for X-ES boards cleanup + + Signed-off-by: Peter Tyser + +commit 1f03cbfae221b24ba1341a0a3f62ff01c5c874df +Author: Peter Tyser +Date: Tue Dec 23 16:32:00 2008 -0600 + + XPedite5200 board support cleanup + + Signed-off-by: Peter Tyser + +commit fea91edee8ae0295e3c30b1ff544df51f4d668e1 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Tue Dec 2 21:58:04 2008 +0100 + + usb_kbd: fix usb_kbd_deregister when DEVICE_DEREGISTER not enable + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Remy Böhmer + +commit ada591d2a0ecff5f9bc5ed1ebf310f439c3d0a28 +Author: Trent Piepho +Date: Wed Dec 3 15:16:37 2008 -0800 + + mpc8[56]xx: Put localbus clock in sysinfo and gd + + Currently MPC85xx and MPC86xx boards just calculate the localbus frequency + and print it out, but don't save it. + + This changes where its calculated and stored to be more consistent with the + CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock. + + The localbus frequency is added to sysinfo and calculated when sysinfo is + set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are. + + get_clocks() copies the frequency into the global data, as the other + frequencies are, into a new field that is only enabled for MPC85xx and + MPC86xx. + + checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency + from sysinfo, like the other frequencies, instead of calculating it on the + spot. + + Signed-off-by: Trent Piepho + Acked-by: Kumar Gala + Acked-by: Jon Loeliger + +commit 9863d6aca11405e1e0d8aba2045d78aeec4d4ee7 +Author: Trent Piepho +Date: Wed Dec 3 15:16:36 2008 -0800 + + mpc86xx: Double local bus clock divider + + The local bus clock divider should be doubled for both 8610 and 8641. + + Signed-off-by: Trent Piepho + Acked-by: Kumar Gala + Acked-by: Jon Loeliger + +commit 446c381e3e16f19857b72ea0d06241267b8b9d58 +Author: Trent Piepho +Date: Wed Dec 3 15:16:35 2008 -0800 + + mpc8568: Double local bus clock divider + + The clock divider for the MPC8568 local bus should be doubled, like the + other newer MPC85xx chips. + + Since there are now more chips with a 2x divider than a 1x, and any new + 85xx chips will probably be 2x, invert the sense of the #if so that it + lists the 1x chips instead of the 2x ones. + + Signed-off-by: Trent Piepho + Acked-by: Kumar Gala + Acked-by: Jon Loeliger + +commit f51f07eb58fad12de9294ba4ee6c09a0ddeaee03 +Author: Dave Liu +Date: Tue Dec 16 12:09:27 2008 +0800 + + 85xx: Fix the boot window issue + + If one custom board is using the 8MB flash, it is set + as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000. + The current start.S code will be broken at switch_as. + + It is because the TLB1[15] is set as 16MB page size, + EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000. + + For the 8MB flash case, the EPN = 0xefxxxxxx, + RPN = 0xffxxxxxx. Assume the virt address of switch_as + is 0xef7ff18c, the real address of the instruction at + switch_as should be 0xff7ff18c. the 0xff7ff18c is out + of the range of the default 8MB boot LAW window + 0xff800000 - 0xffffffff. + + So when we switch to AS1 address space at switch_as, + the core can't fetch the instruction at switch_as any + more. It will cause broken issue. + + Signed-off-by: Dave Liu + +commit 58da8890d5fbd074746037722a423de9ac408616 +Author: Paul Gortmaker +Date: Thu Dec 11 15:47:50 2008 -0500 + + sbc8548: use proper PHY address + + The values given for the PHY address were wrong, so the code + read no valid PHY ID, and fell through to the generic PHY + support, which would work on 1000M but would not auto negotiate + down to 100M or 10M. + + Signed-off-by: Paul Gortmaker + +commit ad22f9273c6f24fbfa917e867680e9688e0c59c5 +Author: Paul Gortmaker +Date: Thu Dec 11 15:47:51 2008 -0500 + + sbc8548: enable command line editing by default. + + Lets make things a bit more user friendly. It isn't 1985 anymore. + + Signed-off-by: Paul Gortmaker + +commit bd93105fa171184a71ca8b22be03dc2705cfbd3f +Author: Paul Gortmaker +Date: Thu Dec 11 15:47:49 2008 -0500 + + sbc8548: don't enable the 3rd and 4th eTSEC + + These interfaces don't have usable connectors on the board, so don't + bother enumerating or configuring them. + + Signed-off-by: Paul Gortmaker + +commit 181a3650113883728927928b3ac81ad6dade4b2c +Author: Haiying Wang +Date: Wed Dec 3 10:08:19 2008 -0500 + + Set IVPR to kenrel entry point in second core boot page + + Assuming the OSes exception vectors start from the base of kernel address, and + the kernel physical starting address can be relocated to an non-zero address. + This patch enables the second core to have a valid IVPR for debugger before + kernel setting IVPR in CAMP mode. Otherwise, IVPR is 0x0 and it is not a valid + value for second core which runs kernel at different physical address other + than 0x0. + + Signed-off-by: Haiying Wang + +commit a5d212a263c58cc746481bf1fc878510533ce7d6 +Author: Trent Piepho +Date: Wed Dec 3 15:16:34 2008 -0800 + + mpc8xxx: LCRR[CLKDIV] is sometimes five bits + + On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits + instead of four. + + In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It + should be safe as the fifth bit was defined as reserved and set to 0. + + Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. + + Signed-off-by: Trent Piepho + Acked-by: Kumar Gala + Acked-by: Jon Loeliger + +commit 58ec4866ed916c7e422f5107bb27b0822084728e +Author: Trent Piepho +Date: Wed Dec 3 15:16:38 2008 -0800 + + mpc8[56]xx: Put localbus clock in device tree + + Export the localbus frequency in the device tree, the same way the CPU, TB, + CCB, and various other frequencies are exported in their respective device + tree nodes. + + Some localbus devices need this information to be programed correctly, so + it makes sense to export it along with the other frequencies. + + Unfortunately, when someone wrote the localbus dts bindings, they didn't + bother to define what the "compatible" property should be. So it seems no + one was quite sure what to put in their dts files. + + Based on current existing dts files in the kernel source, I've used + "fsl,pq3-localbus" and "fsl,elbc" for MPC85xx, which are used by almost all + of the 85xx devices, and are looked for by the Linux code. The eLBC is + apparently not entirely backward compatible with the pq3 LBC and so eLBC + equipped platforms like 8572 won't use pq3-localbus. + + For MPC86xx, I've used "fsl,elbc" which is used by some of the 86xx systems + and is also looked for by the Linux code. On MPC8641, I've also used + "fsl,mpc8641-localbus" as it is also commonly used in dts files, some of + which don't use "fsl,elbc" or any other acceptable name to match on. + + Signed-off-by: Trent Piepho + Acked-by: Kumar Gala + Acked-by: Jon Loeliger + +commit 9d94aff699eed38b286814fcbb335f3eb8516a0e +Author: Kumar Gala +Date: Tue Dec 16 14:59:22 2008 -0600 + + NAND FSL elbc: Use virt_to_phys to determine which bank is in use + + The current code that determines which bank/chipselect is used for a + given NAND instance only worked for 32-bit addresses and assumed + a 1:1 mapping. This breaks in 36-bit physical configs. + + The proper way to handle this is to use the virt_to_phys() and + BR_PHYS_ADDR() routinues to match the 34-bit lbc bus address + with the the virtual address the NAND code uses. + + Signed-off-by: Kumar Gala + Acked-by: Scott Wood + +commit 77c8115b1f1871811633eae77a5a700fac1f0e50 +Author: Kumar Gala +Date: Tue Dec 16 14:59:21 2008 -0600 + + ppc: Use addrmap in virt_to_phys and map_physmem. + + If we have addr map support enabled use the mapping functions to + implement virt_to_phys() and map_physmem(). + + Signed-off-by: Kumar Gala + +commit ecf5b98c7a6a2e2256dfddd48fab26678dcd6b90 +Author: Kumar Gala +Date: Tue Dec 16 14:59:20 2008 -0600 + + 85xx: Add support to populate addr map based on TLB settings + + Signed-off-by: Kumar Gala + +commit 78bbc5ce151c5a484bb51bf1866b4a993ffc16ec +Author: Peter Tyser +Date: Mon Dec 1 13:47:13 2008 -0600 + + XPedite5200 board support + + Initial support for Extreme Engineering Solutions XPedite5200 - + a MPC8548-based PMC single board computer. + + Signed-off-by: Peter Tyser + +commit 487dcb4fb89be0992bc06ec1341090017bd9cf2f +Author: Peter Tyser +Date: Wed Oct 29 12:39:27 2008 -0500 + + 85xx: Enable inbound PCI config cycles for X-ES boards + + Update X-ES Freescale boards to allow inbound PCI configuration + cycles when configured as agent/endpoint. + + Signed-off-by: Peter Tyser + +commit ccf0fdd02b97323f8caae18d06cc9daeac2f192f +Author: Peter Tyser +Date: Wed Dec 17 16:36:23 2008 -0600 + + XPedite5370 board support + + Initial support for Extreme Engineering Solutions XPedite5370 - + a MPC8572-based 3U VPX single board computer with a PMC/XMC + site. + + Signed-off-by: Peter Tyser + +commit e92739d34e2d6b6aca93b2598248210710897ce8 +Author: Peter Tyser +Date: Wed Dec 17 16:36:21 2008 -0600 + + Add support for PCA953x I2C gpio devices + + Initial support for NXP's 4 and 8 bit I2C gpio expanders + (eg pca9537, pca9557, etc). The CONFIG_PCA953X define + enables support for the devices while the CONFIG_CMD_PCA953X + define enables the pca953x command. The CONFIG_CMD_PCA953X_INFO + define enables an 'info' sub-command which provides summary + information for the given pca953x device. + + Signed-off-by: Peter Tyser + +commit 7a8979591171676417ab36852d8811a8c46accd8 +Author: Peter Tyser +Date: Wed Oct 29 12:39:26 2008 -0500 + + pci/fsl_pci_init: Enable inbound PCI config cycles + + Add fsl_pci_config_unlock() function to enable a + PCI/PCIe interface configured in agent/endpoint mode to + respond to inbound PCI configuration cycles. + + Signed-off-by: Peter Tyser + +commit b616f2b545f73757669b37386f0b37bb61fc6797 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Mon Sep 8 22:27:18 2008 +0200 + + MIPS: qemu_mips: update doc to generate and to use qemu flash, ide file + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Shinya Kuribayashi + +commit 16cdf816779f5b602a9b3b4d2ea4dea05095c35b +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Tue Dec 16 22:10:31 2008 +0100 + + MIPS: qemu_mips: update doc to use all disk and boot linux kernel + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Shinya Kuribayashi + +commit 13095b2f07dacb1f863772266c1789d47a523a8a +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Tue Dec 16 22:10:30 2008 +0100 + + MIPS: qemu_mips: move env storage just after u-boot + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Shinya Kuribayashi + +commit aced78d852d0b009e8aaa1445af8cb40861ee549 +Author: Wolfgang Denk +Date: Tue Dec 16 23:48:27 2008 +0100 + + Prepare 2009.01-rc1 + + Signed-off-by: Wolfgang Denk + commit 9e2a79b4c585ad31138fb90b68fd0234d64a8da8 Author: Wolfgang Denk Date: Tue Dec 16 23:13:46 2008 +0100 @@ -21,6 +597,18 @@ Date: Tue Dec 16 22:32:25 2008 +0100 Signed-off-by: Wolfgang Denk +commit ff49ea8977b56916edd5b1766d9939010e30b181 +Author: Scott Wood +Date: Tue Dec 16 14:24:16 2008 -0600 + + NAND: Mark the BBT as scanned prior to calling scan_bbt. + + Otherwise, recursion can occur if scan_bbt does not find a bad block + table, and tries to write one, and the attempt to erase the BBT area + causes a bad block check. + + Signed-off-by: Scott Wood + commit 584eedab66d0828f2d571a24b10526c4e65f547b Author: Ilya Yanok Date: Thu Dec 11 05:51:57 2008 +0300 From 1e15ff999322e81af4c0c0c548908f38944ba39c Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 20 Dec 2008 15:25:22 +0100 Subject: [PATCH 107/188] sh: update sh timer coding style Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nobuhiro Iwamatsu --- lib_sh/time.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/lib_sh/time.c b/lib_sh/time.c index 2bd771528..8fccce3d6 100644 --- a/lib_sh/time.c +++ b/lib_sh/time.c @@ -49,21 +49,21 @@ int timer_init (void) { /* Divide clock by TMU_CLK_DIVIDER */ u16 bit = 0; - switch( TMU_CLK_DIVIDER ){ - case 4: - bit = 0; - break; - case 16: - bit = 1; - break; - case 64: bit = 2; + + switch (TMU_CLK_DIVIDER) { + case 1024: + bit = 4; break; case 256: bit = 3; break; - case 1024: - bit = 4; + case 64: + bit = 2; break; + case 16: + bit = 1; + break; + case 4: default: bit = 0; break; @@ -71,7 +71,7 @@ int timer_init (void) writew(readw(TCR0) | bit, TCR0); /* Clock adjustment calc */ - clk_adj = (int)(1.0/((1.0/CONFIG_SYS_HZ)*1000000)); + clk_adj = (int)(1.0 / ((1.0 / CONFIG_SYS_HZ) * 1000000)); if (clk_adj < 1) clk_adj = 1; @@ -102,8 +102,8 @@ void udelay (unsigned long usec) unsigned long get_timer (unsigned long base) { - /* return msec */ - return ((get_usec()/clk_adj)/1000) - base; + /* return msec */ + return ((get_usec() / clk_adj) / 1000) - base; } void set_timer (unsigned long t) From 85cb052ee41675ca361e6a4c69455dc715c8f2d9 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 20 Dec 2008 15:27:45 +0100 Subject: [PATCH 108/188] sh: update sh2/sh2a timer coding style Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nobuhiro Iwamatsu --- lib_sh/time_sh2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib_sh/time_sh2.c b/lib_sh/time_sh2.c index 4f893c87b..5c6c9d438 100644 --- a/lib_sh/time_sh2.c +++ b/lib_sh/time_sh2.c @@ -28,7 +28,7 @@ #include #include -#define CMT_CMCSR_INIT 0x0001 /* PCLK/32 */ +#define CMT_CMCSR_INIT 0x0001 /* PCLK/32 */ #define CMT_CMCSR_CALIB 0x0000 #define CMT_MAX_COUNTER (0xFFFFFFFF) #define CMT_TIMER_RESET (0xFFFF) @@ -87,7 +87,7 @@ static unsigned long get_usec (void) /* return msec */ ulong get_timer(ulong base) { - return (get_usec()/1000) - base; + return (get_usec() / 1000) - base; } void set_timer(ulong t) From e4430779623af500de1cee7892c379f07ef59813 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 20 Dec 2008 19:29:48 +0100 Subject: [PATCH 109/188] sh: lowlevel_init coding style cleanup Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nobuhiro Iwamatsu --- board/mpr2/lowlevel_init.S | 44 ++- board/ms7722se/lowlevel_init.S | 34 +- board/ms7750se/lowlevel_init.S | 150 ++++---- board/renesas/MigoR/lowlevel_init.S | 10 +- board/renesas/ap325rxa/lowlevel_init.S | 86 ++--- board/renesas/r2dplus/lowlevel_init.S | 126 +++---- board/renesas/r7780mp/lowlevel_init.S | 438 ++++++++++++------------ board/renesas/rsk7203/lowlevel_init.S | 214 ++++++------ board/renesas/sh7763rdp/lowlevel_init.S | 162 ++++----- board/renesas/sh7785lcr/lowlevel_init.S | 2 +- 10 files changed, 636 insertions(+), 630 deletions(-) diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S index 060957ad0..187b5bbeb 100644 --- a/board/mpr2/lowlevel_init.S +++ b/board/mpr2/lowlevel_init.S @@ -33,17 +33,17 @@ lowlevel_init: /* * Set frequency multipliers and dividers in FRQCR. */ - mov.l WTCSR_A,r1 - mov.l WTCSR_D,r0 - mov.w r0,@r1 + mov.l WTCSR_A, r1 + mov.l WTCSR_D, r0 + mov.w r0, @r1 - mov.l WTCNT_A,r1 - mov.l WTCNT_D,r0 - mov.w r0,@r1 + mov.l WTCNT_A, r1 + mov.l WTCNT_D, r0 + mov.w r0, @r1 - mov.l FRQCR_A,r1 - mov.l FRQCR_D,r0 - mov.w r0,@r1 + mov.l FRQCR_A, r1 + mov.l FRQCR_D, r0 + mov.w r0, @r1 /* * Setup CS0 (Flash). @@ -112,21 +112,27 @@ WTCSR_D: .long 0xA507 /* divide by 4096 */ /* * Spansion S29GL256N11 @ 48 MHz */ -CS0BCR_D: .long 0x12490400 /* 1 idle cycle inserted, normal space, 16 bit */ -CS0WCR_D: .long 0x00000340 /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */ +/* 1 idle cycle inserted, normal space, 16 bit */ +CS0BCR_D: .long 0x12490400 +/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */ +CS0WCR_D: .long 0x00000340 /* * Samsung K4S511632B-UL75 @ 48 MHz * Micron MT48LC32M16A2-75 @ 48 MHz */ -CS3BCR_D: .long 0x10004400 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */ -CS3WCR_D: .long 0x00000091 /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */ -SDCR_D1: .long 0x00000012 /* no refresh, 13 rows, 10 cols, NO bank active mode */ -SDCR_D2: .long 0x00000812 /* refresh */ -RTCSR_D: .long 0xA55A0008 /* 1/4, once */ -RTCNT_D: .long 0xA55A005D /* count 93 */ -RTCOR_D: .long 0xa55a005d /* count 93 */ -SDMR3_D: .long 0x440 /* mode register CL2, burst read and SINGLE WRITE */ +/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */ +CS3BCR_D: .long 0x10004400 +/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */ +CS3WCR_D: .long 0x00000091 +/* no refresh, 13 rows, 10 cols, NO bank active mode */ +SDCR_D1: .long 0x00000012 +SDCR_D2: .long 0x00000812 /* refresh */ +RTCSR_D: .long 0xA55A0008 /* 1/4, once */ +RTCNT_D: .long 0xA55A005D /* count 93 */ +RTCOR_D: .long 0xa55a005d /* count 93 */ +/* mode register CL2, burst read and SINGLE WRITE */ +SDMR3_D: .long 0x440 /* * Registers diff --git a/board/ms7722se/lowlevel_init.S b/board/ms7722se/lowlevel_init.S index 8b46595f3..3e887cfe8 100644 --- a/board/ms7722se/lowlevel_init.S +++ b/board/ms7722se/lowlevel_init.S @@ -29,11 +29,11 @@ #include /* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. * - * (Note: As no stack is available, no subroutines can be called...). + * (Note: As no stack is available, no subroutines can be called...). */ .global lowlevel_init @@ -203,7 +203,7 @@ bsc_init: mov #0x00, r0 ! SDMR3 data -> R0 mov.b r0, @r1 ! SDMR3 set - ! BL bit off (init = ON) (?!?) + ! BL bit off (init = ON) (?!?) stc sr, r0 ! BL bit off(init=ON) mov.l SR_MASK_D, r1 @@ -232,28 +232,28 @@ MSTPCR0_D: .long 0x00001001 MSTPCR2_D: .long 0xffffffff FRQCR_D: .long 0x07022538 -PSELA_A: .long 0xa405014E -PSELA_D: .word 0x0A10 +PSELA_A: .long 0xa405014E +PSELA_D: .word 0x0A10 .align 2 -DRVCR_A: .long 0xa405018A -DRVCR_D: .word 0x0554 +DRVCR_A: .long 0xa405018A +DRVCR_D: .word 0x0554 .align 2 -PCCR_A: .long 0xa4050104 -PCCR_D: .word 0x8800 +PCCR_A: .long 0xa4050104 +PCCR_D: .word 0x8800 .align 2 -PECR_A: .long 0xa4050108 -PECR_D: .word 0x0000 +PECR_A: .long 0xa4050108 +PECR_D: .word 0x0000 .align 2 -PJCR_A: .long 0xa4050110 -PJCR_D: .word 0x1000 +PJCR_A: .long 0xa4050110 +PJCR_D: .word 0x1000 .align 2 -PXCR_A: .long 0xa4050148 -PXCR_D: .word 0x0AAA +PXCR_A: .long 0xa4050148 +PXCR_D: .word 0x0AAA .align 2 CMNCR_A: .long CMNCR diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S index d3e3cd5e8..de05dd9ee 100644 --- a/board/ms7750se/lowlevel_init.S +++ b/board/ms7750se/lowlevel_init.S @@ -31,118 +31,118 @@ #include #ifdef CONFIG_CPU_SH7751 -#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ -#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ +#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ +#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ #ifdef CONFIG_MARUBUN_PCCARD -#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 - A3:2 A2:15 A1:15 A0:6 A0B:7 */ +#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 + A3:2 A2:15 A1:15 A0:6 A0B:7 */ #else /* CONFIG_MARUBUN_PCCARD */ -#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 - A3:2 A2:15 A1:15 A0:6 A0B:7 */ +#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 + A3:2 A2:15 A1:15 A0:6 A0B:7 */ #endif /* CONFIG_MARUBUN_PCCARD */ -#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 - A2: 1-3 A1: 1-3 A0: 0-1 */ -#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ -#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ -#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */ -#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ +#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 + A2: 1-3 A1: 1-3 A0: 0-1 */ +#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ +#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ +#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */ +#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ #else /* CONFIG_CPU_SH7751 */ -#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ -#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ -#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 - A3:2 A2:15 A1:15 A0:15 A0B:7 */ -#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 - A2: 1-3 A1: 1-3 A0: 0-1 */ -#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ -#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ -#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */ -#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ +#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ +#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ +#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 + A3:2 A2:15 A1:15 A0:15 A0B:7 */ +#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 + A2: 1-3 A1: 1-3 A0: 0-1 */ +#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ +#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ +#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */ +#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ #endif /* CONFIG_CPU_SH7751 */ .global lowlevel_init .text - .align 2 + .align 2 lowlevel_init: - mov.l CCR_A, r1 ! CCR Address - mov.l CCR_D_DISABLE, r0 ! CCR Data - mov.l r0, @r1 + mov.l CCR_A, r1 ! CCR Address + mov.l CCR_D_DISABLE, r0 ! CCR Data + mov.l r0, @r1 init_bsc: - mov.l FRQCR_A,r1 /* FRQCR Address */ - mov.l FRQCR_D,r0 /* FRQCR Data */ - mov.w r0,@r1 + mov.l FRQCR_A, r1 /* FRQCR Address */ + mov.l FRQCR_D, r0 /* FRQCR Data */ + mov.w r0, @r1 - mov.l BCR1_A,r1 /* BCR1 Address */ - mov.l BCR1_D,r0 /* BCR1 Data */ - mov.l r0,@r1 + mov.l BCR1_A, r1 /* BCR1 Address */ + mov.l BCR1_D, r0 /* BCR1 Data */ + mov.l r0, @r1 - mov.l BCR2_A,r1 /* BCR2 Address */ - mov.l BCR2_D,r0 /* BCR2 Data */ - mov.w r0,@r1 + mov.l BCR2_A, r1 /* BCR2 Address */ + mov.l BCR2_D, r0 /* BCR2 Data */ + mov.w r0, @r1 - mov.l WCR1_A,r1 /* WCR1 Address */ - mov.l WCR1_D,r0 /* WCR1 Data */ - mov.l r0,@r1 + mov.l WCR1_A, r1 /* WCR1 Address */ + mov.l WCR1_D, r0 /* WCR1 Data */ + mov.l r0, @r1 - mov.l WCR2_A,r1 /* WCR2 Address */ - mov.l WCR2_D,r0 /* WCR2 Data */ - mov.l r0,@r1 + mov.l WCR2_A, r1 /* WCR2 Address */ + mov.l WCR2_D, r0 /* WCR2 Data */ + mov.l r0, @r1 - mov.l WCR3_A,r1 /* WCR3 Address */ - mov.l WCR3_D,r0 /* WCR3 Data */ - mov.l r0,@r1 + mov.l WCR3_A, r1 /* WCR3 Address */ + mov.l WCR3_D, r0 /* WCR3 Data */ + mov.l r0, @r1 - mov.l MCR_A,r1 /* MCR Address */ - mov.l MCR_D1,r0 /* MCR Data1 */ - mov.l r0,@r1 + mov.l MCR_A, r1 /* MCR Address */ + mov.l MCR_D1, r0 /* MCR Data1 */ + mov.l r0, @r1 - mov.l SDMR3_A,r1 /* Set SDRAM mode */ - mov #0,r0 - mov.b r0,@r1 + mov.l SDMR3_A, r1 /* Set SDRAM mode */ + mov #0, r0 + mov.b r0, @r1 ! Do you need PCMCIA setting? ! If so, please add the lines here... - mov.l RTCNT_A,r1 /* RTCNT Address */ - mov.l RTCNT_D,r0 /* RTCNT Data */ - mov.w r0,@r1 + mov.l RTCNT_A, r1 /* RTCNT Address */ + mov.l RTCNT_D, r0 /* RTCNT Data */ + mov.w r0, @r1 - mov.l RTCOR_A,r1 /* RTCOR Address */ - mov.l RTCOR_D,r0 /* RTCOR Data */ - mov.w r0,@r1 + mov.l RTCOR_A, r1 /* RTCOR Address */ + mov.l RTCOR_D, r0 /* RTCOR Data */ + mov.w r0, @r1 - mov.l RTCSR_A,r1 /* RTCSR Address */ - mov.l RTCSR_D,r0 /* RTCSR Data */ - mov.w r0,@r1 + mov.l RTCSR_A, r1 /* RTCSR Address */ + mov.l RTCSR_D, r0 /* RTCSR Data */ + mov.w r0, @r1 - mov.l RFCR_A,r1 /* RFCR Address */ - mov.l RFCR_D,r0 /* RFCR Data */ - mov.w r0,@r1 /* Clear reflesh counter */ + mov.l RFCR_A, r1 /* RFCR Address */ + mov.l RFCR_D, r0 /* RFCR Data */ + mov.w r0, @r1 /* Clear reflesh counter */ /* Wait DRAM refresh 30 times */ - mov #30,r3 + mov #30, r3 1: - mov.w @r1,r0 - extu.w r0,r2 - cmp/hi r3,r2 + mov.w @r1, r0 + extu.w r0, r2 + cmp/hi r3, r2 bf 1b - mov.l MCR_A,r1 /* MCR Address */ - mov.l MCR_D2,r0 /* MCR Data2 */ - mov.l r0,@r1 + mov.l MCR_A, r1 /* MCR Address */ + mov.l MCR_D2, r0 /* MCR Data2 */ + mov.l r0, @r1 - mov.l SDMR3_A,r1 /* Set SDRAM mode */ - mov #0,r0 - mov.b r0,@r1 + mov.l SDMR3_A, r1 /* Set SDRAM mode */ + mov #0, r0 + mov.b r0, @r1 rts - nop + nop .align 2 -CCR_A: .long CCR -CCR_D_DISABLE: .long 0x0808 +CCR_A: .long CCR +CCR_D_DISABLE: .long 0x0808 FRQCR_A: .long FRQCR FRQCR_D: #ifdef CONFIG_CPU_TYPE_R diff --git a/board/renesas/MigoR/lowlevel_init.S b/board/renesas/MigoR/lowlevel_init.S index 4c1900ec2..13c83bf8c 100644 --- a/board/renesas/MigoR/lowlevel_init.S +++ b/board/renesas/MigoR/lowlevel_init.S @@ -29,11 +29,11 @@ #include /* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. * - * (Note: As no stack is available, no subroutines can be called...). + * (Note: As no stack is available, no subroutines can be called...). */ .global lowlevel_init @@ -176,7 +176,7 @@ bsc_init: mov #0x00, r0 ! SDMR3 data -> R0 mov.b r0, @r1 ! SDMR3 set - ! BL bit off (init = ON) (?!?) + ! BL bit off (init = ON) (?!?) stc sr, r0 ! BL bit off(init=ON) mov.l SR_MASK_D, r1 diff --git a/board/renesas/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S index 4f6658879..558e7793e 100644 --- a/board/renesas/ap325rxa/lowlevel_init.S +++ b/board/renesas/ap325rxa/lowlevel_init.S @@ -39,111 +39,111 @@ lowlevel_init: mov.l DRVCRA_A, r1 - mov.l DRVCRA_D, r0 + mov.l DRVCRA_D, r0 mov.w r0, @r1 mov.l DRVCRB_A, r1 - mov.l DRVCRB_D, r0 + mov.l DRVCRB_D, r0 mov.w r0, @r1 mov.l RWTCSR_A, r1 - mov.l RWTCSR_D1, r0 + mov.l RWTCSR_D1, r0 mov.w r0, @r1 mov.l RWTCNT_A, r1 - mov.l RWTCNT_D, r0 + mov.l RWTCNT_D, r0 mov.w r0, @r1 mov.l RWTCSR_A, r1 - mov.l RWTCSR_D2, r0 + mov.l RWTCSR_D2, r0 mov.w r0, @r1 mov.l FRQCR_A, r1 - mov.l FRQCR_D, r0 + mov.l FRQCR_D, r0 mov.l r0, @r1 mov.l CMNCR_A, r1 mov.l CMNCR_D, r0 mov.l r0, @r1 - mov.l CS0BCR_A ,r1 - mov.l CS0BCR_D ,r0 + mov.l CS0BCR_A, r1 + mov.l CS0BCR_D, r0 mov.l r0, @r1 - mov.l CS4BCR_A ,r1 - mov.l CS4BCR_D ,r0 + mov.l CS4BCR_A, r1 + mov.l CS4BCR_D, r0 mov.l r0, @r1 - mov.l CS5ABCR_A ,r1 - mov.l CS5ABCR_D ,r0 + mov.l CS5ABCR_A, r1 + mov.l CS5ABCR_D, r0 mov.l r0, @r1 - mov.l CS5BBCR_A ,r1 - mov.l CS5BBCR_D ,r0 + mov.l CS5BBCR_A, r1 + mov.l CS5BBCR_D, r0 mov.l r0, @r1 - mov.l CS6ABCR_A ,r1 - mov.l CS6ABCR_D ,r0 + mov.l CS6ABCR_A, r1 + mov.l CS6ABCR_D, r0 mov.l r0, @r1 - mov.l CS6BBCR_A ,r1 - mov.l CS6BBCR_D ,r0 + mov.l CS6BBCR_A, r1 + mov.l CS6BBCR_D, r0 mov.l r0, @r1 - mov.l CS0WCR_A ,r1 - mov.l CS0WCR_D ,r0 + mov.l CS0WCR_A, r1 + mov.l CS0WCR_D, r0 mov.l r0, @r1 - mov.l CS4WCR_A ,r1 - mov.l CS4WCR_D ,r0 + mov.l CS4WCR_A, r1 + mov.l CS4WCR_D, r0 mov.l r0, @r1 - mov.l CS5AWCR_A ,r1 - mov.l CS5AWCR_D ,r0 + mov.l CS5AWCR_A, r1 + mov.l CS5AWCR_D, r0 mov.l r0, @r1 - mov.l CS5BWCR_A ,r1 - mov.l CS5BWCR_D ,r0 + mov.l CS5BWCR_A, r1 + mov.l CS5BWCR_D, r0 mov.l r0, @r1 - mov.l CS6AWCR_A ,r1 - mov.l CS6AWCR_D ,r0 + mov.l CS6AWCR_A, r1 + mov.l CS6AWCR_D, r0 mov.l r0, @r1 - mov.l CS6BWCR_A ,r1 - mov.l CS6BWCR_D ,r0 + mov.l CS6BWCR_A, r1 + mov.l CS6BWCR_D, r0 mov.l r0, @r1 mov.l SBSC_SDCR_A, r1 - mov.l SBSC_SDCR_D1, r0 + mov.l SBSC_SDCR_D1, r0 mov.l r0, @r1 mov.l SBSC_SDWCR_A, r1 - mov.l SBSC_SDWCR_D, r0 + mov.l SBSC_SDWCR_D, r0 mov.l r0, @r1 mov.l SBSC_SDPCR_A, r1 - mov.l SBSC_SDPCR_D, r0 + mov.l SBSC_SDPCR_D, r0 mov.l r0, @r1 mov.l SBSC_RTCSR_A, r1 - mov.l SBSC_RTCSR_D, r0 + mov.l SBSC_RTCSR_D, r0 mov.l r0, @r1 mov.l SBSC_RTCNT_A, r1 - mov.l SBSC_RTCNT_D, r0 + mov.l SBSC_RTCNT_D, r0 mov.l r0, @r1 mov.l SBSC_RTCOR_A, r1 - mov.l SBSC_RTCOR_D, r0 + mov.l SBSC_RTCOR_D, r0 mov.l r0, @r1 mov.l SBSC_SDMR3_A1, r1 - mov.l SBSC_SDMR3_D, r0 + mov.l SBSC_SDMR3_D, r0 mov.b r0, @r1 mov.l SBSC_SDMR3_A2, r1 - mov.l SBSC_SDMR3_D, r0 + mov.l SBSC_SDMR3_D, r0 mov.b r0, @r1 mov.l SLEEP_CNT, r1 @@ -153,18 +153,18 @@ lowlevel_init: dt r1 mov.l SBSC_SDMR3_A3, r1 - mov.l SBSC_SDMR3_D, r0 + mov.l SBSC_SDMR3_D, r0 mov.b r0, @r1 mov.l SBSC_SDCR_A, r1 - mov.l SBSC_SDCR_D2, r0 + mov.l SBSC_SDCR_D2, r0 mov.l r0, @r1 mov.l CCR_A, r1 - mov.l CCR_D, r0 + mov.l CCR_D, r0 mov.l r0, @r1 - ! BL bit off (init = ON) (?!?) + ! BL bit off (init = ON) (?!?) stc sr, r0 ! BL bit off(init=ON) mov.l SR_MASK_D, r1 @@ -211,7 +211,7 @@ SBSC_SDMR3_D: .long 0x00 CMNCR_A: .long CMNCR CS0BCR_A: .long CS0BCR CS4BCR_A: .long CS4BCR -CS5ABCR_A: .long CS5ABCR +CS5ABCR_A: .long CS5ABCR CS5BBCR_A: .long CS5BBCR CS6ABCR_A: .long CS6ABCR CS6BBCR_A: .long CS6BBCR diff --git a/board/renesas/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S index 28d2b3769..a0573708d 100644 --- a/board/renesas/r2dplus/lowlevel_init.S +++ b/board/renesas/r2dplus/lowlevel_init.S @@ -17,92 +17,92 @@ lowlevel_init: mov.l CCR_A, r1 mov.l CCR_D_D, r0 - mov.l r0,@r1 + mov.l r0, @r1 - mov.l MMUCR_A,r1 - mov.l MMUCR_D,r0 - mov.l r0,@r1 + mov.l MMUCR_A, r1 + mov.l MMUCR_D, r0 + mov.l r0, @r1 - mov.l BCR1_A,r1 - mov.l BCR1_D,r0 - mov.l r0,@r1 + mov.l BCR1_A, r1 + mov.l BCR1_D, r0 + mov.l r0, @r1 - mov.l BCR2_A,r1 - mov.l BCR2_D,r0 - mov.w r0,@r1 + mov.l BCR2_A, r1 + mov.l BCR2_D, r0 + mov.w r0, @r1 - mov.l BCR3_A,r1 - mov.l BCR3_D,r0 - mov.w r0,@r1 + mov.l BCR3_A, r1 + mov.l BCR3_D, r0 + mov.w r0, @r1 - mov.l BCR4_A,r1 - mov.l BCR4_D,r0 - mov.l r0,@r1 + mov.l BCR4_A, r1 + mov.l BCR4_D, r0 + mov.l r0, @r1 - mov.l WCR1_A,r1 - mov.l WCR1_D,r0 - mov.l r0,@r1 + mov.l WCR1_A, r1 + mov.l WCR1_D, r0 + mov.l r0, @r1 - mov.l WCR2_A,r1 - mov.l WCR2_D,r0 - mov.l r0,@r1 + mov.l WCR2_A, r1 + mov.l WCR2_D, r0 + mov.l r0, @r1 - mov.l WCR3_A,r1 - mov.l WCR3_D,r0 - mov.l r0,@r1 + mov.l WCR3_A, r1 + mov.l WCR3_D, r0 + mov.l r0, @r1 - mov.l PCR_A,r1 - mov.l PCR_D,r0 - mov.w r0,@r1 + mov.l PCR_A, r1 + mov.l PCR_D, r0 + mov.w r0, @r1 - mov.l LED_A,r1 - mov #0xff,r0 - mov.w r0,@r1 + mov.l LED_A, r1 + mov #0xff, r0 + mov.w r0, @r1 - mov.l MCR_A,r1 - mov.l MCR_D1,r0 - mov.l r0,@r1 + mov.l MCR_A, r1 + mov.l MCR_D1, r0 + mov.l r0, @r1 - mov.l RTCNT_A,r1 - mov.l RTCNT_D,r0 - mov.w r0,@r1 + mov.l RTCNT_A, r1 + mov.l RTCNT_D, r0 + mov.w r0, @r1 - mov.l RTCOR_A,r1 - mov.l RTCOR_D,r0 - mov.w r0,@r1 + mov.l RTCOR_A, r1 + mov.l RTCOR_D, r0 + mov.w r0, @r1 - mov.l RFCR_A,r1 - mov.l RFCR_D,r0 - mov.w r0,@r1 + mov.l RFCR_A, r1 + mov.l RFCR_D, r0 + mov.w r0, @r1 - mov.l RTCSR_A,r1 - mov.l RTCSR_D,r0 - mov.w r0,@r1 + mov.l RTCSR_A, r1 + mov.l RTCSR_D, r0 + mov.w r0, @r1 - mov.l SDMR3_A,r1 - mov #0x55,r0 - mov.b r0,@r1 + mov.l SDMR3_A, r1 + mov #0x55, r0 + mov.b r0, @r1 /* Wait DRAM refresh 30 times */ - mov.l RFCR_A,r1 - mov #30,r3 + mov.l RFCR_A, r1 + mov #30, r3 1: - mov.w @r1,r0 - extu.w r0,r2 - cmp/hi r3,r2 + mov.w @r1, r0 + extu.w r0, r2 + cmp/hi r3, r2 bf 1b - mov.l MCR_A,r1 - mov.l MCR_D2,r0 - mov.l r0,@r1 + mov.l MCR_A, r1 + mov.l MCR_D2, r0 + mov.l r0, @r1 - mov.l SDMR3_A,r1 - mov #0,r0 - mov.b r0,@r1 + mov.l SDMR3_A, r1 + mov #0, r0 + mov.b r0, @r1 - mov.l IRLMASK_A,r1 - mov.l IRLMASK_D,r0 - mov.l r0,@r1 + mov.l IRLMASK_A, r1 + mov.l IRLMASK_D, r0 + mov.l r0, @r1 mov.l CCR_A, r1 mov.l CCR_D_E, r0 diff --git a/board/renesas/r7780mp/lowlevel_init.S b/board/renesas/r7780mp/lowlevel_init.S index ab0499a3a..0df8c8410 100644 --- a/board/renesas/r7780mp/lowlevel_init.S +++ b/board/renesas/r7780mp/lowlevel_init.S @@ -24,11 +24,11 @@ #include /* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. * - * (Note: As no stack is available, no subroutines can be called...). + * (Note: As no stack is available, no subroutines can be called...). */ .global lowlevel_init @@ -47,54 +47,54 @@ lowlevel_init: mov.l r0, @r1 /* pin_multi_setting */ - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSR1,r0 - mov.l r0,@r1 + mov.l BBG_PMMR_A, r1 + mov.l BBG_PMMR_D_PMSR1, r0 + mov.l r0, @r1 - mov.l BBG_PMSR1_A,r1 - mov.l BBG_PMSR1_D,r0 - mov.l r0,@r1 + mov.l BBG_PMSR1_A, r1 + mov.l BBG_PMSR1_D, r0 + mov.l r0, @r1 - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSR2,r0 - mov.l r0,@r1 + mov.l BBG_PMMR_A, r1 + mov.l BBG_PMMR_D_PMSR2, r0 + mov.l r0, @r1 - mov.l BBG_PMSR2_A,r1 - mov.l BBG_PMSR2_D,r0 - mov.l r0,@r1 + mov.l BBG_PMSR2_A, r1 + mov.l BBG_PMSR2_D, r0 + mov.l r0, @r1 - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSR3,r0 - mov.l r0,@r1 + mov.l BBG_PMMR_A, r1 + mov.l BBG_PMMR_D_PMSR3, r0 + mov.l r0, @r1 - mov.l BBG_PMSR3_A,r1 - mov.l BBG_PMSR3_D,r0 - mov.l r0,@r1 + mov.l BBG_PMSR3_A, r1 + mov.l BBG_PMSR3_D, r0 + mov.l r0, @r1 - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSR4,r0 - mov.l r0,@r1 + mov.l BBG_PMMR_A, r1 + mov.l BBG_PMMR_D_PMSR4, r0 + mov.l r0, @r1 - mov.l BBG_PMSR4_A,r1 - mov.l BBG_PMSR4_D,r0 - mov.l r0,@r1 + mov.l BBG_PMSR4_A, r1 + mov.l BBG_PMSR4_D, r0 + mov.l r0, @r1 - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSRG,r0 - mov.l r0,@r1 + mov.l BBG_PMMR_A, r1 + mov.l BBG_PMMR_D_PMSRG, r0 + mov.l r0, @r1 - mov.l BBG_PMSRG_A,r1 - mov.l BBG_PMSRG_D,r0 - mov.l r0,@r1 + mov.l BBG_PMSRG_A, r1 + mov.l BBG_PMSRG_D, r0 + mov.l r0, @r1 /* cpg_setting */ - mov.l FRQCR_A,r1 - mov.l FRQCR_D,r0 - mov.l r0,@r1 + mov.l FRQCR_A, r1 + mov.l FRQCR_D, r0 + mov.l r0, @r1 - mov.l DLLCSR_A,r1 - mov.l DLLCSR_D,r0 - mov.l r0,@r1 + mov.l DLLCSR_A, r1 + mov.l DLLCSR_D, r0 + mov.l r0, @r1 nop nop @@ -108,111 +108,111 @@ lowlevel_init: nop /* wait 200us */ - mov.l REPEAT0_R3,r3 - mov #0,r2 + mov.l REPEAT0_R3, r3 + mov #0, r2 repeat0: - add #1,r2 - cmp/hs r3,r2 - bf repeat0 + add #1, r2 + cmp/hs r3, r2 + bf repeat0 nop /* bsc_setting */ - mov.l MMSELR_A,r1 - mov.l MMSELR_D,r0 - mov.l r0,@r1 + mov.l MMSELR_A, r1 + mov.l MMSELR_D, r0 + mov.l r0, @r1 - mov.l BCR_A,r1 - mov.l BCR_D,r0 - mov.l r0,@r1 + mov.l BCR_A, r1 + mov.l BCR_D, r0 + mov.l r0, @r1 - mov.l CS0BCR_A,r1 - mov.l CS0BCR_D,r0 - mov.l r0,@r1 + mov.l CS0BCR_A, r1 + mov.l CS0BCR_D, r0 + mov.l r0, @r1 - mov.l CS1BCR_A,r1 - mov.l CS1BCR_D,r0 - mov.l r0,@r1 + mov.l CS1BCR_A, r1 + mov.l CS1BCR_D, r0 + mov.l r0, @r1 - mov.l CS2BCR_A,r1 - mov.l CS2BCR_D,r0 - mov.l r0,@r1 + mov.l CS2BCR_A, r1 + mov.l CS2BCR_D, r0 + mov.l r0, @r1 - mov.l CS4BCR_A,r1 - mov.l CS4BCR_D,r0 - mov.l r0,@r1 + mov.l CS4BCR_A, r1 + mov.l CS4BCR_D, r0 + mov.l r0, @r1 - mov.l CS5BCR_A,r1 - mov.l CS5BCR_D,r0 - mov.l r0,@r1 + mov.l CS5BCR_A, r1 + mov.l CS5BCR_D, r0 + mov.l r0, @r1 - mov.l CS6BCR_A,r1 - mov.l CS6BCR_D,r0 - mov.l r0,@r1 + mov.l CS6BCR_A, r1 + mov.l CS6BCR_D, r0 + mov.l r0, @r1 - mov.l CS0WCR_A,r1 - mov.l CS0WCR_D,r0 - mov.l r0,@r1 + mov.l CS0WCR_A, r1 + mov.l CS0WCR_D, r0 + mov.l r0, @r1 - mov.l CS1WCR_A,r1 - mov.l CS1WCR_D,r0 - mov.l r0,@r1 + mov.l CS1WCR_A, r1 + mov.l CS1WCR_D, r0 + mov.l r0, @r1 - mov.l CS2WCR_A,r1 - mov.l CS2WCR_D,r0 - mov.l r0,@r1 + mov.l CS2WCR_A, r1 + mov.l CS2WCR_D, r0 + mov.l r0, @r1 - mov.l CS4WCR_A,r1 - mov.l CS4WCR_D,r0 - mov.l r0,@r1 + mov.l CS4WCR_A, r1 + mov.l CS4WCR_D, r0 + mov.l r0, @r1 - mov.l CS5WCR_A,r1 - mov.l CS5WCR_D,r0 - mov.l r0,@r1 + mov.l CS5WCR_A, r1 + mov.l CS5WCR_D, r0 + mov.l r0, @r1 - mov.l CS6WCR_A,r1 - mov.l CS6WCR_D,r0 - mov.l r0,@r1 + mov.l CS6WCR_A, r1 + mov.l CS6WCR_D, r0 + mov.l r0, @r1 - mov.l CS5PCR_A,r1 - mov.l CS5PCR_D,r0 - mov.l r0,@r1 + mov.l CS5PCR_A, r1 + mov.l CS5PCR_D, r0 + mov.l r0, @r1 - mov.l CS6PCR_A,r1 - mov.l CS6PCR_D,r0 - mov.l r0,@r1 + mov.l CS6PCR_A, r1 + mov.l CS6PCR_D, r0 + mov.l r0, @r1 /* ddr_setting */ /* wait 200us */ - mov.l REPEAT0_R3,r3 - mov #0,r2 + mov.l REPEAT0_R3, r3 + mov #0, r2 repeat1: - add #1,r2 - cmp/hs r3,r2 - bf repeat1 + add #1, r2 + cmp/hs r3, r2 + bf repeat1 nop - mov.l MIM_U_A,r0 - mov.l MIM_U_D,r1 + mov.l MIM_U_A, r0 + mov.l MIM_U_D, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco - mov.l MIM_L_A,r0 - mov.l MIM_L_D0,r1 + mov.l MIM_L_A, r0 + mov.l MIM_L_D0, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco - mov.l STR_L_A,r0 - mov.l STR_L_D,r1 + mov.l STR_L_A, r0 + mov.l STR_L_D, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco - mov.l SDR_L_A,r0 - mov.l SDR_L_D,r1 + mov.l SDR_L_A, r0 + mov.l SDR_L_D, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco nop @@ -220,193 +220,193 @@ repeat1: nop nop - mov.l SCR_L_A,r0 - mov.l SCR_L_D0,r1 + mov.l SCR_L_A, r0 + mov.l SCR_L_D0, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco - mov.l SCR_L_A,r0 - mov.l SCR_L_D1,r1 + mov.l SCR_L_A, r0 + mov.l SCR_L_D1, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco nop nop nop - mov.l EMRS_A,r0 - mov.l EMRS_D,r1 + mov.l EMRS_A, r0 + mov.l EMRS_D, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco nop nop nop - mov.l MRS1_A,r0 - mov.l MRS1_D,r1 + mov.l MRS1_A, r0 + mov.l MRS1_D, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco nop nop nop - mov.l SCR_L_A,r0 - mov.l SCR_L_D2,r1 + mov.l SCR_L_A, r0 + mov.l SCR_L_D2, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco nop nop nop - mov.l SCR_L_A,r0 - mov.l SCR_L_D3,r1 + mov.l SCR_L_A, r0 + mov.l SCR_L_D3, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco nop nop nop - mov.l SCR_L_A,r0 - mov.l SCR_L_D4,r1 + mov.l SCR_L_A, r0 + mov.l SCR_L_D4, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco nop nop nop - mov.l MRS2_A,r0 - mov.l MRS2_D,r1 + mov.l MRS2_A, r0 + mov.l MRS2_D, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco nop nop nop - mov.l SCR_L_A,r0 - mov.l SCR_L_D5,r1 + mov.l SCR_L_A, r0 + mov.l SCR_L_D5, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco /* wait 200us */ - mov.l REPEAT0_R1,r3 - mov #0,r2 + mov.l REPEAT0_R1, r3 + mov #0, r2 repeat2: - add #1,r2 - cmp/hs r3,r2 - bf repeat2 + add #1, r2 + cmp/hs r3, r2 + bf repeat2 synco - mov.l MIM_L_A,r0 - mov.l MIM_L_D1,r1 + mov.l MIM_L_A, r0 + mov.l MIM_L_D1, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco rts nop .align 4 -RWTCSR_D_1: .word 0xA507 -RWTCSR_D_2: .word 0xA507 -RWTCNT_D: .word 0x5A00 +RWTCSR_D_1: .word 0xA507 +RWTCSR_D_2: .word 0xA507 +RWTCNT_D: .word 0x5A00 .align 2 -BBG_PMMR_A: .long 0xFF800010 -BBG_PMSR1_A: .long 0xFF800014 -BBG_PMSR2_A: .long 0xFF800018 -BBG_PMSR3_A: .long 0xFF80001C -BBG_PMSR4_A: .long 0xFF800020 -BBG_PMSRG_A: .long 0xFF800024 +BBG_PMMR_A: .long 0xFF800010 +BBG_PMSR1_A: .long 0xFF800014 +BBG_PMSR2_A: .long 0xFF800018 +BBG_PMSR3_A: .long 0xFF80001C +BBG_PMSR4_A: .long 0xFF800020 +BBG_PMSRG_A: .long 0xFF800024 -BBG_PMMR_D_PMSR1: .long 0xffffbffd -BBG_PMSR1_D: .long 0x00004002 -BBG_PMMR_D_PMSR2: .long 0xfc21a7ff -BBG_PMSR2_D: .long 0x03de5800 -BBG_PMMR_D_PMSR3: .long 0xfffffff8 -BBG_PMSR3_D: .long 0x00000007 -BBG_PMMR_D_PMSR4: .long 0xdffdfff9 -BBG_PMSR4_D: .long 0x20020006 -BBG_PMMR_D_PMSRG: .long 0xffffffff -BBG_PMSRG_D: .long 0x00000000 +BBG_PMMR_D_PMSR1: .long 0xffffbffd +BBG_PMSR1_D: .long 0x00004002 +BBG_PMMR_D_PMSR2: .long 0xfc21a7ff +BBG_PMSR2_D: .long 0x03de5800 +BBG_PMMR_D_PMSR3: .long 0xfffffff8 +BBG_PMSR3_D: .long 0x00000007 +BBG_PMMR_D_PMSR4: .long 0xdffdfff9 +BBG_PMSR4_D: .long 0x20020006 +BBG_PMMR_D_PMSRG: .long 0xffffffff +BBG_PMSRG_D: .long 0x00000000 -FRQCR_A: .long FRQCR -DLLCSR_A: .long 0xffc40010 -FRQCR_D: .long 0x40233035 -DLLCSR_D: .long 0x00000000 +FRQCR_A: .long FRQCR +DLLCSR_A: .long 0xffc40010 +FRQCR_D: .long 0x40233035 +DLLCSR_D: .long 0x00000000 /* for DDR-SDRAM */ -MIM_U_A: .long MIM_1 -MIM_L_A: .long MIM_2 -SCR_U_A: .long SCR_1 -SCR_L_A: .long SCR_2 -STR_U_A: .long STR_1 -STR_L_A: .long STR_2 -SDR_U_A: .long SDR_1 -SDR_L_A: .long SDR_2 +MIM_U_A: .long MIM_1 +MIM_L_A: .long MIM_2 +SCR_U_A: .long SCR_1 +SCR_L_A: .long SCR_2 +STR_U_A: .long STR_1 +STR_L_A: .long STR_2 +SDR_U_A: .long SDR_1 +SDR_L_A: .long SDR_2 -EMRS_A: .long 0xFEC02000 -MRS1_A: .long 0xFEC00B08 -MRS2_A: .long 0xFEC00308 +EMRS_A: .long 0xFEC02000 +MRS1_A: .long 0xFEC00B08 +MRS2_A: .long 0xFEC00308 -MIM_U_D: .long 0x00004000 -MIM_L_D0: .long 0x03e80009 -MIM_L_D1: .long 0x03e80209 -SCR_L_D0: .long 0x3 -SCR_L_D1: .long 0x2 -SCR_L_D2: .long 0x2 -SCR_L_D3: .long 0x4 -SCR_L_D4: .long 0x4 -SCR_L_D5: .long 0x0 -STR_L_D: .long 0x000f0000 -SDR_L_D: .long 0x00000400 -EMRS_D: .long 0x0 -MRS1_D: .long 0x0 -MRS2_D: .long 0x0 +MIM_U_D: .long 0x00004000 +MIM_L_D0: .long 0x03e80009 +MIM_L_D1: .long 0x03e80209 +SCR_L_D0: .long 0x3 +SCR_L_D1: .long 0x2 +SCR_L_D2: .long 0x2 +SCR_L_D3: .long 0x4 +SCR_L_D4: .long 0x4 +SCR_L_D5: .long 0x0 +STR_L_D: .long 0x000f0000 +SDR_L_D: .long 0x00000400 +EMRS_D: .long 0x0 +MRS1_D: .long 0x0 +MRS2_D: .long 0x0 /* Cache Controller */ -CCR_A: .long CCR -MMUCR_A: .long MMUCR -RWTCNT_A: .long WTCNT +CCR_A: .long CCR +MMUCR_A: .long MMUCR +RWTCNT_A: .long WTCNT -CCR_D: .long 0x0000090b -CCR_D_2: .long 0x00000103 -MMUCR_D: .long 0x00000004 -MSTPCR0_D: .long 0x00001001 -MSTPCR2_D: .long 0xffffffff +CCR_D: .long 0x0000090b +CCR_D_2: .long 0x00000103 +MMUCR_D: .long 0x00000004 +MSTPCR0_D: .long 0x00001001 +MSTPCR2_D: .long 0xffffffff /* local Bus State Controller */ -MMSELR_A: .long MMSELR -BCR_A: .long BCR -CS0BCR_A: .long CS0BCR -CS1BCR_A: .long CS1BCR -CS2BCR_A: .long CS2BCR -CS4BCR_A: .long CS4BCR -CS5BCR_A: .long CS5BCR -CS6BCR_A: .long CS6BCR -CS0WCR_A: .long CS0WCR -CS1WCR_A: .long CS1WCR -CS2WCR_A: .long CS2WCR -CS4WCR_A: .long CS4WCR -CS5WCR_A: .long CS5WCR -CS6WCR_A: .long CS6WCR -CS5PCR_A: .long CS5PCR -CS6PCR_A: .long CS6PCR +MMSELR_A: .long MMSELR +BCR_A: .long BCR +CS0BCR_A: .long CS0BCR +CS1BCR_A: .long CS1BCR +CS2BCR_A: .long CS2BCR +CS4BCR_A: .long CS4BCR +CS5BCR_A: .long CS5BCR +CS6BCR_A: .long CS6BCR +CS0WCR_A: .long CS0WCR +CS1WCR_A: .long CS1WCR +CS2WCR_A: .long CS2WCR +CS4WCR_A: .long CS4WCR +CS5WCR_A: .long CS5WCR +CS6WCR_A: .long CS6WCR +CS5PCR_A: .long CS5PCR +CS6PCR_A: .long CS6PCR MMSELR_D: .long 0xA5A50003 BCR_D: .long 0x00000000 @@ -425,5 +425,5 @@ CS6WCR_D: .long 0x77777703 CS5PCR_D: .long 0x77000000 CS6PCR_D: .long 0x77000000 -REPEAT0_R3: .long 0x00002000 -REPEAT0_R1: .long 0x0000200 +REPEAT0_R3: .long 0x00002000 +REPEAT0_R1: .long 0x0000200 diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S index e4d6f9e7d..f6a62311d 100644 --- a/board/renesas/rsk7203/lowlevel_init.S +++ b/board/renesas/rsk7203/lowlevel_init.S @@ -29,153 +29,153 @@ lowlevel_init: /* Cache setting */ - mov.l CCR1_A ,r1 - mov.l CCR1_D ,r0 - mov.l r0,@r1 + mov.l CCR1_A, r1 + mov.l CCR1_D, r0 + mov.l r0, @r1 /* ConfigurePortPins */ - mov.l PECRL3_A, r1 - mov.l PECRL3_D, r0 - mov.w r0,@r1 + mov.l PECRL3_A, r1 + mov.l PECRL3_D, r0 + mov.w r0, @r1 - mov.l PCCRL4_A, r1 - mov.l PCCRL4_D0, r0 - mov.w r0,@r1 + mov.l PCCRL4_A, r1 + mov.l PCCRL4_D0, r0 + mov.w r0, @r1 - mov.l PECRL4_A, r1 - mov.l PECRL4_D0, r0 - mov.w r0,@r1 + mov.l PECRL4_A, r1 + mov.l PECRL4_D0, r0 + mov.w r0, @r1 - mov.l PEIORL_A, r1 - mov.l PEIORL_D0, r0 - mov.w r0,@r1 + mov.l PEIORL_A, r1 + mov.l PEIORL_D0, r0 + mov.w r0, @r1 - mov.l PCIORL_A, r1 - mov.l PCIORL_D, r0 - mov.w r0,@r1 + mov.l PCIORL_A, r1 + mov.l PCIORL_D, r0 + mov.w r0, @r1 - mov.l PFCRH2_A, r1 - mov.l PFCRH2_D, r0 - mov.w r0,@r1 + mov.l PFCRH2_A, r1 + mov.l PFCRH2_D, r0 + mov.w r0, @r1 - mov.l PFCRH3_A, r1 - mov.l PFCRH3_D, r0 - mov.w r0,@r1 + mov.l PFCRH3_A, r1 + mov.l PFCRH3_D, r0 + mov.w r0, @r1 - mov.l PFCRH1_A, r1 - mov.l PFCRH1_D, r0 - mov.w r0,@r1 + mov.l PFCRH1_A, r1 + mov.l PFCRH1_D, r0 + mov.w r0, @r1 - mov.l PFIORH_A, r1 - mov.l PFIORH_D, r0 - mov.w r0,@r1 + mov.l PFIORH_A, r1 + mov.l PFIORH_D, r0 + mov.w r0, @r1 - mov.l PECRL1_A, r1 - mov.l PECRL1_D0, r0 - mov.w r0,@r1 + mov.l PECRL1_A, r1 + mov.l PECRL1_D0, r0 + mov.w r0, @r1 - mov.l PEIORL_A, r1 - mov.l PEIORL_D1, r0 - mov.w r0,@r1 + mov.l PEIORL_A, r1 + mov.l PEIORL_D1, r0 + mov.w r0, @r1 /* Configure Operating Frequency */ - mov.l WTCSR_A ,r1 - mov.l WTCSR_D0 ,r0 - mov.w r0,@r1 + mov.l WTCSR_A, r1 + mov.l WTCSR_D0, r0 + mov.w r0, @r1 - mov.l WTCSR_A ,r1 - mov.l WTCSR_D1 ,r0 - mov.w r0,@r1 + mov.l WTCSR_A, r1 + mov.l WTCSR_D1, r0 + mov.w r0, @r1 - mov.l WTCNT_A ,r1 - mov.l WTCNT_D ,r0 - mov.w r0,@r1 + mov.l WTCNT_A, r1 + mov.l WTCNT_D, r0 + mov.w r0, @r1 /* Set clock mode*/ - mov.l FRQCR_A,r1 - mov.l FRQCR_D,r0 - mov.w r0,@r1 + mov.l FRQCR_A, r1 + mov.l FRQCR_D, r0 + mov.w r0, @r1 /* Configure Bus And Memory */ init_bsc_cs0: - mov.l PCCRL4_A,r1 - mov.l PCCRL4_D1,r0 - mov.w r0,@r1 + mov.l PCCRL4_A, r1 + mov.l PCCRL4_D1, r0 + mov.w r0, @r1 - mov.l PECRL1_A,r1 - mov.l PECRL1_D1,r0 - mov.w r0,@r1 + mov.l PECRL1_A, r1 + mov.l PECRL1_D1, r0 + mov.w r0, @r1 - mov.l CMNCR_A,r1 - mov.l CMNCR_D,r0 - mov.l r0,@r1 + mov.l CMNCR_A, r1 + mov.l CMNCR_D, r0 + mov.l r0, @r1 - mov.l SC0BCR_A,r1 - mov.l SC0BCR_D,r0 - mov.l r0,@r1 + mov.l SC0BCR_A, r1 + mov.l SC0BCR_D, r0 + mov.l r0, @r1 - mov.l CS0WCR_A,r1 - mov.l CS0WCR_D,r0 - mov.l r0,@r1 + mov.l CS0WCR_A, r1 + mov.l CS0WCR_D, r0 + mov.l r0, @r1 init_bsc_cs1: - mov.l PECRL4_A,r1 - mov.l PECRL4_D1,r0 - mov.w r0,@r1 + mov.l PECRL4_A, r1 + mov.l PECRL4_D1, r0 + mov.w r0, @r1 - mov.l CS1WCR_A,r1 - mov.l CS1WCR_D,r0 - mov.l r0,@r1 + mov.l CS1WCR_A, r1 + mov.l CS1WCR_D, r0 + mov.l r0, @r1 init_sdram: - mov.l PCCRL2_A,r1 - mov.l PCCRL2_D,r0 - mov.w r0,@r1 + mov.l PCCRL2_A, r1 + mov.l PCCRL2_D, r0 + mov.w r0, @r1 - mov.l PCCRL4_A,r1 - mov.l PCCRL4_D2,r0 - mov.w r0,@r1 + mov.l PCCRL4_A, r1 + mov.l PCCRL4_D2, r0 + mov.w r0, @r1 - mov.l PCCRL1_A,r1 - mov.l PCCRL1_D,r0 - mov.w r0,@r1 + mov.l PCCRL1_A, r1 + mov.l PCCRL1_D, r0 + mov.w r0, @r1 - mov.l PCCRL3_A,r1 - mov.l PCCRL3_D,r0 - mov.w r0,@r1 + mov.l PCCRL3_A, r1 + mov.l PCCRL3_D, r0 + mov.w r0, @r1 - mov.l CS3BCR_A,r1 - mov.l CS3BCR_D,r0 - mov.l r0,@r1 + mov.l CS3BCR_A, r1 + mov.l CS3BCR_D, r0 + mov.l r0, @r1 - mov.l CS3WCR_A,r1 - mov.l CS3WCR_D,r0 - mov.l r0,@r1 + mov.l CS3WCR_A, r1 + mov.l CS3WCR_D, r0 + mov.l r0, @r1 - mov.l SDCR_A,r1 - mov.l SDCR_D,r0 - mov.l r0,@r1 + mov.l SDCR_A, r1 + mov.l SDCR_D, r0 + mov.l r0, @r1 - mov.l RTCOR_A,r1 - mov.l RTCOR_D,r0 - mov.l r0,@r1 + mov.l RTCOR_A, r1 + mov.l RTCOR_D, r0 + mov.l r0, @r1 - mov.l RTCSR_A,r1 - mov.l RTCSR_D,r0 - mov.l r0,@r1 + mov.l RTCSR_A, r1 + mov.l RTCSR_D, r0 + mov.l r0, @r1 /* wait 200us */ - mov.l REPEAT_D,r3 - mov #0,r2 + mov.l REPEAT_D, r3 + mov #0, r2 repeat0: - add #1,r2 - cmp/hs r3,r2 - bf repeat0 + add #1, r2 + cmp/hs r3, r2 + bf repeat0 nop - mov.l SDRAM_MODE, r1 - mov #0,r0 - mov.l r0, @r1 + mov.l SDRAM_MODE, r1 + mov #0, r0 + mov.l r0, @r1 nop rts @@ -208,8 +208,8 @@ PECRL1_D0: .long 0x00000033 WTCSR_A: .long 0xFFFE0000 -WTCSR_D0: .long 0x0000A518 -WTCSR_D1: .long 0x0000A51D +WTCSR_D0: .long 0x0000A518 +WTCSR_D1: .long 0x0000A51D WTCNT_A: .long 0xFFFE0002 WTCNT_D: .long 0x00005A84 FRQCR_A: .long 0xFFFE0010 @@ -259,7 +259,7 @@ STBCR4_A: .long 0xFFFE040C STBCR4_D: .long 0x00000008 STBCR5_A: .long 0xFFFE0410 STBCR5_D: .long 0x00000000 -STBCR6_A: .long 0xFFFE0414 +STBCR6_A: .long 0xFFFE0414 STBCR6_D: .long 0x00000002 SDRAM_MODE: .long 0xFFFC5040 REPEAT_D: .long 0x00009C40 diff --git a/board/renesas/sh7763rdp/lowlevel_init.S b/board/renesas/sh7763rdp/lowlevel_init.S index 2a44eee1a..715e75fe6 100644 --- a/board/renesas/sh7763rdp/lowlevel_init.S +++ b/board/renesas/sh7763rdp/lowlevel_init.S @@ -33,17 +33,17 @@ lowlevel_init: - mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */ - mov.l WDTCSR_D, r0 - mov.l r0, @r1 + mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */ + mov.l WDTCSR_D, r0 + mov.l r0, @r1 - mov.l WDTST_A, r1 /* Watchdog Stop Time Register */ - mov.l WDTST_D, r0 - mov.l r0, @r1 + mov.l WDTST_A, r1 /* Watchdog Stop Time Register */ + mov.l WDTST_D, r0 + mov.l r0, @r1 - mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */ - mov.l WDTBST_D, r0 - mov.l r0, @r1 + mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */ + mov.l WDTBST_D, r0 + mov.l r0, @r1 mov.l CCR_A, r1 /* Address of Cache Control Register */ mov.l CCR_CACHE_ICI_D, r0 /* Instruction Cache Invalidate */ @@ -61,107 +61,107 @@ lowlevel_init: mov.l MSTPCR1_D, r0 mov.l r0, @r1 - mov.l RAMCR_A,r1 - mov.l RAMCR_D,r0 + mov.l RAMCR_A, r1 + mov.l RAMCR_D, r0 mov.l r0, @r1 - mov.l MMSELR_A,r1 - mov.l MMSELR_D,r0 + mov.l MMSELR_A, r1 + mov.l MMSELR_D, r0 synco mov.l r0, @r1 - mov.l @r1,r2 /* execute two reads after setting MMSELR*/ - mov.l @r1,r2 + mov.l @r1, r2 /* execute two reads after setting MMSELR*/ + mov.l @r1, r2 synco /* issue memory read */ - mov.l DDRSD_START_A,r1 /* memory address to read*/ - mov.l @r1,r0 + mov.l DDRSD_START_A, r1 /* memory address to read*/ + mov.l @r1, r0 synco - mov.l MIM8_A,r1 - mov.l MIM8_D,r0 - mov.l r0,@r1 + mov.l MIM8_A, r1 + mov.l MIM8_D, r0 + mov.l r0, @r1 - mov.l MIMC_A,r1 - mov.l MIMC_D1,r0 - mov.l r0,@r1 + mov.l MIMC_A, r1 + mov.l MIMC_D1, r0 + mov.l r0, @r1 - mov.l STRC_A,r1 - mov.l STRC_D,r0 - mov.l r0,@r1 + mov.l STRC_A, r1 + mov.l STRC_D, r0 + mov.l r0, @r1 - mov.l SDR4_A,r1 - mov.l SDR4_D,r0 - mov.l r0,@r1 + mov.l SDR4_A, r1 + mov.l SDR4_D, r0 + mov.l r0, @r1 - mov.l MIMC_A,r1 - mov.l MIMC_D2,r0 - mov.l r0,@r1 + mov.l MIMC_A, r1 + mov.l MIMC_D2, r0 + mov.l r0, @r1 nop nop nop - mov.l SCR4_A,r1 - mov.l SCR4_D3,r0 - mov.l r0,@r1 + mov.l SCR4_A, r1 + mov.l SCR4_D3, r0 + mov.l r0, @r1 - mov.l SCR4_A,r1 - mov.l SCR4_D2,r0 - mov.l r0,@r1 + mov.l SCR4_A, r1 + mov.l SCR4_D2, r0 + mov.l r0, @r1 - mov.l SDMR02000_A,r1 - mov.l SDMR02000_D,r0 - mov.l r0,@r1 + mov.l SDMR02000_A, r1 + mov.l SDMR02000_D, r0 + mov.l r0, @r1 - mov.l SDMR00B08_A,r1 - mov.l SDMR00B08_D,r0 - mov.l r0,@r1 + mov.l SDMR00B08_A, r1 + mov.l SDMR00B08_D, r0 + mov.l r0, @r1 - mov.l SCR4_A,r1 - mov.l SCR4_D2,r0 - mov.l r0,@r1 + mov.l SCR4_A, r1 + mov.l SCR4_D2, r0 + mov.l r0, @r1 - mov.l SCR4_A,r1 - mov.l SCR4_D4,r0 - mov.l r0,@r1 + mov.l SCR4_A, r1 + mov.l SCR4_D4, r0 + mov.l r0, @r1 nop nop nop nop - mov.l SCR4_A,r1 - mov.l SCR4_D4,r0 - mov.l r0,@r1 + mov.l SCR4_A, r1 + mov.l SCR4_D4, r0 + mov.l r0, @r1 nop nop nop nop - mov.l SDMR00308_A,r1 - mov.l SDMR00308_D,r0 - mov.l r0,@r1 + mov.l SDMR00308_A, r1 + mov.l SDMR00308_D, r0 + mov.l r0, @r1 - mov.l MIMC_A,r1 - mov.l MIMC_D3,r0 - mov.l r0,@r1 + mov.l MIMC_A, r1 + mov.l MIMC_D3, r0 + mov.l r0, @r1 - mov.l SCR4_A,r1 - mov.l SCR4_D1,r0 - mov.l DELAY60_D,r3 + mov.l SCR4_A, r1 + mov.l SCR4_D1, r0 + mov.l DELAY60_D, r3 delay_loop_60: - mov.l r0,@r1 + mov.l r0, @r1 dt r3 bf delay_loop_60 nop - mov.l CCR_A, r1 /* Address of Cache Control Register */ - mov.l CCR_CACHE_D_2, r0 - mov.l r0, @r1 + mov.l CCR_A, r1 /* Address of Cache Control Register */ + mov.l CCR_CACHE_D_2, r0 + mov.l r0, @r1 bsc_init: mov.l BCR_A, r1 @@ -172,9 +172,9 @@ bsc_init: mov.l CS0BCR_D, r0 mov.l r0, @r1 - mov.l CS1BCR_A,r1 - mov.l CS1BCR_D,r0 - mov.l r0,@r1 + mov.l CS1BCR_A, r1 + mov.l CS1BCR_D, r0 + mov.l r0, @r1 mov.l CS2BCR_A, r1 mov.l CS2BCR_D, r0 @@ -224,27 +224,27 @@ bsc_init: mov.l CS6PCR_D, r0 mov.l r0, @r1 - mov.l DELAY200_D,r3 + mov.l DELAY200_D, r3 delay_loop_200: dt r3 bf delay_loop_200 nop - mov.l PSEL0_A,r1 - mov.l PSEL0_D,r0 - mov.w r0,@r1 + mov.l PSEL0_A, r1 + mov.l PSEL0_D, r0 + mov.w r0, @r1 - mov.l PSEL1_A,r1 - mov.l PSEL1_D,r0 - mov.w r0,@r1 + mov.l PSEL1_A, r1 + mov.l PSEL1_D, r0 + mov.w r0, @r1 - mov.l ICR0_A,r1 - mov.l ICR0_D,r0 - mov.l r0,@r1 + mov.l ICR0_A, r1 + mov.l ICR0_D, r0 + mov.l r0, @r1 stc sr, r0 /* BL bit off(init=ON) */ - mov.l SR_MASK_D, r1 + mov.l SR_MASK_D, r1 and r1, r0 ldc r0, sr @@ -321,7 +321,7 @@ CS4BCR_D: .long 0x77777670 CS5BCR_D: .long 0x77777670 CS6BCR_D: .long 0x77777670 CS0WCR_D: .long 0x7777770F -CS1WCR_D: .long 0x22000002 +CS1WCR_D: .long 0x22000002 CS2WCR_D: .long 0x7777770F CS4WCR_D: .long 0x7777770F CS5WCR_D: .long 0x7777770F diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S index 50e1789cc..4cb1d9d67 100644 --- a/board/renesas/sh7785lcr/lowlevel_init.S +++ b/board/renesas/sh7785lcr/lowlevel_init.S @@ -305,7 +305,7 @@ CS4WCR_D: .long 0x00101012 CS_USB_BCR_D: .long 0x11111200 CS_USB_WCR_D: .long 0x00020004 -/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */ +/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */ CS_SD_BCR_D: .long 0x00000300 CS_SD_WCR_D: .long 0x00030108 From f7e78f3b74aae9caca2997bad865a72338326c0a Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 20 Dec 2008 19:29:49 +0100 Subject: [PATCH 110/188] sh: use write{8,16,32} in all lowlevel_init Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nobuhiro Iwamatsu --- board/mpr2/lowlevel_init.S | 49 ++----- board/ms7722se/lowlevel_init.S | 160 +++++++--------------- board/ms7750se/lowlevel_init.S | 64 +++------ board/renesas/MigoR/lowlevel_init.S | 141 ++++++------------- board/renesas/ap325rxa/lowlevel_init.S | 121 +++++------------ board/renesas/r2dplus/lowlevel_init.S | 85 +++--------- board/renesas/r7780mp/lowlevel_init.S | 122 +++++------------ board/renesas/rsk7203/lowlevel_init.S | 129 +++++------------- board/renesas/sh7763rdp/lowlevel_init.S | 172 +++++++----------------- board/renesas/sh7785lcr/lowlevel_init.S | 28 +--- include/asm-sh/macro.h | 52 +++++++ 11 files changed, 338 insertions(+), 785 deletions(-) create mode 100644 include/asm-sh/macro.h diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S index 187b5bbeb..5f02bd4bb 100644 --- a/board/mpr2/lowlevel_init.S +++ b/board/mpr2/lowlevel_init.S @@ -22,6 +22,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ +#include .global lowlevel_init @@ -33,59 +34,35 @@ lowlevel_init: /* * Set frequency multipliers and dividers in FRQCR. */ - mov.l WTCSR_A, r1 - mov.l WTCSR_D, r0 - mov.w r0, @r1 + write16 WTCSR_A, WTCSR_D - mov.l WTCNT_A, r1 - mov.l WTCNT_D, r0 - mov.w r0, @r1 + write16 WTCNT_A, WTCNT_D - mov.l FRQCR_A, r1 - mov.l FRQCR_D, r0 - mov.w r0, @r1 + write16 FRQCR_A, FRQCR_D /* * Setup CS0 (Flash). */ - mov.l CS0BCR_A, r1 - mov.l CS0BCR_D, r0 - mov.l r0, @r1 + write32 CS0BCR_A, CS0BCR_D - mov.l CS0WCR_A, r1 - mov.l CS0WCR_D, r0 - mov.l r0, @r1 + write32 CS0WCR_A, CS0WCR_D /* * Setup CS3 (SDRAM). */ - mov.l CS3BCR_A, r1 - mov.l CS3BCR_D, r0 - mov.l r0, @r1 + write32 CS3BCR_A, CS3BCR_D - mov.l CS3WCR_A, r1 - mov.l CS3WCR_D, r0 - mov.l r0, @r1 + write32 CS3WCR_A, CS3WCR_D - mov.l SDCR_A, r1 - mov.l SDCR_D1, r0 - mov.l r0, @r1 + write32 SDCR_A, SDCR_D1 - mov.l RTCSR_A, r1 - mov.l RTCSR_D, r0 - mov.l r0, @r1 + write32 RTCSR_A, RTCSR_D - mov.l RTCNT_A, r1 - mov.l RTCNT_D, r0 - mov.l r0, @r1 + write32 RTCNT_A, RTCNT_D - mov.l RTCOR_A, r1 - mov.l RTCOR_D, r0 - mov.l r0, @r1 + write32 RTCOR_A, RTCOR_D - mov.l SDCR_A, r1 - mov.l SDCR_D2, r0 - mov.l r0, @r1 + write32 SDCR_A, SDCR_D2 mov.l SDMR3_A, r1 mov.l SDMR3_D, r0 diff --git a/board/ms7722se/lowlevel_init.S b/board/ms7722se/lowlevel_init.S index 3e887cfe8..9144e104b 100644 --- a/board/ms7722se/lowlevel_init.S +++ b/board/ms7722se/lowlevel_init.S @@ -27,6 +27,7 @@ #include #include +#include /* * Board specific low level init code, called _very_ early in the @@ -43,165 +44,94 @@ lowlevel_init: - /* Address of Cache Control Register */ - mov.l CCR_A, r1 - /*Instruction Cache Invalidate */ - mov.l CCR_D, r0 - mov.l r0, @r1 + /* + * Cache Control Register + * Instruction Cache Invalidate + */ + write32 CCR_A, CCR_D - /* Address of MMU Control Register */ - mov.l MMUCR_A, r1 - /* TI == TLB Invalidate bit */ - mov.l MMUCR_D, r0 - mov.l r0, @r1 + /* + * Address of MMU Control Register + * TI == TLB Invalidate bit + */ + write32 MMUCR_A, MMUCR_D /* Address of Power Control Register 0 */ - mov.l MSTPCR0_A, r1 - mov.l MSTPCR0_D, r0 - mov.l r0, @r1 + write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 2 */ - mov.l MSTPCR2_A, r1 - mov.l MSTPCR2_D, r0 - mov.l r0, @r1 + write32 MSTPCR2_A, MSTPCR2_D - mov.l SBSCR_A, r1 - mov.w SBSCR_D, r0 - mov.w r0, @r1 + write16 SBSCR_A, SBSCR_D - mov.l PSCR_A, r1 - mov.w PSCR_D, r0 - mov.w r0, @r1 + write16 PSCR_A, PSCR_D /* 0xA4520004 (Watchdog Control / Status Register) */ -! mov.l RWTCSR_A, r1 - /* 0xA507 -> timer_STOP/WDT_CLK=max */ -! mov.w RWTCSR_D_1, r0 -! mov.w r0, @r1 +! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */ /* 0xA4520000 (Watchdog Count Register) */ - mov.l RWTCNT_A, r1 - /*0x5A00 -> Clear */ - mov.w RWTCNT_D, r0 - mov.w r0, @r1 + write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */ /* 0xA4520004 (Watchdog Control / Status Register) */ - mov.l RWTCSR_A, r1 - /* 0xA504 -> timer_STOP/CLK=500ms */ - mov.w RWTCSR_D_2, r0 - mov.w r0, @r1 + write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */ /* 0xA4150000 Frequency control register */ - mov.l FRQCR_A, r1 - mov.l FRQCR_D, r0 ! - mov.l r0, @r1 + write32 FRQCR_A, FRQCR_D - mov.l CCR_A, r1 - mov.l CCR_D_2, r0 - mov.l r0, @r1 + write32 CCR_A, CCR_D_2 bsc_init: - mov.l PSELA_A, r1 - mov.w PSELA_D, r0 - mov.w r0, @r1 + write16 PSELA_A, PSELA_D - mov.l DRVCR_A, r1 - mov.w DRVCR_D, r0 - mov.w r0, @r1 + write16 DRVCR_A, DRVCR_D - mov.l PCCR_A, r1 - mov.w PCCR_D, r0 - mov.w r0, @r1 + write16 PCCR_A, PCCR_D - mov.l PECR_A, r1 - mov.w PECR_D, r0 - mov.w r0, @r1 + write16 PECR_A, PECR_D - mov.l PJCR_A, r1 - mov.w PJCR_D, r0 - mov.w r0, @r1 + write16 PJCR_A, PJCR_D - mov.l PXCR_A, r1 - mov.w PXCR_D, r0 - mov.w r0, @r1 + write16 PXCR_A, PXCR_D - mov.l CMNCR_A, r1 ! CMNCR address -> R1 - mov.l CMNCR_D, r0 ! CMNCR data -> R0 - mov.l r0, @r1 ! CMNCR set + write32 CMNCR_A, CMNCR_D - mov.l CS0BCR_A, r1 ! CS0BCR address -> R1 - mov.l CS0BCR_D, r0 ! CS0BCR data -> R0 - mov.l r0, @r1 ! CS0BCR set + write32 CS0BCR_A, CS0BCR_D - mov.l CS2BCR_A, r1 ! CS2BCR address -> R1 - mov.l CS2BCR_D, r0 ! CS2BCR data -> R0 - mov.l r0, @r1 ! CS2BCR set + write32 CS2BCR_A, CS2BCR_D - mov.l CS4BCR_A, r1 ! CS4BCR address -> R1 - mov.l CS4BCR_D, r0 ! CS4BCR data -> R0 - mov.l r0, @r1 ! CS4BCR set + write32 CS4BCR_A, CS4BCR_D - mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1 - mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0 - mov.l r0, @r1 ! CS5ABCR set + write32 CS5ABCR_A, CS5ABCR_D - mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1 - mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0 - mov.l r0, @r1 ! CS5BBCR set + write32 CS5BBCR_A, CS5BBCR_D - mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1 - mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0 - mov.l r0, @r1 ! CS6ABCR set + write32 CS6ABCR_A, CS6ABCR_D - mov.l CS0WCR_A, r1 ! CS0WCR address -> R1 - mov.l CS0WCR_D, r0 ! CS0WCR data -> R0 - mov.l r0, @r1 ! CS0WCR set + write32 CS0WCR_A, CS0WCR_D - mov.l CS2WCR_A, r1 ! CS2WCR address -> R1 - mov.l CS2WCR_D, r0 ! CS2WCR data -> R0 - mov.l r0, @r1 ! CS2WCR set + write32 CS2WCR_A, CS2WCR_D - mov.l CS4WCR_A, r1 ! CS4WCR address -> R1 - mov.l CS4WCR_D, r0 ! CS4WCR data -> R0 - mov.l r0, @r1 ! CS4WCR set + write32 CS4WCR_A, CS4WCR_D - mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1 - mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0 - mov.l r0, @r1 ! CS5AWCR set + write32 CS5AWCR_A, CS5AWCR_D - mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1 - mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0 - mov.l r0, @r1 ! CS5BWCR set + write32 CS5BWCR_A, CS5BWCR_D - mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1 - mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0 - mov.l r0, @r1 ! CS6AWCR set + write32 CS6AWCR_A, CS6AWCR_D ! SDRAM initialization - mov.l SDCR_A, r1 ! SB_SDCR address -> R1 - mov.l SDCR_D, r0 ! SB_SDCR data -> R0 - mov.l r0, @r1 ! SB_SDCR set + write32 SDCR_A, SDCR_D - mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1 - mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0 - mov.l r0, @r1 ! SB_SDWCR set + write32 SDWCR_A, SDWCR_D - mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1 - mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0 - mov.l r0, @r1 ! SB_SDPCR set + write32 SDPCR_A, SDPCR_D - mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1 - mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0 - mov.l r0, @r1 ! SB_RTCOR set + write32 RTCOR_A, RTCOR_D - mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1 - mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0 - mov.l r0, @r1 ! SB_RTCSR set + write32 RTCSR_A, RTCSR_D - mov.l SDMR3_A, r1 ! SDMR3 address -> R1 - mov #0x00, r0 ! SDMR3 data -> R0 - mov.b r0, @r1 ! SDMR3 set + write8 SDMR3_A, #0x00 ! BL bit off (init = ON) (?!?) diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S index de05dd9ee..710801978 100644 --- a/board/ms7750se/lowlevel_init.S +++ b/board/ms7750se/lowlevel_init.S @@ -29,6 +29,7 @@ #include #include +#include #ifdef CONFIG_CPU_SH7751 #define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ @@ -65,61 +66,37 @@ lowlevel_init: - mov.l CCR_A, r1 ! CCR Address - mov.l CCR_D_DISABLE, r0 ! CCR Data - mov.l r0, @r1 + write32 CCR_A, CCR_D_DISABLE init_bsc: - mov.l FRQCR_A, r1 /* FRQCR Address */ - mov.l FRQCR_D, r0 /* FRQCR Data */ - mov.w r0, @r1 + write16 FRQCR_A, FRQCR_D - mov.l BCR1_A, r1 /* BCR1 Address */ - mov.l BCR1_D, r0 /* BCR1 Data */ - mov.l r0, @r1 + write32 BCR1_A, BCR1_D - mov.l BCR2_A, r1 /* BCR2 Address */ - mov.l BCR2_D, r0 /* BCR2 Data */ - mov.w r0, @r1 + write16 BCR2_A, BCR2_D - mov.l WCR1_A, r1 /* WCR1 Address */ - mov.l WCR1_D, r0 /* WCR1 Data */ - mov.l r0, @r1 + write32 WCR1_A, WCR1_D - mov.l WCR2_A, r1 /* WCR2 Address */ - mov.l WCR2_D, r0 /* WCR2 Data */ - mov.l r0, @r1 + write32 WCR2_A, WCR2_D - mov.l WCR3_A, r1 /* WCR3 Address */ - mov.l WCR3_D, r0 /* WCR3 Data */ - mov.l r0, @r1 + write32 WCR3_A, WCR3_D - mov.l MCR_A, r1 /* MCR Address */ - mov.l MCR_D1, r0 /* MCR Data1 */ - mov.l r0, @r1 + write32 MCR_A, MCR_D1 - mov.l SDMR3_A, r1 /* Set SDRAM mode */ - mov #0, r0 - mov.b r0, @r1 + /* Set SDRAM mode */ + write8 SDMR3_A, #0 ! Do you need PCMCIA setting? ! If so, please add the lines here... - mov.l RTCNT_A, r1 /* RTCNT Address */ - mov.l RTCNT_D, r0 /* RTCNT Data */ - mov.w r0, @r1 + write16 RTCNT_A, RTCNT_D - mov.l RTCOR_A, r1 /* RTCOR Address */ - mov.l RTCOR_D, r0 /* RTCOR Data */ - mov.w r0, @r1 + write16 RTCOR_A, RTCOR_D - mov.l RTCSR_A, r1 /* RTCSR Address */ - mov.l RTCSR_D, r0 /* RTCSR Data */ - mov.w r0, @r1 + write16 RTCSR_A, RTCSR_D + + write16 RFCR_A, RFCR_D - mov.l RFCR_A, r1 /* RFCR Address */ - mov.l RFCR_D, r0 /* RFCR Data */ - mov.w r0, @r1 /* Clear reflesh counter */ /* Wait DRAM refresh 30 times */ mov #30, r3 1: @@ -128,13 +105,10 @@ init_bsc: cmp/hi r3, r2 bf 1b - mov.l MCR_A, r1 /* MCR Address */ - mov.l MCR_D2, r0 /* MCR Data2 */ - mov.l r0, @r1 + write32 MCR_A, MCR_D2 - mov.l SDMR3_A, r1 /* Set SDRAM mode */ - mov #0, r0 - mov.b r0, @r1 + /* Set SDRAM mode */ + write8 SDMR3_A, #0 rts nop diff --git a/board/renesas/MigoR/lowlevel_init.S b/board/renesas/MigoR/lowlevel_init.S index 13c83bf8c..1da603a9f 100644 --- a/board/renesas/MigoR/lowlevel_init.S +++ b/board/renesas/MigoR/lowlevel_init.S @@ -27,6 +27,7 @@ #include #include +#include /* * Board specific low level init code, called _very_ early in the @@ -42,139 +43,81 @@ .align 2 lowlevel_init: - mov.l CCR_A, r1 ! Address of Cache Control Register - mov.l CCR_D, r0 ! Instruction Cache Invalidate - mov.l r0, @r1 + write32 CCR_A, CCR_D ! Address of Cache Control Register + ! Instruction Cache Invalidate - mov.l MMUCR_A, r1 ! Address of MMU Control Register - mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit - mov.l r0, @r1 + write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register + ! TI == TLB Invalidate bit - mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0 - mov.l MSTPCR0_D, r0 ! - mov.l r0, @r1 + write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0 - mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2 - mov.l MSTPCR2_D, r0 ! - mov.l r0, @r1 + write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2 - mov.l PFC_PULCR_A, r1 - mov.w PFC_PULCR_D, r0 - mov.w r0,@r1 + write16 PFC_PULCR_A, PFC_PULCR_D - mov.l PFC_DRVCR_A, r1 - mov.w PFC_DRVCR_D, r0 - mov.w r0, @r1 + write16 PFC_DRVCR_A, PFC_DRVCR_D - mov.l SBSCR_A, r1 ! - mov.w SBSCR_D, r0 ! - mov.w r0, @r1 + write16 SBSCR_A, SBSCR_D - mov.l PSCR_A, r1 ! - mov.w PSCR_D, r0 ! - mov.w r0, @r1 + write16 PSCR_A, PSCR_D - mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) - mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max - mov.w r0, @r1 + write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register) + ! 0xA507 -> timer_STOP / WDT_CLK = max - mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register) - mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear - mov.w r0, @r1 + write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register) + ! 0x5A00 -> Clear - mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) - mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms - mov.w r0, @r1 + write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register) + ! 0xA504 -> timer_STOP / CLK = 500ms - mov.l DLLFRQ_A, r1 ! 20080115 - mov.l DLLFRQ_D, r0 ! 20080115 - mov.l r0, @r1 + write32 DLLFRQ_A, DLLFRQ_D ! 20080115 + ! 20080115 - mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register - mov.l FRQCR_D, r0 ! 20080115 - mov.l r0, @r1 + write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register + ! 20080115 - mov.l CCR_A, r1 ! Address of Cache Control Register - mov.l CCR_D_2, r0 ! ?? - mov.l r0, @r1 + write32 CCR_A, CCR_D_2 ! Address of Cache Control Register + ! ?? bsc_init: - mov.l CMNCR_A, r1 ! CMNCR address -> R1 - mov.l CMNCR_D, r0 ! CMNCR data -> R0 - mov.l r0, @r1 ! CMNCR set + write32 CMNCR_A, CMNCR_D - mov.l CS0BCR_A, r1 ! CS0BCR address -> R1 - mov.l CS0BCR_D, r0 ! CS0BCR data -> R0 - mov.l r0, @r1 ! CS0BCR set + write32 CS0BCR_A, CS0BCR_D - mov.l CS4BCR_A, r1 ! CS4BCR address -> R1 - mov.l CS4BCR_D, r0 ! CS4BCR data -> R0 - mov.l r0, @r1 ! CS4BCR set + write32 CS4BCR_A, CS4BCR_D - mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1 - mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0 - mov.l r0, @r1 ! CS5ABCR set + write32 CS5ABCR_A, CS5ABCR_D - mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1 - mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0 - mov.l r0, @r1 ! CS5BBCR set + write32 CS5BBCR_A, CS5BBCR_D - mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1 - mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0 - mov.l r0, @r1 ! CS6ABCR set + write32 CS6ABCR_A, CS6ABCR_D - mov.l CS0WCR_A, r1 ! CS0WCR address -> R1 - mov.l CS0WCR_D, r0 ! CS0WCR data -> R0 - mov.l r0, @r1 ! CS0WCR set + write32 CS0WCR_A, CS0WCR_D - mov.l CS4WCR_A, r1 ! CS4WCR address -> R1 - mov.l CS4WCR_D, r0 ! CS4WCR data -> R0 - mov.l r0, @r1 ! CS4WCR set + write32 CS4WCR_A, CS4WCR_D - mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1 - mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0 - mov.l r0, @r1 ! CS5AWCR set + write32 CS5AWCR_A, CS5AWCR_D - mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1 - mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0 - mov.l r0, @r1 ! CS5BWCR set + write32 CS5BWCR_A, CS5BWCR_D - mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1 - mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0 - mov.l r0, @r1 ! CS6AWCR set + write32 CS6AWCR_A, CS6AWCR_D ! SDRAM initialization - mov.l SDCR_A, r1 ! SB_SDCR address -> R1 - mov.l SDCR_D, r0 ! SB_SDCR data -> R0 - mov.l r0, @r1 ! SB_SDCR set + write32 SDCR_A, SDCR_D - mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1 - mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0 - mov.l r0, @r1 ! SB_SDWCR set + write32 SDWCR_A, SDWCR_D - mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1 - mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0 - mov.l r0, @r1 ! SB_SDPCR set + write32 SDPCR_A, SDPCR_D - mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1 - mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0 - mov.l r0, @r1 ! SB_RTCOR set + write32 RTCOR_A, RTCOR_D - mov.l RTCNT_A, r1 ! SB_RTCNT address -> R1 - mov.l RTCNT_D, r0 ! SB_RTCNT data -> R0 - mov.l r0, @r1 + write32 RTCNT_A, RTCNT_D - mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1 - mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0 - mov.l r0, @r1 ! SB_RTCSR set + write32 RTCSR_A, RTCSR_D - mov.l RFCR_A, r1 ! SB_RFCR address -> R1 - mov.l RFCR_D, r0 ! SB_RFCR data -> R0 - mov.l r0, @r1 + write32 RFCR_A, RFCR_D - mov.l SDMR3_A, r1 ! SDMR3 address -> R1 - mov #0x00, r0 ! SDMR3 data -> R0 - mov.b r0, @r1 ! SDMR3 set + write8 SDMR3_A, #0x00 ! BL bit off (init = ON) (?!?) diff --git a/board/renesas/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S index 558e7793e..b32f49132 100644 --- a/board/renesas/ap325rxa/lowlevel_init.S +++ b/board/renesas/ap325rxa/lowlevel_init.S @@ -23,6 +23,7 @@ #include #include #include +#include /* * Board specific low level init code, called _very_ early in the @@ -38,113 +39,59 @@ .align 2 lowlevel_init: - mov.l DRVCRA_A, r1 - mov.l DRVCRA_D, r0 - mov.w r0, @r1 + write16 DRVCRA_A, DRVCRA_D - mov.l DRVCRB_A, r1 - mov.l DRVCRB_D, r0 - mov.w r0, @r1 + write16 DRVCRB_A, DRVCRB_D - mov.l RWTCSR_A, r1 - mov.l RWTCSR_D1, r0 - mov.w r0, @r1 + write16 RWTCSR_A, RWTCSR_D1 - mov.l RWTCNT_A, r1 - mov.l RWTCNT_D, r0 - mov.w r0, @r1 + write16 RWTCNT_A, RWTCNT_D - mov.l RWTCSR_A, r1 - mov.l RWTCSR_D2, r0 - mov.w r0, @r1 + write16 RWTCSR_A, RWTCSR_D2 - mov.l FRQCR_A, r1 - mov.l FRQCR_D, r0 - mov.l r0, @r1 + write32 FRQCR_A, FRQCR_D - mov.l CMNCR_A, r1 - mov.l CMNCR_D, r0 - mov.l r0, @r1 + write32 CMNCR_A, CMNCR_D - mov.l CS0BCR_A, r1 - mov.l CS0BCR_D, r0 - mov.l r0, @r1 + write32 CS0BCR_A, CS0BCR_D - mov.l CS4BCR_A, r1 - mov.l CS4BCR_D, r0 - mov.l r0, @r1 + write32 CS4BCR_A, CS4BCR_D - mov.l CS5ABCR_A, r1 - mov.l CS5ABCR_D, r0 - mov.l r0, @r1 + write32 CS5ABCR_A, CS5ABCR_D - mov.l CS5BBCR_A, r1 - mov.l CS5BBCR_D, r0 - mov.l r0, @r1 + write32 CS5BBCR_A, CS5BBCR_D - mov.l CS6ABCR_A, r1 - mov.l CS6ABCR_D, r0 - mov.l r0, @r1 + write32 CS6ABCR_A, CS6ABCR_D - mov.l CS6BBCR_A, r1 - mov.l CS6BBCR_D, r0 - mov.l r0, @r1 + write32 CS6BBCR_A, CS6BBCR_D - mov.l CS0WCR_A, r1 - mov.l CS0WCR_D, r0 - mov.l r0, @r1 + write32 CS0WCR_A, CS0WCR_D - mov.l CS4WCR_A, r1 - mov.l CS4WCR_D, r0 - mov.l r0, @r1 + write32 CS4WCR_A, CS4WCR_D - mov.l CS5AWCR_A, r1 - mov.l CS5AWCR_D, r0 - mov.l r0, @r1 + write32 CS5AWCR_A, CS5AWCR_D - mov.l CS5BWCR_A, r1 - mov.l CS5BWCR_D, r0 - mov.l r0, @r1 + write32 CS5BWCR_A, CS5BWCR_D - mov.l CS6AWCR_A, r1 - mov.l CS6AWCR_D, r0 - mov.l r0, @r1 + write32 CS6AWCR_A, CS6AWCR_D - mov.l CS6BWCR_A, r1 - mov.l CS6BWCR_D, r0 - mov.l r0, @r1 + write32 CS6BWCR_A, CS6BWCR_D - mov.l SBSC_SDCR_A, r1 - mov.l SBSC_SDCR_D1, r0 - mov.l r0, @r1 + write32 SBSC_SDCR_A, SBSC_SDCR_D1 - mov.l SBSC_SDWCR_A, r1 - mov.l SBSC_SDWCR_D, r0 - mov.l r0, @r1 + write32 SBSC_SDWCR_A, SBSC_SDWCR_D - mov.l SBSC_SDPCR_A, r1 - mov.l SBSC_SDPCR_D, r0 - mov.l r0, @r1 + write32 SBSC_SDPCR_A, SBSC_SDPCR_D - mov.l SBSC_RTCSR_A, r1 - mov.l SBSC_RTCSR_D, r0 - mov.l r0, @r1 + write32 SBSC_RTCSR_A, SBSC_RTCSR_D - mov.l SBSC_RTCNT_A, r1 - mov.l SBSC_RTCNT_D, r0 - mov.l r0, @r1 + write32 SBSC_RTCNT_A, SBSC_RTCNT_D - mov.l SBSC_RTCOR_A, r1 - mov.l SBSC_RTCOR_D, r0 - mov.l r0, @r1 + write32 SBSC_RTCOR_A, SBSC_RTCOR_D - mov.l SBSC_SDMR3_A1, r1 - mov.l SBSC_SDMR3_D, r0 - mov.b r0, @r1 + write8 SBSC_SDMR3_A1, SBSC_SDMR3_D - mov.l SBSC_SDMR3_A2, r1 - mov.l SBSC_SDMR3_D, r0 - mov.b r0, @r1 + write8 SBSC_SDMR3_A2, SBSC_SDMR3_D mov.l SLEEP_CNT, r1 2: tst r1, r1 @@ -152,17 +99,11 @@ lowlevel_init: bf/s 2b dt r1 - mov.l SBSC_SDMR3_A3, r1 - mov.l SBSC_SDMR3_D, r0 - mov.b r0, @r1 + write8 SBSC_SDMR3_A3, SBSC_SDMR3_D - mov.l SBSC_SDCR_A, r1 - mov.l SBSC_SDCR_D2, r0 - mov.l r0, @r1 + write32 SBSC_SDCR_A, SBSC_SDCR_D2 - mov.l CCR_A, r1 - mov.l CCR_D, r0 - mov.l r0, @r1 + write32 CCR_A, CCR_D ! BL bit off (init = ON) (?!?) diff --git a/board/renesas/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S index a0573708d..2f6a9b74a 100644 --- a/board/renesas/r2dplus/lowlevel_init.S +++ b/board/renesas/r2dplus/lowlevel_init.S @@ -8,6 +8,7 @@ #include #include +#include .global lowlevel_init .text @@ -15,73 +16,39 @@ lowlevel_init: - mov.l CCR_A, r1 - mov.l CCR_D_D, r0 - mov.l r0, @r1 + write32 CCR_A, CCR_D_D - mov.l MMUCR_A, r1 - mov.l MMUCR_D, r0 - mov.l r0, @r1 + write32 MMUCR_A, MMUCR_D - mov.l BCR1_A, r1 - mov.l BCR1_D, r0 - mov.l r0, @r1 + write32 BCR1_A, BCR1_D - mov.l BCR2_A, r1 - mov.l BCR2_D, r0 - mov.w r0, @r1 + write16 BCR2_A, BCR2_D - mov.l BCR3_A, r1 - mov.l BCR3_D, r0 - mov.w r0, @r1 + write16 BCR3_A, BCR3_D - mov.l BCR4_A, r1 - mov.l BCR4_D, r0 - mov.l r0, @r1 + write32 BCR4_A, BCR4_D - mov.l WCR1_A, r1 - mov.l WCR1_D, r0 - mov.l r0, @r1 + write32 WCR1_A, WCR1_D - mov.l WCR2_A, r1 - mov.l WCR2_D, r0 - mov.l r0, @r1 + write32 WCR2_A, WCR2_D - mov.l WCR3_A, r1 - mov.l WCR3_D, r0 - mov.l r0, @r1 + write32 WCR3_A, WCR3_D - mov.l PCR_A, r1 - mov.l PCR_D, r0 - mov.w r0, @r1 + write16 PCR_A, PCR_D - mov.l LED_A, r1 - mov #0xff, r0 - mov.w r0, @r1 + write16 LED_A, #0xff - mov.l MCR_A, r1 - mov.l MCR_D1, r0 - mov.l r0, @r1 + write32 MCR_A, MCR_D1 - mov.l RTCNT_A, r1 - mov.l RTCNT_D, r0 - mov.w r0, @r1 + write16 RTCNT_A, RTCNT_D - mov.l RTCOR_A, r1 - mov.l RTCOR_D, r0 - mov.w r0, @r1 + write16 RTCOR_A, RTCOR_D - mov.l RFCR_A, r1 - mov.l RFCR_D, r0 - mov.w r0, @r1 + write16 RFCR_A, RFCR_D - mov.l RTCSR_A, r1 - mov.l RTCSR_D, r0 - mov.w r0, @r1 + write16 RTCSR_A, RTCSR_D - mov.l SDMR3_A, r1 - mov #0x55, r0 - mov.b r0, @r1 + write8 SDMR3_A, #0x55 /* Wait DRAM refresh 30 times */ mov.l RFCR_A, r1 @@ -92,21 +59,13 @@ lowlevel_init: cmp/hi r3, r2 bf 1b - mov.l MCR_A, r1 - mov.l MCR_D2, r0 - mov.l r0, @r1 + write32 MCR_A, MCR_D2 - mov.l SDMR3_A, r1 - mov #0, r0 - mov.b r0, @r1 + write8 SDMR3_A, #0 - mov.l IRLMASK_A, r1 - mov.l IRLMASK_D, r0 - mov.l r0, @r1 + write32 IRLMASK_A, IRLMASK_D - mov.l CCR_A, r1 - mov.l CCR_D_E, r0 - mov.l r0, @r1 + write32 CCR_A, CCR_D_E rts nop diff --git a/board/renesas/r7780mp/lowlevel_init.S b/board/renesas/r7780mp/lowlevel_init.S index 0df8c8410..bbea62192 100644 --- a/board/renesas/r7780mp/lowlevel_init.S +++ b/board/renesas/r7780mp/lowlevel_init.S @@ -22,6 +22,7 @@ #include #include #include +#include /* * Board specific low level init code, called _very_ early in the @@ -38,63 +39,36 @@ lowlevel_init: - mov.l CCR_A, r1 /* Address of Cache Control Register */ - mov.l CCR_D, r0 /* Instruction Cache Invalidate */ - mov.l r0, @r1 + write32 CCR_A, CCR_D /* Address of Cache Control Register */ + /* Instruction Cache Invalidate */ - mov.l FRQCR_A, r1 /* Frequency control register */ - mov.l FRQCR_D, r0 - mov.l r0, @r1 + write32 FRQCR_A, FRQCR_D /* Frequency control register */ /* pin_multi_setting */ - mov.l BBG_PMMR_A, r1 - mov.l BBG_PMMR_D_PMSR1, r0 - mov.l r0, @r1 + write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1 - mov.l BBG_PMSR1_A, r1 - mov.l BBG_PMSR1_D, r0 - mov.l r0, @r1 + write32 BBG_PMSR1_A, BBG_PMSR1_D - mov.l BBG_PMMR_A, r1 - mov.l BBG_PMMR_D_PMSR2, r0 - mov.l r0, @r1 + write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2 - mov.l BBG_PMSR2_A, r1 - mov.l BBG_PMSR2_D, r0 - mov.l r0, @r1 + write32 BBG_PMSR2_A, BBG_PMSR2_D - mov.l BBG_PMMR_A, r1 - mov.l BBG_PMMR_D_PMSR3, r0 - mov.l r0, @r1 + write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3 - mov.l BBG_PMSR3_A, r1 - mov.l BBG_PMSR3_D, r0 - mov.l r0, @r1 + write32 BBG_PMSR3_A, BBG_PMSR3_D - mov.l BBG_PMMR_A, r1 - mov.l BBG_PMMR_D_PMSR4, r0 - mov.l r0, @r1 + write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4 - mov.l BBG_PMSR4_A, r1 - mov.l BBG_PMSR4_D, r0 - mov.l r0, @r1 + write32 BBG_PMSR4_A, BBG_PMSR4_D - mov.l BBG_PMMR_A, r1 - mov.l BBG_PMMR_D_PMSRG, r0 - mov.l r0, @r1 + write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG - mov.l BBG_PMSRG_A, r1 - mov.l BBG_PMSRG_D, r0 - mov.l r0, @r1 + write32 BBG_PMSRG_A, BBG_PMSRG_D /* cpg_setting */ - mov.l FRQCR_A, r1 - mov.l FRQCR_D, r0 - mov.l r0, @r1 + write32 FRQCR_A, FRQCR_D - mov.l DLLCSR_A, r1 - mov.l DLLCSR_D, r0 - mov.l r0, @r1 + write32 DLLCSR_A, DLLCSR_D nop nop @@ -117,69 +91,37 @@ repeat0: nop /* bsc_setting */ - mov.l MMSELR_A, r1 - mov.l MMSELR_D, r0 - mov.l r0, @r1 + write32 MMSELR_A, MMSELR_D - mov.l BCR_A, r1 - mov.l BCR_D, r0 - mov.l r0, @r1 + write32 BCR_A, BCR_D - mov.l CS0BCR_A, r1 - mov.l CS0BCR_D, r0 - mov.l r0, @r1 + write32 CS0BCR_A, CS0BCR_D - mov.l CS1BCR_A, r1 - mov.l CS1BCR_D, r0 - mov.l r0, @r1 + write32 CS1BCR_A, CS1BCR_D - mov.l CS2BCR_A, r1 - mov.l CS2BCR_D, r0 - mov.l r0, @r1 + write32 CS2BCR_A, CS2BCR_D - mov.l CS4BCR_A, r1 - mov.l CS4BCR_D, r0 - mov.l r0, @r1 + write32 CS4BCR_A, CS4BCR_D - mov.l CS5BCR_A, r1 - mov.l CS5BCR_D, r0 - mov.l r0, @r1 + write32 CS5BCR_A, CS5BCR_D - mov.l CS6BCR_A, r1 - mov.l CS6BCR_D, r0 - mov.l r0, @r1 + write32 CS6BCR_A, CS6BCR_D - mov.l CS0WCR_A, r1 - mov.l CS0WCR_D, r0 - mov.l r0, @r1 + write32 CS0WCR_A, CS0WCR_D - mov.l CS1WCR_A, r1 - mov.l CS1WCR_D, r0 - mov.l r0, @r1 + write32 CS1WCR_A, CS1WCR_D - mov.l CS2WCR_A, r1 - mov.l CS2WCR_D, r0 - mov.l r0, @r1 + write32 CS2WCR_A, CS2WCR_D - mov.l CS4WCR_A, r1 - mov.l CS4WCR_D, r0 - mov.l r0, @r1 + write32 CS4WCR_A, CS4WCR_D - mov.l CS5WCR_A, r1 - mov.l CS5WCR_D, r0 - mov.l r0, @r1 + write32 CS5WCR_A, CS5WCR_D - mov.l CS6WCR_A, r1 - mov.l CS6WCR_D, r0 - mov.l r0, @r1 + write32 CS6WCR_A, CS6WCR_D - mov.l CS5PCR_A, r1 - mov.l CS5PCR_D, r0 - mov.l r0, @r1 + write32 CS5PCR_A, CS5PCR_D - mov.l CS6PCR_A, r1 - mov.l CS6PCR_D, r0 - mov.l r0, @r1 + write32 CS6PCR_A, CS6PCR_D /* ddr_setting */ /* wait 200us */ diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S index f6a62311d..7b9ecd89c 100644 --- a/board/renesas/rsk7203/lowlevel_init.S +++ b/board/renesas/rsk7203/lowlevel_init.S @@ -21,6 +21,7 @@ #include #include +#include .global lowlevel_init @@ -29,140 +30,76 @@ lowlevel_init: /* Cache setting */ - mov.l CCR1_A, r1 - mov.l CCR1_D, r0 - mov.l r0, @r1 + write32 CCR1_A ,CCR1_D /* ConfigurePortPins */ - mov.l PECRL3_A, r1 - mov.l PECRL3_D, r0 - mov.w r0, @r1 + write16 PECRL3_A, PECRL3_D - mov.l PCCRL4_A, r1 - mov.l PCCRL4_D0, r0 - mov.w r0, @r1 + write16 PCCRL4_A, PCCRL4_D0 - mov.l PECRL4_A, r1 - mov.l PECRL4_D0, r0 - mov.w r0, @r1 + write16 PECRL4_A, PECRL4_D0 - mov.l PEIORL_A, r1 - mov.l PEIORL_D0, r0 - mov.w r0, @r1 + write16 PEIORL_A, PEIORL_D0 - mov.l PCIORL_A, r1 - mov.l PCIORL_D, r0 - mov.w r0, @r1 + write16 PCIORL_A, PCIORL_D - mov.l PFCRH2_A, r1 - mov.l PFCRH2_D, r0 - mov.w r0, @r1 + write16 PFCRH2_A, PFCRH2_D - mov.l PFCRH3_A, r1 - mov.l PFCRH3_D, r0 - mov.w r0, @r1 + write16 PFCRH3_A, PFCRH3_D - mov.l PFCRH1_A, r1 - mov.l PFCRH1_D, r0 - mov.w r0, @r1 + write16 PFCRH1_A, PFCRH1_D - mov.l PFIORH_A, r1 - mov.l PFIORH_D, r0 - mov.w r0, @r1 + write16 PFIORH_A, PFIORH_D - mov.l PECRL1_A, r1 - mov.l PECRL1_D0, r0 - mov.w r0, @r1 + write16 PECRL1_A, PECRL1_D0 - mov.l PEIORL_A, r1 - mov.l PEIORL_D1, r0 - mov.w r0, @r1 + write16 PEIORL_A, PEIORL_D1 /* Configure Operating Frequency */ - mov.l WTCSR_A, r1 - mov.l WTCSR_D0, r0 - mov.w r0, @r1 + write16 WTCSR_A, WTCSR_D0 - mov.l WTCSR_A, r1 - mov.l WTCSR_D1, r0 - mov.w r0, @r1 + write16 WTCSR_A, WTCSR_D1 - mov.l WTCNT_A, r1 - mov.l WTCNT_D, r0 - mov.w r0, @r1 + write16 WTCNT_A, WTCNT_D /* Set clock mode*/ - mov.l FRQCR_A, r1 - mov.l FRQCR_D, r0 - mov.w r0, @r1 + write16 FRQCR_A, FRQCR_D /* Configure Bus And Memory */ init_bsc_cs0: - mov.l PCCRL4_A, r1 - mov.l PCCRL4_D1, r0 - mov.w r0, @r1 + write16 PCCRL4_A, PCCRL4_D1 - mov.l PECRL1_A, r1 - mov.l PECRL1_D1, r0 - mov.w r0, @r1 + write16 PECRL1_A, PECRL1_D1 - mov.l CMNCR_A, r1 - mov.l CMNCR_D, r0 - mov.l r0, @r1 + write32 CMNCR_A, CMNCR_D - mov.l SC0BCR_A, r1 - mov.l SC0BCR_D, r0 - mov.l r0, @r1 + write32 SC0BCR_A, SC0BCR_D - mov.l CS0WCR_A, r1 - mov.l CS0WCR_D, r0 - mov.l r0, @r1 + write32 CS0WCR_A, CS0WCR_D init_bsc_cs1: - mov.l PECRL4_A, r1 - mov.l PECRL4_D1, r0 - mov.w r0, @r1 + write16 PECRL4_A, PECRL4_D1 - mov.l CS1WCR_A, r1 - mov.l CS1WCR_D, r0 - mov.l r0, @r1 + write32 CS1WCR_A, CS1WCR_D init_sdram: - mov.l PCCRL2_A, r1 - mov.l PCCRL2_D, r0 - mov.w r0, @r1 + write16 PCCRL2_A, PCCRL2_D - mov.l PCCRL4_A, r1 - mov.l PCCRL4_D2, r0 - mov.w r0, @r1 + write16 PCCRL4_A, PCCRL4_D2 - mov.l PCCRL1_A, r1 - mov.l PCCRL1_D, r0 - mov.w r0, @r1 + write16 PCCRL1_A, PCCRL1_D - mov.l PCCRL3_A, r1 - mov.l PCCRL3_D, r0 - mov.w r0, @r1 + write16 PCCRL3_A, PCCRL3_D - mov.l CS3BCR_A, r1 - mov.l CS3BCR_D, r0 - mov.l r0, @r1 + write32 CS3BCR_A, CS3BCR_D - mov.l CS3WCR_A, r1 - mov.l CS3WCR_D, r0 - mov.l r0, @r1 + write32 CS3WCR_A, CS3WCR_D - mov.l SDCR_A, r1 - mov.l SDCR_D, r0 - mov.l r0, @r1 + write32 SDCR_A, SDCR_D - mov.l RTCOR_A, r1 - mov.l RTCOR_D, r0 - mov.l r0, @r1 + write32 RTCOR_A, RTCOR_D - mov.l RTCSR_A, r1 - mov.l RTCSR_D, r0 - mov.l r0, @r1 + write32 RTCSR_A, RTCSR_D /* wait 200us */ mov.l REPEAT_D, r3 diff --git a/board/renesas/sh7763rdp/lowlevel_init.S b/board/renesas/sh7763rdp/lowlevel_init.S index 715e75fe6..3747bf6f8 100644 --- a/board/renesas/sh7763rdp/lowlevel_init.S +++ b/board/renesas/sh7763rdp/lowlevel_init.S @@ -25,6 +25,7 @@ #include #include +#include .global lowlevel_init @@ -33,44 +34,33 @@ lowlevel_init: - mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */ - mov.l WDTCSR_D, r0 - mov.l r0, @r1 + write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */ - mov.l WDTST_A, r1 /* Watchdog Stop Time Register */ - mov.l WDTST_D, r0 - mov.l r0, @r1 + write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */ - mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */ - mov.l WDTBST_D, r0 - mov.l r0, @r1 + write32 WDTBST_A, WDTBST_D /* + * 0xFFCC0008 + * Watchdog Base Stop Time Register + */ - mov.l CCR_A, r1 /* Address of Cache Control Register */ - mov.l CCR_CACHE_ICI_D, r0 /* Instruction Cache Invalidate */ - mov.l r0, @r1 + write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */ + /* Instruction Cache Invalidate */ - mov.l MMUCR_A, r1 /* Address of MMU Control Register */ - mov.l MMU_CONTROL_TI_D, r0 /* TI == TLB Invalidate bit */ - mov.l r0, @r1 + write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */ + /* TI == TLB Invalidate bit */ - mov.l MSTPCR0_A, r1 /* Address of Power Control Register 0 */ - mov.l MSTPCR0_D, r0 - mov.l r0, @r1 + write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */ - mov.l MSTPCR1_A, r1 /*i Address of Power Control Register 1 */ - mov.l MSTPCR1_D, r0 - mov.l r0, @r1 + write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */ - mov.l RAMCR_A, r1 - mov.l RAMCR_D, r0 - mov.l r0, @r1 + write32 RAMCR_A, RAMCR_D mov.l MMSELR_A, r1 mov.l MMSELR_D, r0 synco mov.l r0, @r1 - mov.l @r1, r2 /* execute two reads after setting MMSELR*/ + mov.l @r1, r2 /* execute two reads after setting MMSELR */ mov.l @r1, r2 synco @@ -79,75 +69,47 @@ lowlevel_init: mov.l @r1, r0 synco - mov.l MIM8_A, r1 - mov.l MIM8_D, r0 - mov.l r0, @r1 + write32 MIM8_A, MIM8_D - mov.l MIMC_A, r1 - mov.l MIMC_D1, r0 - mov.l r0, @r1 + write32 MIMC_A, MIMC_D1 - mov.l STRC_A, r1 - mov.l STRC_D, r0 - mov.l r0, @r1 + write32 STRC_A, STRC_D - mov.l SDR4_A, r1 - mov.l SDR4_D, r0 - mov.l r0, @r1 + write32 SDR4_A, SDR4_D - mov.l MIMC_A, r1 - mov.l MIMC_D2, r0 - mov.l r0, @r1 + write32 MIMC_A, MIMC_D2 nop nop nop - mov.l SCR4_A, r1 - mov.l SCR4_D3, r0 - mov.l r0, @r1 + write32 SCR4_A, SCR4_D3 - mov.l SCR4_A, r1 - mov.l SCR4_D2, r0 - mov.l r0, @r1 + write32 SCR4_A, SCR4_D2 - mov.l SDMR02000_A, r1 - mov.l SDMR02000_D, r0 - mov.l r0, @r1 + write32 SDMR02000_A, SDMR02000_D - mov.l SDMR00B08_A, r1 - mov.l SDMR00B08_D, r0 - mov.l r0, @r1 + write32 SDMR00B08_A, SDMR00B08_D - mov.l SCR4_A, r1 - mov.l SCR4_D2, r0 - mov.l r0, @r1 + write32 SCR4_A, SCR4_D2 - mov.l SCR4_A, r1 - mov.l SCR4_D4, r0 - mov.l r0, @r1 + write32 SCR4_A, SCR4_D4 nop nop nop nop - mov.l SCR4_A, r1 - mov.l SCR4_D4, r0 - mov.l r0, @r1 + write32 SCR4_A, SCR4_D4 nop nop nop nop - mov.l SDMR00308_A, r1 - mov.l SDMR00308_D, r0 - mov.l r0, @r1 + write32 SDMR00308_A, SDMR00308_D - mov.l MIMC_A, r1 - mov.l MIMC_D3, r0 - mov.l r0, @r1 + write32 MIMC_A, MIMC_D3 mov.l SCR4_A, r1 mov.l SCR4_D1, r0 @@ -159,70 +121,38 @@ delay_loop_60: bf delay_loop_60 nop - mov.l CCR_A, r1 /* Address of Cache Control Register */ - mov.l CCR_CACHE_D_2, r0 - mov.l r0, @r1 + write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */ bsc_init: - mov.l BCR_A, r1 - mov.l BCR_D, r0 - mov.l r0, @r1 + write32 BCR_A, BCR_D - mov.l CS0BCR_A, r1 - mov.l CS0BCR_D, r0 - mov.l r0, @r1 + write32 CS0BCR_A, CS0BCR_D - mov.l CS1BCR_A, r1 - mov.l CS1BCR_D, r0 - mov.l r0, @r1 + write32 CS1BCR_A, CS1BCR_D - mov.l CS2BCR_A, r1 - mov.l CS2BCR_D, r0 - mov.l r0, @r1 + write32 CS2BCR_A, CS2BCR_D - mov.l CS4BCR_A, r1 - mov.l CS4BCR_D, r0 - mov.l r0, @r1 + write32 CS4BCR_A, CS4BCR_D - mov.l CS5BCR_A, r1 - mov.l CS5BCR_D, r0 - mov.l r0, @r1 + write32 CS5BCR_A, CS5BCR_D - mov.l CS6BCR_A, r1 - mov.l CS6BCR_D, r0 - mov.l r0, @r1 + write32 CS6BCR_A, CS6BCR_D - mov.l CS0WCR_A, r1 - mov.l CS0WCR_D, r0 - mov.l r0, @r1 + write32 CS0WCR_A, CS0WCR_D - mov.l CS1WCR_A, r1 - mov.l CS1WCR_D, r0 - mov.l r0, @r1 + write32 CS1WCR_A, CS1WCR_D - mov.l CS2WCR_A, r1 - mov.l CS2WCR_D, r0 - mov.l r0, @r1 + write32 CS2WCR_A, CS2WCR_D - mov.l CS4WCR_A, r1 - mov.l CS4WCR_D, r0 - mov.l r0, @r1 + write32 CS4WCR_A, CS4WCR_D - mov.l CS5WCR_A, r1 - mov.l CS5WCR_D, r0 - mov.l r0, @r1 + write32 CS5WCR_A, CS5WCR_D - mov.l CS6WCR_A, r1 - mov.l CS6WCR_D, r0 - mov.l r0, @r1 + write32 CS6WCR_A, CS6WCR_D - mov.l CS5PCR_A, r1 - mov.l CS5PCR_D, r0 - mov.l r0, @r1 + write32 CS5PCR_A, CS5PCR_D - mov.l CS6PCR_A, r1 - mov.l CS6PCR_D, r0 - mov.l r0, @r1 + write32 CS6PCR_A, CS6PCR_D mov.l DELAY200_D, r3 @@ -231,17 +161,11 @@ delay_loop_200: bf delay_loop_200 nop - mov.l PSEL0_A, r1 - mov.l PSEL0_D, r0 - mov.w r0, @r1 + write16 PSEL0_A, PSEL0_D - mov.l PSEL1_A, r1 - mov.l PSEL1_D, r0 - mov.w r0, @r1 + write16 PSEL1_A, PSEL1_D - mov.l ICR0_A, r1 - mov.l ICR0_D, r0 - mov.l r0, @r1 + write32 ICR0_A, ICR0_D stc sr, r0 /* BL bit off(init=ON) */ mov.l SR_MASK_D, r1 diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S index 4cb1d9d67..f5ebeb9a7 100644 --- a/board/renesas/sh7785lcr/lowlevel_init.S +++ b/board/renesas/sh7785lcr/lowlevel_init.S @@ -19,33 +19,7 @@ #include #include #include - -.macro write32, addr, data - mov.l \addr ,r1 - mov.l \data ,r0 - mov.l r0, @r1 -.endm - -.macro write16, addr, data - mov.l \addr ,r1 - mov.l \data ,r0 - mov.w r0, @r1 -.endm - -.macro write8, addr, data - mov.l \addr ,r1 - mov.l \data ,r0 - mov.b r0, @r1 -.endm - -.macro wait_timer, time - mov.l \time ,r3 -1: - nop - tst r3, r3 - bf/s 1b - dt r3 -.endm +#include #include diff --git a/include/asm-sh/macro.h b/include/asm-sh/macro.h new file mode 100644 index 000000000..61f792a04 --- /dev/null +++ b/include/asm-sh/macro.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MACRO_H__ +#define __MACRO_H__ +#ifdef __ASSEMBLY__ + +.macro write32, addr, data + mov.l \addr ,r1 + mov.l \data ,r0 + mov.l r0, @r1 +.endm + +.macro write16, addr, data + mov.l \addr ,r1 + mov.l \data ,r0 + mov.w r0, @r1 +.endm + +.macro write8, addr, data + mov.l \addr ,r1 + mov.l \data ,r0 + mov.b r0, @r1 +.endm + +.macro wait_timer, time + mov.l \time ,r3 +1: + nop + tst r3, r3 + bf/s 1b + dt r3 +.endm + +#endif /* __ASSEMBLY__ */ +#endif /* __MACRO_H__ */ From a5b04d00bfeb940c62232972ce644d50b45797f9 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Tue, 30 Dec 2008 01:16:03 +0000 Subject: [PATCH 111/188] sh: Fix up rsk7203 target for out of tree build Fix up rsk7203 target to build successfully using out-of-tree build. Signed-off-by: Kieran Bingham Signed-off-by: Nobuhiro Iwamatsu --- Makefile | 4 ++-- board/renesas/rsk7203/Makefile | 4 ++++ cpu/sh2/Makefile | 21 +++++++++++++-------- 3 files changed, 19 insertions(+), 10 deletions(-) diff --git a/Makefile b/Makefile index ecde92b4c..8fb1e2ae2 100644 --- a/Makefile +++ b/Makefile @@ -3230,8 +3230,8 @@ mimc200_config : unconfig ## sh2 (Renesas SuperH) ######################################################################### rsk7203_config: unconfig - @ >include/config.h - @echo "#define CONFIG_RSK7203 1" >> include/config.h + @mkdir -p $(obj)include + @echo "#define CONFIG_RSK7203 1" > $(obj)/include/config.h @$(MKCONFIG) -a $(@:_config=) sh sh2 rsk7203 renesas ######################################################################### diff --git a/board/renesas/rsk7203/Makefile b/board/renesas/rsk7203/Makefile index 7365d1930..5412010ae 100644 --- a/board/renesas/rsk7203/Makefile +++ b/board/renesas/rsk7203/Makefile @@ -26,6 +26,10 @@ LIB = lib$(BOARD).a OBJS := rsk7203.o SOBJS := lowlevel_init.o +LIB := $(addprefix $(obj),$(LIB)) +OBJS := $(addprefix $(obj),$(OBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) diff --git a/cpu/sh2/Makefile b/cpu/sh2/Makefile index e33ba0f2a..346d3285d 100644 --- a/cpu/sh2/Makefile +++ b/cpu/sh2/Makefile @@ -28,19 +28,24 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o -OBJS = cpu.o interrupts.o watchdog.o +SOBJS = start.o +COBJS = cpu.o interrupts.o watchdog.o -all: .depend $(START) $(LIB) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### -.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ - # defines $(obj).depend target include $(SRCTREE)/rules.mk From c9935c992575922b7ef13eec0656ed8665d324e3 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sun, 11 Jan 2009 17:48:56 +0900 Subject: [PATCH 112/188] sh: Fix compile error on lowlevel_init file lowlevel_init of SH was corrected to use the write/readXX macro. However, there was a problem that was not able to be compiled partially. This patch corrected this. Signed-off-by: Nobuhiro Iwamatsu --- board/ms7722se/lowlevel_init.S | 3 ++- board/ms7750se/lowlevel_init.S | 5 +++-- board/renesas/MigoR/lowlevel_init.S | 3 ++- board/renesas/r2dplus/lowlevel_init.S | 10 ++++++---- 4 files changed, 13 insertions(+), 8 deletions(-) diff --git a/board/ms7722se/lowlevel_init.S b/board/ms7722se/lowlevel_init.S index 9144e104b..1cb57e72e 100644 --- a/board/ms7722se/lowlevel_init.S +++ b/board/ms7722se/lowlevel_init.S @@ -131,7 +131,7 @@ bsc_init: write32 RTCSR_A, RTCSR_D - write8 SDMR3_A, #0x00 + write8 SDMR3_A, SDMR3_D ! BL bit off (init = ON) (?!?) @@ -225,6 +225,7 @@ RTCOR_D: .long 0xA55A0034 RTCSR_A: .long SBSC_RTCSR RTCSR_D: .long 0xA55A0010 SDMR3_A: .long 0xFE500180 +SDMR3_D: .long 0x0 .align 1 diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S index 710801978..5e09a39ba 100644 --- a/board/ms7750se/lowlevel_init.S +++ b/board/ms7750se/lowlevel_init.S @@ -84,7 +84,7 @@ init_bsc: write32 MCR_A, MCR_D1 /* Set SDRAM mode */ - write8 SDMR3_A, #0 + write8 SDMR3_A, SDMR3_D ! Do you need PCMCIA setting? ! If so, please add the lines here... @@ -108,7 +108,7 @@ init_bsc: write32 MCR_A, MCR_D2 /* Set SDRAM mode */ - write8 SDMR3_A, #0 + write8 SDMR3_A, SDMR3_D rts nop @@ -146,6 +146,7 @@ RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ RTCOR_A: .long RTCOR RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */ SDMR3_A: .long SDMR3_ADDRESS +SDMR3_D: .long 0x00 MCR_A: .long MCR MCR_D1: .long MCR_D1_VALUE MCR_D2: .long MCR_D2_VALUE diff --git a/board/renesas/MigoR/lowlevel_init.S b/board/renesas/MigoR/lowlevel_init.S index 1da603a9f..e32a7afb4 100644 --- a/board/renesas/MigoR/lowlevel_init.S +++ b/board/renesas/MigoR/lowlevel_init.S @@ -117,7 +117,7 @@ bsc_init: write32 RFCR_A, RFCR_D - write8 SDMR3_A, #0x00 + write8 SDMR3_A, SDMR3_D ! BL bit off (init = ON) (?!?) @@ -195,6 +195,7 @@ RFCR_A: .long SBSC_RFCR RFCR_D: .long 0xA55A0221 RTCSR_D: .long 0xA55A009a SDMR3_A: .long 0xFE581180 +SDMR3_D: .long 0x0 SR_MASK_D: .long 0xEFFFFF0F diff --git a/board/renesas/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S index 2f6a9b74a..76d3cfc40 100644 --- a/board/renesas/r2dplus/lowlevel_init.S +++ b/board/renesas/r2dplus/lowlevel_init.S @@ -36,7 +36,7 @@ lowlevel_init: write16 PCR_A, PCR_D - write16 LED_A, #0xff + write16 LED_A, LED_D write32 MCR_A, MCR_D1 @@ -48,7 +48,7 @@ lowlevel_init: write16 RTCSR_A, RTCSR_D - write8 SDMR3_A, #0x55 + write8 SDMR3_A, SDMR3_D0 /* Wait DRAM refresh 30 times */ mov.l RFCR_A, r1 @@ -61,7 +61,7 @@ lowlevel_init: write32 MCR_A, MCR_D2 - write8 SDMR3_A, #0 + write8 SDMR3_A, SDMR3_D1 write32 IRLMASK_A, IRLMASK_D @@ -92,6 +92,7 @@ WCR2_D: .long 0xcff86fbf WCR3_A: .long WCR3 /* WCR3 Address */ WCR3_D: .long 0x07777707 LED_A: .long 0x04000036 /* LED Address */ +LED_D: .long 0xFF /* LED Data */ RTCNT_A: .long RTCNT /* RTCNT Address */ RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ RTCOR_A: .long RTCOR /* RTCOR Address */ @@ -99,7 +100,8 @@ RTCOR_D: .long 0xA534 /* RTCOR Write Code */ RTCSR_A: .long RTCSR /* RTCSR Address */ RTCSR_D: .long 0xA510 /* RTCSR Write Code */ SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */ -SDMR3_D: .long 0x55 +SDMR3_D0: .long 0x55 +SDMR3_D1: .long 0x00 MCR_A: .long MCR /* MCR Address */ MCR_D1: .long 0x081901F4 /* MRSET:'0' */ MCR_D2: .long 0x481901F4 /* MRSET:'1' */ From 9e1fa628bdb64745811cdd26c4f953846c076180 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sun, 11 Jan 2009 16:35:15 +0100 Subject: [PATCH 113/188] sh: serial: coding style cleanup Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nobuhiro Iwamatsu --- drivers/serial/serial_sh.c | 35 ++++++++++++++++++----------------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 1d76a194a..e47ec2e27 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -49,7 +49,7 @@ # define SCFRDR (vu_char *)(SCIF_BASE + 0x24) #else # define SCFTDR (vu_char *)(SCIF_BASE + 0xC) -# define SCFSR (vu_short *)(SCIF_BASE + 0x10) +# define SCFSR (vu_short *)(SCIF_BASE + 0x10) # define SCFRDR (vu_char *)(SCIF_BASE + 0x14) #endif @@ -64,7 +64,7 @@ #elif defined(CONFIG_CPU_SH7763) # if defined(CONFIG_CONS_SCIF2) # define SCSPTR (vu_short *)(SCIF_BASE + 0x20) -# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +# define SCLSR (vu_short *)(SCIF_BASE + 0x24) # define LSR_ORER 1 # define FIFOLEVEL_MASK 0x1F # else @@ -90,7 +90,7 @@ defined(CONFIG_CPU_SH7722) || \ defined(CONFIG_CPU_SH7203) # define SCSPTR (vu_short *)(SCIF_BASE + 0x20) -# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +# define SCLSR (vu_short *)(SCIF_BASE + 0x24) # define LSR_ORER 1 # define FIFOLEVEL_MASK 0x1F #elif defined(CONFIG_CPU_SH7720) @@ -106,31 +106,32 @@ /* SCBRR register value setting */ #if defined(CONFIG_CPU_SH7720) -# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) +# define SCBRR_VALUE(bps, clk) (((clk * 2) + 16 * bps) / (32 * bps) - 1) #elif defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A) /* SH7723 SCIFA use bus clock. So clock *2 */ -# define SCBRR_VALUE(bps, clk) (((clk*2*2)+16*bps)/(32*bps)-1) +# define SCBRR_VALUE(bps, clk) (((clk * 2 * 2) + 16 * bps) / (32 * bps) - 1) #else /* Generic SuperH */ -# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) +# define SCBRR_VALUE(bps, clk) ((clk + 16 * bps) / (32 * bps) - 1) #endif -#define SCR_RE (1 << 4) -#define SCR_TE (1 << 5) +#define SCR_RE (1 << 4) +#define SCR_TE (1 << 5) #define FCR_RFRST (1 << 1) /* RFCL */ #define FCR_TFRST (1 << 2) /* TFCL */ -#define FSR_DR (1 << 0) -#define FSR_RDF (1 << 1) -#define FSR_FER (1 << 3) -#define FSR_BRK (1 << 4) -#define FSR_FER (1 << 3) -#define FSR_TEND (1 << 6) -#define FSR_ER (1 << 7) +#define FSR_DR (1 << 0) +#define FSR_RDF (1 << 1) +#define FSR_FER (1 << 3) +#define FSR_BRK (1 << 4) +#define FSR_FER (1 << 3) +#define FSR_TEND (1 << 6) +#define FSR_ER (1 << 7) /*----------------------------------------------------------------------*/ void serial_setbrg(void) { DECLARE_GLOBAL_DATA_PTR; + *SCBRR = SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ); } @@ -191,8 +192,8 @@ int serial_tstc(void) return serial_rx_fifo_level() ? 1 : 0; } -#define FSR_ERR_CLEAR 0x0063 -#define RDRF_CLEAR 0x00fc +#define FSR_ERR_CLEAR 0x0063 +#define RDRF_CLEAR 0x00fc void handle_error(void) { From fc83c9273cec6e6e542f4a0ea3b653b7d0513ffa Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sun, 11 Jan 2009 16:35:16 +0100 Subject: [PATCH 114/188] sh: serial: use readx/writex accessors Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nobuhiro Iwamatsu --- drivers/serial/serial_sh.c | 46 +++++++++++++++++++------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index e47ec2e27..bfdb2ce77 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -18,6 +18,7 @@ */ #include +#include #include #if defined(CONFIG_CONS_SCIF0) @@ -132,17 +133,17 @@ void serial_setbrg(void) { DECLARE_GLOBAL_DATA_PTR; - *SCBRR = SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ); + writeb(SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ), SCBRR); } int serial_init(void) { - *SCSCR = (SCR_RE | SCR_TE); - *SCSMR = 0; - *SCSMR = 0; - *SCFCR = (FCR_RFRST | FCR_TFRST); - *SCFCR; - *SCFCR = 0; + writew((SCR_RE | SCR_TE), SCSCR); + writew(0, SCSMR); + writew(0, SCSMR); + writew((FCR_RFRST | FCR_TFRST), SCFCR); + readw(SCFCR); + writew(0, SCFCR); serial_setbrg(); return 0; @@ -151,9 +152,9 @@ int serial_init(void) static int serial_rx_fifo_level(void) { #if defined(SCRFDR) - return (*SCRFDR >> 0) & FIFOLEVEL_MASK; + return (readw(SCRFDR) >> 0) & FIFOLEVEL_MASK; #else - return (*SCFDR >> 0) & FIFOLEVEL_MASK; + return (readw(SCFDR) >> 0) & FIFOLEVEL_MASK; #endif } @@ -162,15 +163,15 @@ void serial_raw_putc(const char c) unsigned int fsr_bits_to_clear; while (1) { - if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */ + if (readw(SCFSR) & FSR_TEND) { /* Tx fifo is empty */ fsr_bits_to_clear = FSR_TEND; break; } } - *SCFTDR = c; + writeb(c, SCFTDR); if (fsr_bits_to_clear != 0) - *SCFSR &= ~fsr_bits_to_clear; + writew(readw(SCFSR) & ~fsr_bits_to_clear, SCFSR); } void serial_putc(const char c) @@ -196,22 +197,21 @@ int serial_tstc(void) #define RDRF_CLEAR 0x00fc void handle_error(void) { - - (void)*SCFSR; - *SCFSR = FSR_ERR_CLEAR; - (void)*SCLSR; - *SCLSR = 0x00; + readw(SCFSR); + writew(FSR_ERR_CLEAR, SCFSR); + readw(SCLSR); + writew(0x00, SCLSR); } int serial_getc_check(void) { unsigned short status; - status = *SCFSR; + status = readw(SCFSR); if (status & (FSR_FER | FSR_ER | FSR_BRK)) handle_error(); - if (*SCLSR & LSR_ORER) + if (readw(SCLSR) & LSR_ORER) handle_error(); return status & (FSR_DR | FSR_RDF); } @@ -224,15 +224,15 @@ int serial_getc(void) while (!serial_getc_check()) ; - ch = *SCFRDR; - status = *SCFSR; + ch = readb(SCFRDR); + status = readw(SCFSR); - *SCFSR = RDRF_CLEAR; + writew(RDRF_CLEAR, SCFSR); if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK)) handle_error(); - if (*SCLSR & LSR_ORER) + if (readw(SCLSR) & LSR_ORER) handle_error(); return ch; From fadad1573fb16c90025f08a2861d6047d093cba7 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 9 Jan 2009 04:38:17 -0500 Subject: [PATCH 115/188] ncb: use socklen_t The recvfrom() function takes a socklen_t, not an int. Signed-off-by: Mike Frysinger --- tools/ncb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/ncb.c b/tools/ncb.c index 74deebb65..7e123f163 100644 --- a/tools/ncb.c +++ b/tools/ncb.c @@ -8,7 +8,7 @@ int main (int argc, char *argv[]) int s, len, o, port = 6666; char buf[512]; struct sockaddr_in addr; - int addr_len = sizeof addr; + socklen_t addr_len = sizeof addr; if (argc > 1) port = atoi (argv[1]); From c088a108c75db565e07292fd668dfa5491e85bc2 Mon Sep 17 00:00:00 2001 From: Peter Korsgaard Date: Wed, 14 Jan 2009 13:52:24 +0100 Subject: [PATCH 116/188] fdt_resize(): fix actualsize calculations with unaligned blobs The code in fdt_resize() to extend the fdt size to end on a page boundary is wrong for fdt's not located at an address aligned on a page boundary. What's even worse, the code would make actualsize shrink rather than grow if (blob & 0xfff) was bigger than the amount of padding added by ALIGN(), causing fdt_add_mem_rsv to fail. Fix it by aligning end address (blob + size) to a page boundary instead. For aligned fdt's this is equivalent to what we had before. Signed-off-by: Peter Korsgaard --- common/fdt_support.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index 5a83bca48..a79bc085b 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -610,7 +610,7 @@ int fdt_resize(void *blob) fdt_size_dt_strings(blob) + sizeof(struct fdt_reserve_entry); /* Make it so the fdt ends on a page boundary */ - actualsize = ALIGN(actualsize, 0x1000); + actualsize = ALIGN(actualsize + ((uint)blob & 0xfff), 0x1000); actualsize = actualsize - ((uint)blob & 0xfff); /* Change the fdt header to reflect the correct size */ From 4cda437898f7873752f0201757cd33f12196ce87 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sat, 17 Jan 2009 13:32:42 -0500 Subject: [PATCH 117/188] build system: treat all Darwin's alike The x86 based version of Darwin behaves the same quirky way as the powerpc Darwin, so only check HOSTOS when setting up Darwin workarounds. Signed-off-by: Mike Frysinger --- config.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/config.mk b/config.mk index d770f09f9..b1254e904 100644 --- a/config.mk +++ b/config.mk @@ -46,7 +46,7 @@ PLATFORM_LDFLAGS = ######################################################################### -ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) +ifeq ($(HOSTOS),darwin) HOSTCC = cc else HOSTCC = gcc @@ -181,7 +181,7 @@ endif # # So far, this is used only by tools/gdb/Makefile. -ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) +ifeq ($(HOSTOS),darwin) BFD_ROOT_DIR = /usr/local/tools else ifeq ($(HOSTARCH),$(ARCH)) From 635e5f8fc82365e6e9734b3132bc95135a6de679 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 18 Jan 2009 21:37:48 +0100 Subject: [PATCH 118/188] Prepare 2009.01-rc3 Update CHANGELOG Signed-off-by: Wolfgang Denk --- CHANGELOG | 176 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ Makefile | 2 +- 2 files changed, 177 insertions(+), 1 deletion(-) diff --git a/CHANGELOG b/CHANGELOG index 17c569167..e582ced93 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,128 @@ +commit 4cda437898f7873752f0201757cd33f12196ce87 +Author: Mike Frysinger +Date: Sat Jan 17 13:32:42 2009 -0500 + + build system: treat all Darwin's alike + + The x86 based version of Darwin behaves the same quirky way as the powerpc + Darwin, so only check HOSTOS when setting up Darwin workarounds. + + Signed-off-by: Mike Frysinger + +commit c088a108c75db565e07292fd668dfa5491e85bc2 +Author: Peter Korsgaard +Date: Wed Jan 14 13:52:24 2009 +0100 + + fdt_resize(): fix actualsize calculations with unaligned blobs + + The code in fdt_resize() to extend the fdt size to end on a page boundary + is wrong for fdt's not located at an address aligned on a page boundary. + What's even worse, the code would make actualsize shrink rather than grow + if (blob & 0xfff) was bigger than the amount of padding added by ALIGN(), + causing fdt_add_mem_rsv to fail. + + Fix it by aligning end address (blob + size) to a page boundary instead. + For aligned fdt's this is equivalent to what we had before. + + Signed-off-by: Peter Korsgaard + +commit fadad1573fb16c90025f08a2861d6047d093cba7 +Author: Mike Frysinger +Date: Fri Jan 9 04:38:17 2009 -0500 + + ncb: use socklen_t + + The recvfrom() function takes a socklen_t, not an int. + + Signed-off-by: Mike Frysinger + +commit fc83c9273cec6e6e542f4a0ea3b653b7d0513ffa +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sun Jan 11 16:35:16 2009 +0100 + + sh: serial: use readx/writex accessors + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Nobuhiro Iwamatsu + +commit 9e1fa628bdb64745811cdd26c4f953846c076180 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sun Jan 11 16:35:15 2009 +0100 + + sh: serial: coding style cleanup + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Nobuhiro Iwamatsu + +commit c9935c992575922b7ef13eec0656ed8665d324e3 +Author: Nobuhiro Iwamatsu +Date: Sun Jan 11 17:48:56 2009 +0900 + + sh: Fix compile error on lowlevel_init file + + lowlevel_init of SH was corrected to use the write/readXX macro. + However, there was a problem that was not able to be compiled partially. + This patch corrected this. + + Signed-off-by: Nobuhiro Iwamatsu + +commit a5b04d00bfeb940c62232972ce644d50b45797f9 +Author: Kieran Bingham +Date: Tue Dec 30 01:16:03 2008 +0000 + + sh: Fix up rsk7203 target for out of tree build + + Fix up rsk7203 target to build successfully using out-of-tree build. + + Signed-off-by: Kieran Bingham + Signed-off-by: Nobuhiro Iwamatsu + +commit f7e78f3b74aae9caca2997bad865a72338326c0a +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sat Dec 20 19:29:49 2008 +0100 + + sh: use write{8,16,32} in all lowlevel_init + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Nobuhiro Iwamatsu + +commit e4430779623af500de1cee7892c379f07ef59813 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sat Dec 20 19:29:48 2008 +0100 + + sh: lowlevel_init coding style cleanup + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Nobuhiro Iwamatsu + +commit 85cb052ee41675ca361e6a4c69455dc715c8f2d9 +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sat Dec 20 15:27:45 2008 +0100 + + sh: update sh2/sh2a timer coding style + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Nobuhiro Iwamatsu + +commit 1e15ff999322e81af4c0c0c548908f38944ba39c +Author: Jean-Christophe PLAGNIOL-VILLARD +Date: Sat Dec 20 15:25:22 2008 +0100 + + sh: update sh timer coding style + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD + Signed-off-by: Nobuhiro Iwamatsu + +commit 0e3ece33801e377be67ffa29f083421ad820f28b +Author: Wolfgang Denk +Date: Wed Jan 14 23:26:05 2009 +0100 + + Prepare 2009.01-rc2 + + Update CHANGELOG. + + Signed-off-by: Wolfgang Denk + commit e92c9a860e44c14513c8909ce4299e253a775eeb Author: Wolfgang Denk Date: Wed Jan 14 22:35:30 2009 +0100 @@ -12,6 +137,57 @@ Date: Wed Jan 14 22:35:30 2009 +0100 Signed-off-by: Wolfgang Denk +commit 3ba605d4beec649438539e7df97b5fedb26592fb +Author: Matthias Fuchs +Date: Fri Jan 2 12:18:49 2009 +0100 + + ppc4xx: Add loadpci command to esd's CPCI4052 and CPCI405AB boards + + This patch adds esd's loadpci BSP command to CPCI4052 and + CPCI405AB board. This requires CONFIG_CMD_BSP and CONFIG_PRAM. + + Signed-off-by: Matthias Fuchs + Signed-off-by: Stefan Roese + +commit 600fe46fb3dab7f07604f9009904f31584415114 +Author: Matthias Fuchs +Date: Fri Jan 2 12:18:12 2009 +0100 + + ppc4xx: Disable pci node in device tree on CPCI405 pci adapters + + Signed-off-by: Matthias Fuchs + Signed-off-by: Stefan Roese + +commit f6a1f490d224c600a09137e58d1026d150b8e679 +Author: Matthias Fuchs +Date: Fri Jan 2 12:17:36 2009 +0100 + + ppc4xx: Cleanup CPCI405 board code + + This patch cleans up CPCI405 board support: + - wrap long lines + - unification of spaces in function calls + - remove dead code + + Use correct io accessors on peripherals. + + Signed-off-by: Matthias Fuchs + Signed-off-by: Stefan Roese + +commit fceebb45a0b97e92f9889861f8c3b9cb885e706f +Author: Matthias Fuchs +Date: Fri Jan 2 12:16:35 2009 +0100 + + ppc4xx: Enable auto RS485 mode on PLU405 boards + + This patch turns on the auto RS485 mode in the 2nd external + uart on PLU405 boards. This is a special mode of the used + Exar XR16C2850 uart. Because these boards only have a 485 physical + layer connected it's a good idea to turn it on by default. + + Signed-off-by: Matthias Fuchs + Signed-off-by: Stefan Roese + commit b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6 Author: Haiying Wang Date: Tue Jan 13 16:29:28 2009 -0500 diff --git a/Makefile b/Makefile index 8fb1e2ae2..9c63643e6 100644 --- a/Makefile +++ b/Makefile @@ -24,7 +24,7 @@ VERSION = 2009 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc3 ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else From 72d15e705bc3983884105cb7755c7ba80e74a0a5 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 21 Jan 2009 23:08:12 +0100 Subject: [PATCH 119/188] Prepare v2009.01 Signed-off-by: Wolfgang Denk --- CHANGELOG | 10 ++++++++++ Makefile | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/CHANGELOG b/CHANGELOG index e582ced93..bd3a7b76d 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,13 @@ +commit 635e5f8fc82365e6e9734b3132bc95135a6de679 +Author: Wolfgang Denk +Date: Sun Jan 18 21:37:48 2009 +0100 + + Prepare 2009.01-rc3 + + Update CHANGELOG + + Signed-off-by: Wolfgang Denk + commit 4cda437898f7873752f0201757cd33f12196ce87 Author: Mike Frysinger Date: Sat Jan 17 13:32:42 2009 -0500 diff --git a/Makefile b/Makefile index 9c63643e6..d533564d9 100644 --- a/Makefile +++ b/Makefile @@ -24,7 +24,7 @@ VERSION = 2009 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc3 +EXTRAVERSION = ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else From 455a46915b82896cc2070eb326d075555c2bc580 Mon Sep 17 00:00:00 2001 From: Ron Madrid Date: Fri, 12 Dec 2008 13:12:45 -0800 Subject: [PATCH 120/188] mpc83xx: Size optimization of start.S Currently there are in excess of 100 bytes located at the beginning of the image built by start.S that are not being utilized. This patch moves a few functions into this part of the image. This will create a greater number of *available* bytes that can be used by board specific code in NAND builds and will decrease the size of the assembled code in other builds. Signed-off-by: Ron Madrid Signed-off-by: Kim Phillips --- cpu/mpc83xx/start.S | 77 +++++++++++++++++++++++---------------------- 1 file changed, 39 insertions(+), 38 deletions(-) diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 792b2c8b2..beebc9951 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -109,6 +109,45 @@ version_string: .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" .ascii " ", CONFIG_IDENT_STRING, "\0" + .align 2 + + .globl enable_addr_trans +enable_addr_trans: + /* enable address translation */ + mfmsr r5 + ori r5, r5, (MSR_IR | MSR_DR) + mtmsr r5 + isync + blr + + .globl disable_addr_trans +disable_addr_trans: + /* disable address translation */ + mflr r4 + mfmsr r3 + andi. r0, r3, (MSR_IR | MSR_DR) + beqlr + andc r3, r3, r0 + mtspr SRR0, r4 + mtspr SRR1, r3 + rfi + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + + .globl ppcDWstore +ppcDWstore: + lfd 1, 0(r4) + stfd 1, 0(r3) + blr + + .globl ppcDWload +ppcDWload: + lfd 1, 0(r3) + stfd 1, 0(r4) + blr #ifndef CONFIG_DEFAULT_IMMR #error CONFIG_DEFAULT_IMMR must be defined @@ -698,27 +737,6 @@ setup_bats: blr - .globl enable_addr_trans -enable_addr_trans: - /* enable address translation */ - mfmsr r5 - ori r5, r5, (MSR_IR | MSR_DR) - mtmsr r5 - isync - blr - - .globl disable_addr_trans -disable_addr_trans: - /* disable address translation */ - mflr r4 - mfmsr r3 - andi. r0, r3, (MSR_IR | MSR_DR) - beqlr - andc r3, r3, r0 - mtspr SRR0, r4 - mtspr SRR1, r3 - rfi - /* Cache functions. * * Note: requires that all cache bits in @@ -796,23 +814,6 @@ flush_dcache: b 1b 2: blr - .globl get_pvr -get_pvr: - mfspr r3, PVR - blr - - .globl ppcDWstore -ppcDWstore: - lfd 1, 0(r4) - stfd 1, 0(r3) - blr - - .globl ppcDWload -ppcDWload: - lfd 1, 0(r3) - stfd 1, 0(r4) - blr - /*-------------------------------------------------------------------*/ /* From 75f35209f702bb26826855ed8c8e4d108ab5f412 Mon Sep 17 00:00:00 2001 From: Ira Snyder Date: Mon, 12 Jan 2009 13:32:26 -0800 Subject: [PATCH 121/188] 83xx: PCI agent mode fixes for multi-board systems When running a system with 2 or more MPC8349EMDS boards in PCI agent mode, the boards will lock up the PCI bus by scanning against each other. The boards lock against each other by trying to access the PCI bus before clearing their configuration lock bit. Both boards end up in a loop, sending and receiving "Target Not Ready" messages forever. When running in PCI agent mode, the scanning now takes place after the boards have cleared their configuration lock bit. Also, add a missing declaration to the mpc83xx.h header file, fixing a build warning. Signed-off-by: Ira W. Snyder Signed-off-by: Kim Phillips --- cpu/mpc83xx/pci.c | 5 +++++ include/mpc83xx.h | 1 + 2 files changed, 6 insertions(+) diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c index ab0760bce..e9965d7df 100644 --- a/cpu/mpc83xx/pci.c +++ b/cpu/mpc83xx/pci.c @@ -118,10 +118,12 @@ static void pci_init_bus(int bus, struct pci_region *reg) #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif +#ifndef CONFIG_PCISLAVE /* * Hose scan. */ hose->last_busno = pci_hose_scan(hose); +#endif } /* @@ -190,6 +192,9 @@ void mpc83xx_pcislave_unlock(int bus) pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, ®16); reg16 &= ~(PCI_FUNCTION_CFG_LOCK); pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16); + + /* The configuration bit is now unlocked, so we can scan the bus */ + hose->last_busno = pci_hose_scan(hose); } #endif diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 43553f5ae..e5dfe3f21 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -1173,6 +1173,7 @@ #ifndef __ASSEMBLY__ struct pci_region; void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot); +void mpc83xx_pcislave_unlock(int bus); #endif #endif /* __MPC83XX_H__ */ From 88ecf55cabd7aea28fe8093720e208f53ccfdcf5 Mon Sep 17 00:00:00 2001 From: Ira Snyder Date: Mon, 12 Jan 2009 13:33:17 -0800 Subject: [PATCH 122/188] MPC8349EMDS: do not setup unused PCI clock outputs in PCI agent mode When running in PCI agent mode, the PCI_CLK_OUT signals are not used, so do not enable them. See the MPC8349EA Reference Manual, Section 4.4.2 "Clocking in PCI Agent Mode". Signed-off-by: Ira W. Snyder Signed-off-by: Kim Phillips --- board/freescale/mpc8349emds/pci.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c index ad7bf5d50..af0b1da13 100644 --- a/board/freescale/mpc8349emds/pci.c +++ b/board/freescale/mpc8349emds/pci.c @@ -171,15 +171,10 @@ void pci_init_board(void) void pci_init_board(void) { volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0]; struct pci_region *reg[] = { pci1_regions }; - /* Enable all 8 PCI_CLK_OUTPUTS */ - clk->occr = 0xff000000; - udelay(2000); - /* Configure PCI Local Access Windows */ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; @@ -187,8 +182,6 @@ void pci_init_board(void) pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; - udelay(2000); - mpc83xx_pci_init(1, reg, 0); /* Configure PCI Inbound Translation Windows (3 1MB windows) */ From fd6646c0b9ebe7e5afc4ae4c78097d9cd317a5e8 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 8 Jan 2009 04:26:12 +0300 Subject: [PATCH 123/188] mpc83xx: Add support for MPC83xx PCI-E controllers This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li Signed-off-by: Anton Vorontsov Acked-by: Dave Liu Signed-off-by: Kim Phillips --- cpu/mpc83xx/Makefile | 1 + cpu/mpc83xx/pcie.c | 314 ++++++++++++++++++++++++++++++++++ cpu/mpc83xx/speed.c | 4 +- include/asm-ppc/global_data.h | 2 +- include/asm-ppc/immap_83xx.h | 119 ++++++++++++- include/mpc83xx.h | 67 ++++++-- include/pci.h | 4 + 7 files changed, 488 insertions(+), 23 deletions(-) create mode 100644 cpu/mpc83xx/pcie.c diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile index fcb6a5246..dd35e6bf8 100644 --- a/cpu/mpc83xx/Makefile +++ b/cpu/mpc83xx/Makefile @@ -39,6 +39,7 @@ COBJS-y += ecc.o COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_FSL_SERDES) += serdes.o COBJS-$(CONFIG_83XX_GENERIC_PCI) += pci.o +COBJS-$(CONFIG_83XX_GENERIC_PCIE) += pcie.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS := $(COBJS-y) diff --git a/cpu/mpc83xx/pcie.c b/cpu/mpc83xx/pcie.c new file mode 100644 index 000000000..02150bafd --- /dev/null +++ b/cpu/mpc83xx/pcie.c @@ -0,0 +1,314 @@ +/* + * Copyright (C) 2007-2009 Freescale Semiconductor, Inc. + * Copyright (C) 2008-2009 MontaVista Software, Inc. + * + * Authors: Tony Li + * Anton Vorontsov + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define PCIE_MAX_BUSES 2 + +#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES + +static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) +{ + int bus = PCI_BUS(dev) - hose->first_busno; + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + pex83xx_t *pex = &immr->pciexp[bus]; + struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0]; + u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev); + u32 dev_base = bus << 24 | devfn << 16; + + if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK) + return -1; + /* + * Workaround for the HW bug: for Type 0 configure transactions the + * PCI-E controller does not check the device number bits and just + * assumes that the device number bits are 0. + */ + if (devfn & 0xf8) + return -1; + + out_le32(&out_win->tarl, dev_base); + return 0; +} + +#define cfg_read(val, addr, type, op) \ + do { *val = op((type)(addr)); } while (0) +#define cfg_write(val, addr, type, op) \ + do { op((type *)(addr), (val)); } while (0) + +#define PCIE_OP(rw, size, type, op) \ +static int pcie_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, \ + type val) \ +{ \ + int ret; \ + \ + ret = mpc83xx_pcie_remap_cfg(hose, dev); \ + if (ret) \ + return ret; \ + cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \ + return 0; \ +} + +PCIE_OP(read, byte, u8 *, in_8) +PCIE_OP(read, word, u16 *, in_le16) +PCIE_OP(read, dword, u32 *, in_le32) +PCIE_OP(write, byte, u8, out_8) +PCIE_OP(write, word, u16, out_le16) +PCIE_OP(write, dword, u32, out_le32) + +static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, + u8 link) +{ + extern void disable_addr_trans(void); /* start.S */ + static struct pci_controller pcie_hose[PCIE_MAX_BUSES]; + static int max_bus; + struct pci_controller *hose = &pcie_hose[bus]; + int i; + + /* + * There are no spare BATs to remap all PCI-E windows for U-Boot, so + * disable translations. In general, this is not great solution, and + * that's why we don't register PCI-E hoses by default. + */ + disable_addr_trans(); + + for (i = 0; i < 2; i++, reg++) { + if (reg->size == 0) + break; + + hose->regions[i] = *reg; + hose->region_count++; + } + + i = hose->region_count++; + hose->regions[i].bus_start = 0; + hose->regions[i].phys_start = 0; + hose->regions[i].size = gd->ram_size; + hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY; + + i = hose->region_count++; + hose->regions[i].bus_start = CONFIG_SYS_IMMR; + hose->regions[i].phys_start = CONFIG_SYS_IMMR; + hose->regions[i].size = 0x100000; + hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY; + + hose->first_busno = max_bus; + hose->last_busno = 0xff; + + if (bus == 0) + hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE1_CFG_BASE; + else + hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE2_CFG_BASE; + + pci_set_ops(hose, + pcie_read_config_byte, + pcie_read_config_word, + pcie_read_config_dword, + pcie_write_config_byte, + pcie_write_config_word, + pcie_write_config_dword); + + if (!link) + hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK; + + pci_register_hose(hose); + +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); + max_bus = hose->last_busno + 1; +} + +#else + +static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, + u8 link) {} + +#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */ + +static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + pex83xx_t *pex = &immr->pciexp[bus]; + struct pex_outbound_window *out_win; + struct pex_inbound_window *in_win; + void *hose_cfg_base; + unsigned int ram_sz; + unsigned int barl; + unsigned int tar; + u16 reg16; + int i; + + /* Enable pex csb bridge inbound & outbound transactions */ + out_le32(&pex->bridge.pex_csb_ctrl, + in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE | + PEX_CSB_CTRL_IBPIOE); + + /* Enable bridge outbound */ + out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE | + PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE | + PEX_CSB_OBCTRL_CFGWE); + + out_win = &pex->bridge.pex_outbound_win[0]; + if (bus) { + out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG | + CONFIG_SYS_PCIE2_CFG_SIZE); + out_le32(&out_win->bar, CONFIG_SYS_PCIE2_CFG_BASE); + } else { + out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG | + CONFIG_SYS_PCIE1_CFG_SIZE); + out_le32(&out_win->bar, CONFIG_SYS_PCIE1_CFG_BASE); + } + out_le32(&out_win->tarl, 0); + out_le32(&out_win->tarh, 0); + + for (i = 0; i < 2; i++, reg++) { + u32 ar; + + if (reg->size == 0) + break; + + out_win = &pex->bridge.pex_outbound_win[i + 1]; + out_le32(&out_win->bar, reg->phys_start); + out_le32(&out_win->tarl, reg->bus_start); + out_le32(&out_win->tarh, 0); + ar = PEX_OWAR_EN | (reg->size & PEX_OWAR_SIZE); + if (reg->flags & PCI_REGION_IO) + ar |= PEX_OWAR_TYPE_IO; + else + ar |= PEX_OWAR_TYPE_MEM; + out_le32(&out_win->ar, ar); + } + + out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE); + + ram_sz = gd->ram_size; + barl = 0; + tar = 0; + i = 0; + while (ram_sz > 0) { + in_win = &pex->bridge.pex_inbound_win[i]; + out_le32(&in_win->barl, barl); + out_le32(&in_win->barh, 0x0); + out_le32(&in_win->tar, tar); + if (ram_sz >= 0x10000000) { + /* The maxium windows size is 256M */ + out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV | + PEX_IWAR_TYPE_PF | 0x0FFFF000); + barl += 0x10000000; + tar += 0x10000000; + ram_sz -= 0x10000000; + } else { + /* The UM is not clear here. + * So, round up to even Mb boundary */ + + ram_sz = ram_sz >> (20 + + ((ram_sz & 0xFFFFF) ? 1 : 0)); + if (!(ram_sz % 2)) + ram_sz -= 1; + out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV | + PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000); + ram_sz = 0; + } + i++; + } + + in_win = &pex->bridge.pex_inbound_win[i]; + out_le32(&in_win->barl, CONFIG_SYS_IMMR); + out_le32(&in_win->barh, 0); + out_le32(&in_win->tar, CONFIG_SYS_IMMR); + out_le32(&in_win->ar, PEX_IWAR_EN | + PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M); + + /* Enable the host virtual INTX interrupts */ + out_le32(&pex->bridge.pex_int_axi_misc_enb, + in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0); + + /* Hose configure header is memory-mapped */ + hose_cfg_base = (void *)pex; + + get_clocks(); + /* Configure the PCIE controller core clock ratio */ + out_le32(hose_cfg_base + PEX_GCLK_RATIO, + (((bus ? gd->pciexp2_clk : gd->pciexp1_clk) / 1000000) * 16) + / 333); + udelay(1000000); + + /* Do Type 1 bridge configuration */ + out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0); + out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1); + out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255); + + /* + * Write to Command register + */ + reg16 = in_le16(hose_cfg_base + PCI_COMMAND); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO | + PCI_COMMAND_SERR | PCI_COMMAND_PARITY; + out_le16(hose_cfg_base + PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + out_le16(hose_cfg_base + PCI_STATUS, 0xffff); + out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80); + out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08); + + printf("PCIE%d: ", bus); + + reg16 = in_le16(hose_cfg_base + PCI_LTSSM); + if (reg16 >= PCI_LTSSM_L0) + printf("link\n"); + else + printf("No link\n"); + + mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0); +} + +/* + * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs + * must have been set to cover all of the requested regions. + */ +void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot) +{ + int i; + + /* + * Release PCI RST Output signal. + * Power on to RST high must be at least 100 ms as per PCI spec. + * On warm boots only 1 ms is required. + */ + udelay(warmboot ? 1000 : 100000); + + for (i = 0; i < num_buses; i++) + mpc83xx_pcie_init_bus(i, reg[i]); +} diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index bf9bf36e5..4230099c0 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -132,7 +132,7 @@ int get_clocks(void) u32 qe_clk; u32 brg_clk; #endif -#if defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X) u32 pciexp1_clk; u32 pciexp2_clk; #endif @@ -328,7 +328,7 @@ int get_clocks(void) i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ #endif -#if defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X) switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) { case 0: pciexp1_clk = 0; diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 2bb50b47f..e5a3b2c17 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -75,7 +75,7 @@ typedef struct global_data { u32 lbiu_clk; u32 lclk_clk; u32 pci_clk; -#if defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X) u32 pciexp1_clk; u32 pciexp2_clk; #endif diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index df24a6e87..77c09db6b 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -52,23 +52,28 @@ typedef struct sysconf83xx { law83xx_t lblaw[4]; /* LBIU local access window */ u8 res2[0x20]; law83xx_t pcilaw[2]; /* PCI local access window */ - u8 res3[0x30]; + u8 res3[0x10]; + law83xx_t pcielaw[2]; /* PCI Express local access window */ + u8 res4[0x10]; law83xx_t ddrlaw[2]; /* DDR local access window */ - u8 res4[0x50]; + u8 res5[0x50]; u32 sgprl; /* System General Purpose Register Low */ u32 sgprh; /* System General Purpose Register High */ u32 spridr; /* System Part and Revision ID Register */ - u8 res5[0x04]; + u8 res6[0x04]; u32 spcr; /* System Priority Configuration Register */ u32 sicrl; /* System I/O Configuration Register Low */ u32 sicrh; /* System I/O Configuration Register High */ - u8 res6[0x04]; + u8 res7[0x04]; u32 sidcr0; /* System I/O Delay Configuration Register 0 */ u32 sidcr1; /* System I/O Delay Configuration Register 1 */ u32 ddrcdr; /* DDR Control Driver Register */ u32 ddrdsr; /* DDR Debug Status Register */ u32 obir; /* Output Buffer Impedance Register */ - u8 res7[0xCC]; + u8 res8[0xC]; + u32 pecr1; /* PCI Express control register 1 */ + u32 pecr2; /* PCI Express control register 2 */ + u8 res9[0xB8]; } sysconf83xx_t; /* @@ -503,8 +508,110 @@ typedef struct security83xx { /* * PCI Express */ +struct pex_inbound_window { + u32 ar; + u32 tar; + u32 barl; + u32 barh; +}; + +struct pex_outbound_window { + u32 ar; + u32 bar; + u32 tarl; + u32 tarh; +}; + +struct pex_csb_bridge { + u32 pex_csb_ver; + u32 pex_csb_cab; + u32 pex_csb_ctrl; + u8 res0[8]; + u32 pex_dms_dstmr; + u8 res1[4]; + u32 pex_cbs_stat; + u8 res2[0x20]; + u32 pex_csb_obctrl; + u32 pex_csb_obstat; + u8 res3[0x98]; + u32 pex_csb_ibctrl; + u32 pex_csb_ibstat; + u8 res4[0xb8]; + u32 pex_wdma_ctrl; + u32 pex_wdma_addr; + u32 pex_wdma_stat; + u8 res5[0x94]; + u32 pex_rdma_ctrl; + u32 pex_rdma_addr; + u32 pex_rdma_stat; + u8 res6[0xd4]; + u32 pex_ombcr; + u32 pex_ombdr; + u8 res7[0x38]; + u32 pex_imbcr; + u32 pex_imbdr; + u8 res8[0x38]; + u32 pex_int_enb; + u32 pex_int_stat; + u32 pex_int_apio_vec1; + u32 pex_int_apio_vec2; + u8 res9[0x10]; + u32 pex_int_ppio_vec1; + u32 pex_int_ppio_vec2; + u32 pex_int_wdma_vec1; + u32 pex_int_wdma_vec2; + u32 pex_int_rdma_vec1; + u32 pex_int_rdma_vec2; + u32 pex_int_misc_vec; + u8 res10[4]; + u32 pex_int_axi_pio_enb; + u32 pex_int_axi_wdma_enb; + u32 pex_int_axi_rdma_enb; + u32 pex_int_axi_misc_enb; + u32 pex_int_axi_pio_stat; + u32 pex_int_axi_wdma_stat; + u32 pex_int_axi_rdma_stat; + u32 pex_int_axi_misc_stat; + u8 res11[0xa0]; + struct pex_outbound_window pex_outbound_win[4]; + u8 res12[0x100]; + u32 pex_epiwtar0; + u32 pex_epiwtar1; + u32 pex_epiwtar2; + u32 pex_epiwtar3; + u8 res13[0x70]; + struct pex_inbound_window pex_inbound_win[4]; +}; + typedef struct pex83xx { - u8 fixme[0x1000]; + u8 pex_cfg_header[0x404]; + u32 pex_ltssm_stat; + u8 res0[0x30]; + u32 pex_ack_replay_timeout; + u8 res1[4]; + u32 pex_gclk_ratio; + u8 res2[0xc]; + u32 pex_pm_timer; + u32 pex_pme_timeout; + u8 res3[4]; + u32 pex_aspm_req_timer; + u8 res4[0x18]; + u32 pex_ssvid_update; + u8 res5[0x34]; + u32 pex_cfg_ready; + u8 res6[0x24]; + u32 pex_bar_sizel; + u8 res7[4]; + u32 pex_bar_sel; + u8 res8[0x20]; + u32 pex_bar_pf; + u8 res9[0x88]; + u32 pex_pme_to_ack_tor; + u8 res10[0xc]; + u32 pex_ss_intr_mask; + u8 res11[0x25c]; + struct pex_csb_bridge bridge; + u8 res12[0x160]; } pex83xx_t; /* diff --git a/include/mpc83xx.h b/include/mpc83xx.h index e5dfe3f21..191488aa8 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -751,9 +751,6 @@ #define SCCR_USBDRCM_2 0x00800000 #define SCCR_USBDRCM_3 0x00c00000 -#define SCCR_PCIEXP1CM 0x00300000 -#define SCCR_PCIEXP2CM 0x000c0000 - #define SCCR_SATA1CM 0x00003000 #define SCCR_SATA1CM_SHIFT 12 #define SCCR_SATACM 0x00003c00 @@ -800,6 +797,17 @@ #define SCCR_USBDRCM_2 0x00800000 #define SCCR_USBDRCM_3 0x00c00000 +/* All of the four SATA controllers must have the same clock ratio */ +#define SCCR_SATA1CM 0x000000c0 +#define SCCR_SATA1CM_SHIFT 6 +#define SCCR_SATACM 0x000000ff +#define SCCR_SATACM_SHIFT 0 +#define SCCR_SATACM_0 0x00000000 +#define SCCR_SATACM_1 0x00000055 +#define SCCR_SATACM_2 0x000000aa +#define SCCR_SATACM_3 0x000000ff +#endif + #define SCCR_PCIEXP1CM 0x00300000 #define SCCR_PCIEXP1CM_SHIFT 20 #define SCCR_PCIEXP1CM_0 0x00000000 @@ -814,17 +822,6 @@ #define SCCR_PCIEXP2CM_2 0x00080000 #define SCCR_PCIEXP2CM_3 0x000c0000 -/* All of the four SATA controllers must have the same clock ratio */ -#define SCCR_SATA1CM 0x000000c0 -#define SCCR_SATA1CM_SHIFT 6 -#define SCCR_SATACM 0x000000ff -#define SCCR_SATACM_SHIFT 0 -#define SCCR_SATACM_0 0x00000000 -#define SCCR_SATACM_1 0x00000055 -#define SCCR_SATACM_2 0x000000aa -#define SCCR_SATACM_3 0x000000ff -#endif - /* CSn_BDNS - Chip Select memory Bounds Register */ #define CSBNDS_SA 0x00FF0000 @@ -1170,10 +1167,52 @@ #define DDRCDR_M_ODR 0x00000002 #define DDRCDR_Q_DRN 0x00000001 +/* PCIE Bridge Register +*/ +#define PEX_CSB_CTRL_OBPIOE 0x00000001 +#define PEX_CSB_CTRL_IBPIOE 0x00000002 +#define PEX_CSB_CTRL_WDMAE 0x00000004 +#define PEX_CSB_CTRL_RDMAE 0x00000008 + +#define PEX_CSB_OBCTRL_PIOE 0x00000001 +#define PEX_CSB_OBCTRL_MEMWE 0x00000002 +#define PEX_CSB_OBCTRL_IOWE 0x00000004 +#define PEX_CSB_OBCTRL_CFGWE 0x00000008 + +#define PEX_CSB_IBCTRL_PIOE 0x00000001 + +#define PEX_OWAR_EN 0x00000001 +#define PEX_OWAR_TYPE_CFG 0x00000000 +#define PEX_OWAR_TYPE_IO 0x00000002 +#define PEX_OWAR_TYPE_MEM 0x00000004 +#define PEX_OWAR_RLXO 0x00000008 +#define PEX_OWAR_NANP 0x00000010 +#define PEX_OWAR_SIZE 0xFFFFF000 + +#define PEX_IWAR_EN 0x00000001 +#define PEX_IWAR_TYPE_INT 0x00000000 +#define PEX_IWAR_TYPE_PF 0x00000004 +#define PEX_IWAR_TYPE_NO_PF 0x00000006 +#define PEX_IWAR_NSOV 0x00000008 +#define PEX_IWAR_NSNP 0x00000010 +#define PEX_IWAR_SIZE 0xFFFFF000 +#define PEX_IWAR_SIZE_1M 0x000FF000 +#define PEX_IWAR_SIZE_2M 0x001FF000 +#define PEX_IWAR_SIZE_4M 0x003FF000 +#define PEX_IWAR_SIZE_8M 0x007FF000 +#define PEX_IWAR_SIZE_16M 0x00FFF000 +#define PEX_IWAR_SIZE_32M 0x01FFF000 +#define PEX_IWAR_SIZE_64M 0x03FFF000 +#define PEX_IWAR_SIZE_128M 0x07FFF000 +#define PEX_IWAR_SIZE_256M 0x0FFFF000 + +#define PEX_GCLK_RATIO 0x440 + #ifndef __ASSEMBLY__ struct pci_region; void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot); void mpc83xx_pcislave_unlock(int bus); +void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot); #endif #endif /* __MPC83XX_H__ */ diff --git a/include/pci.h b/include/pci.h index eebe8a8a5..072273be5 100644 --- a/include/pci.h +++ b/include/pci.h @@ -382,6 +382,8 @@ extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev #define MAX_PCI_REGIONS 7 +#define INDIRECT_TYPE_NO_PCIE_LINK 1 + /* * Structure of a PCI controller (host bridge) */ @@ -394,6 +396,8 @@ struct pci_controller { volatile unsigned int *cfg_addr; volatile unsigned char *cfg_data; + int indirect_type; + struct pci_region regions[MAX_PCI_REGIONS]; int region_count; From 8f11e34b31a7be124a3239653f33af9510502045 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 8 Jan 2009 04:26:17 +0300 Subject: [PATCH 124/188] mpc83xx: Add PCI-E support for MPC8315ERDB boards MPC8315ERDB boards features PCI-E x1 and Mini PCI-E x1 ports. Let's support them. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- board/freescale/mpc8315erdb/mpc8315erdb.c | 52 +++++++++++++++++++++++ include/configs/MPC8315ERDB.h | 21 +++++++++ 2 files changed, 73 insertions(+) diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c index ea4b04fd3..f80b0ba4a 100644 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ b/board/freescale/mpc8315erdb/mpc8315erdb.c @@ -30,6 +30,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -95,12 +96,45 @@ static struct pci_region pci_regions[] = { } }; +static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +static struct pci_region pcie_regions_1[] = { + { + .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, + .size = CONFIG_SYS_PCIE2_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE2_IO_BASE, + .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, + .size = CONFIG_SYS_PCIE2_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + void pci_init_board(void) { volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile sysconf83xx_t *sysconf = &immr->sysconf; volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + volatile law83xx_t *pcie_law = sysconf->pcielaw; struct pci_region *reg[] = { pci_regions }; + struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; int warmboot; /* Enable all 3 PCI_CLK_OUTPUTs. */ @@ -119,6 +153,24 @@ void pci_init_board(void) warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF; mpc83xx_pci_init(1, reg, warmboot); + + /* Configure the clock for PCIE controller */ + clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, + SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + out_be32(&sysconf->pecr2, 0xE0008000); + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); + out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); + + mpc83xx_pcie_init(2, pcie_reg, warmboot); } #if defined(CONFIG_OF_BOARD_SETUP) diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index add65f03d..909353d41 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -308,8 +308,29 @@ #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 +#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + +#define CONFIG_SYS_PCIE2_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 +#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 + #define CONFIG_PCI #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ +#define CONFIG_83XX_GENERIC_PCIE 1 #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ From 8b34557c546e5e9f34ebf83c93413dad973d93df Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 8 Jan 2009 04:26:19 +0300 Subject: [PATCH 125/188] mpc83xx: Add PCI-E support for MPC837XEMDS boards MPC837XEMDS boards can support PCI-E via "PCI-E riser card". The card provides two PCI-E (x2) ports. Though, only one port can be used in x2 mode. Two ports can function simultaneously in x1 mode. PCI-E x1/x2 modes can be switched via "pex_x2" environment variable. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- board/freescale/mpc837xemds/mpc837xemds.c | 6 +- board/freescale/mpc837xemds/pci.c | 89 ++++++++++++++++++++++- board/freescale/mpc837xemds/pci.h | 6 ++ include/configs/MPC837XEMDS.h | 21 ++++++ 4 files changed, 117 insertions(+), 5 deletions(-) create mode 100644 board/freescale/mpc837xemds/pci.h diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index acf8ada7b..156d8089a 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -18,6 +18,7 @@ #include #include #include +#include "pci.h" #include "../common/pq-mds-pib.h" int board_early_init_f(void) @@ -38,14 +39,10 @@ int board_early_init_f(void) case SPR_8377: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8378: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII, FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8379: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, @@ -316,6 +313,7 @@ void ft_board_setup(void *blob, bd_t *bd) ft_pci_setup(blob, bd); if (board_pci_host_broken()) ft_pci_fixup(blob, bd); + ft_pcie_fixup(blob, bd); #endif } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c index df4e748e9..31116b31c 100644 --- a/board/freescale/mpc837xemds/pci.c +++ b/board/freescale/mpc837xemds/pci.c @@ -16,7 +16,9 @@ #include #include #include +#include #include +#include #if defined(CONFIG_PCI) static struct pci_region pci_regions[] = { @@ -40,15 +42,59 @@ static struct pci_region pci_regions[] = { } }; +static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +static struct pci_region pcie_regions_1[] = { + { + .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, + .size = CONFIG_SYS_PCIE2_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE2_IO_BASE, + .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, + .size = CONFIG_SYS_PCIE2_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +static int is_pex_x2(void) +{ + const char *pex_x2 = getenv("pex_x2"); + + if (pex_x2 && !strcmp(pex_x2, "yes")) + return 1; + return 0; +} + void pci_init_board(void) { volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile sysconf83xx_t *sysconf = &immr->sysconf; volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + volatile law83xx_t *pcie_law = sysconf->pcielaw; struct pci_region *reg[] = { pci_regions }; + struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; + u32 spridr = in_be32(&immr->sysconf.spridr); + int pex2 = is_pex_x2(); if (board_pci_host_broken()) - return; + goto skip_pci; /* Enable all 5 PCI_CLK_OUTPUTS */ clk->occr |= 0xf8000000; @@ -64,5 +110,46 @@ void pci_init_board(void) udelay(2000); mpc83xx_pci_init(1, reg, 0); +skip_pci: + /* There is no PEX in MPC8379 parts. */ + if (PARTID_NO_E(spridr) == SPR_8379) + return; + + /* Configure the clock for PCIE controller */ + clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, + SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + if (!pex2) + out_be32(&sysconf->pecr2, 0xE0008000); + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); + out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); + + if (pex2) + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + else + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + + mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg, 0); +} + +void ft_pcie_fixup(void *blob, bd_t *bd) +{ + const char *status = "disabled (PCIE1 is x2)"; + + if (!is_pex_x2()) + return; + + do_fixup_by_path(blob, "pci2", "status", status, + strlen(status) + 1, 1); } #endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc837xemds/pci.h b/board/freescale/mpc837xemds/pci.h new file mode 100644 index 000000000..fd7a916af --- /dev/null +++ b/board/freescale/mpc837xemds/pci.h @@ -0,0 +1,6 @@ +#ifndef __BOARD_MPC837XEMDS_PCI_H +#define __BOARD_MPC837XEMDS_PCI_H + +extern void ft_pcie_fixup(void *blob, bd_t *bd); + +#endif /* __BOARD_MPC837XEMDS_PCI_H */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index d49155fce..28d442bab 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -354,11 +354,32 @@ #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 +#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + +#define CONFIG_SYS_PCIE2_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 +#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 + #ifdef CONFIG_PCI #ifndef __ASSEMBLY__ extern int board_pci_host_broken(void); #endif #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ +#define CONFIG_83XX_GENERIC_PCIE 1 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ From 6677876181cc8772bca8a372479a500d160f3993 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Tue, 20 Jan 2009 11:56:11 -0600 Subject: [PATCH 126/188] 83xx: Use the proper sequence for updating IMMR. This ensures that subsequent accesses properly hit the new window. The dcbi during the NAND loop was accidentally working around this; it's no longer necessary, as the cache is not enabled. Reported-by: Suchit Lepcha Signed-off-by: Scott Wood Signed-off-by: Kim Phillips --- cpu/mpc83xx/start.S | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index beebc9951..26e31061f 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -200,9 +200,23 @@ boot_cold: /* time t 3 */ nop boot_warm: /* time t 5 */ mfmsr r5 /* save msr contents */ + + /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */ + bl 1f +1: mflr r7 + lis r3, CONFIG_SYS_IMMR@h ori r3, r3, CONFIG_SYS_IMMR@l + + lwz r6, IMMRBAR(r4) + isync + stw r3, IMMRBAR(r4) + lwz r6, 0(r7) /* Arbitrary external load */ + isync + + lwz r6, IMMRBAR(r3) + isync /* Initialise the E300 processor core */ /*------------------------------------------*/ @@ -212,9 +226,7 @@ boot_warm: /* time t 5 */ * is loaded. Wait for the rest before branching * to another flash page. */ - addi r7, r3, 0x50b0 -1: dcbi 0, r7 - lwz r6, 0(r7) +1: lwz r6, 0x50b0(r3) andi. r6, r6, 1 beq 1b #endif From 52a822ed9c37a2ea0ed112a26d8ff5a6cb1c6f10 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 19 Dec 2008 13:14:05 +0100 Subject: [PATCH 127/188] microblaze: Rename ml401 to microblaze-generic Signed-off-by: Michal Simek --- MAINTAINERS | 2 +- MAKEALL | 6 +++--- Makefile | 5 ++--- board/xilinx/{ml401 => microblaze-generic}/Makefile | 0 board/xilinx/{ml401 => microblaze-generic}/config.mk | 0 .../ml401.c => microblaze-generic/microblaze-generic.c} | 0 board/xilinx/{ml401 => microblaze-generic}/u-boot.lds | 0 board/xilinx/{ml401 => microblaze-generic}/xparameters.h | 0 include/configs/{ml401.h => microblaze-generic.h} | 3 +-- 9 files changed, 7 insertions(+), 9 deletions(-) rename board/xilinx/{ml401 => microblaze-generic}/Makefile (100%) rename board/xilinx/{ml401 => microblaze-generic}/config.mk (100%) rename board/xilinx/{ml401/ml401.c => microblaze-generic/microblaze-generic.c} (100%) rename board/xilinx/{ml401 => microblaze-generic}/u-boot.lds (100%) rename board/xilinx/{ml401 => microblaze-generic}/xparameters.h (100%) rename include/configs/{ml401.h => microblaze-generic.h} (98%) diff --git a/MAINTAINERS b/MAINTAINERS index 60def0c34..dfe54a7cb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -707,7 +707,7 @@ Yasushi Shoji Michal Simek - ML401 MicroBlaze + microblaze-generic MicroBlaze ######################################################################### # Coldfire Systems: # diff --git a/MAKEALL b/MAKEALL index 5ce3f3112..f6271a29f 100755 --- a/MAKEALL +++ b/MAKEALL @@ -697,9 +697,9 @@ LIST_nios2=" \ ## MicroBlaze Systems ######################################################################### -LIST_microblaze=" \ - ml401 \ - suzaku \ +LIST_microblaze=" \ + microblaze-generic \ + suzaku \ " ######################################################################### diff --git a/Makefile b/Makefile index d533564d9..5cc950dea 100644 --- a/Makefile +++ b/Makefile @@ -3170,10 +3170,9 @@ PCI5441_config : unconfig ## Microblaze #======================================================================== -ml401_config: unconfig +microblaze-generic_config: unconfig @mkdir -p $(obj)include - @echo "#define CONFIG_ML401 1" > $(obj)include/config.h - @$(MKCONFIG) -a $(@:_config=) microblaze microblaze ml401 xilinx + @$(MKCONFIG) -a $(@:_config=) microblaze microblaze microblaze-generic xilinx suzaku_config: unconfig @mkdir -p $(obj)include diff --git a/board/xilinx/ml401/Makefile b/board/xilinx/microblaze-generic/Makefile similarity index 100% rename from board/xilinx/ml401/Makefile rename to board/xilinx/microblaze-generic/Makefile diff --git a/board/xilinx/ml401/config.mk b/board/xilinx/microblaze-generic/config.mk similarity index 100% rename from board/xilinx/ml401/config.mk rename to board/xilinx/microblaze-generic/config.mk diff --git a/board/xilinx/ml401/ml401.c b/board/xilinx/microblaze-generic/microblaze-generic.c similarity index 100% rename from board/xilinx/ml401/ml401.c rename to board/xilinx/microblaze-generic/microblaze-generic.c diff --git a/board/xilinx/ml401/u-boot.lds b/board/xilinx/microblaze-generic/u-boot.lds similarity index 100% rename from board/xilinx/ml401/u-boot.lds rename to board/xilinx/microblaze-generic/u-boot.lds diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h similarity index 100% rename from board/xilinx/ml401/xparameters.h rename to board/xilinx/microblaze-generic/xparameters.h diff --git a/include/configs/ml401.h b/include/configs/microblaze-generic.h similarity index 98% rename from include/configs/ml401.h rename to include/configs/microblaze-generic.h index c802dcb6a..ed4bf6d35 100644 --- a/include/configs/ml401.h +++ b/include/configs/microblaze-generic.h @@ -25,11 +25,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include "../board/xilinx/ml401/xparameters.h" +#include "../board/xilinx/microblaze-generic/xparameters.h" #define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */ #define MICROBLAZE_V5 1 -#define CONFIG_ML401 1 /* ML401 Board */ /* uart */ #ifdef XILINX_UARTLITE_BASEADDR From 330e55459bc9983341da6c1d5c7fe00a664436fe Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 19 Dec 2008 13:25:55 +0100 Subject: [PATCH 128/188] microblaze: Change microblaze-generic config file Signed-off-by: Michal Simek --- board/xilinx/microblaze-generic/xparameters.h | 2 + include/configs/microblaze-generic.h | 97 ++++++++++--------- 2 files changed, 53 insertions(+), 46 deletions(-) diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index d805061c0..fae03bf71 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -25,6 +25,8 @@ * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 */ +#define XILINX_BOARD_NAME microblaze-generic + /* System Clock Frequency */ #define XILINX_CLOCK_FREQ 100000000 diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index ed4bf6d35..867f88513 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -32,24 +32,26 @@ /* uart */ #ifdef XILINX_UARTLITE_BASEADDR -#define CONFIG_XILINX_UARTLITE -#define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR -#define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE -#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } + #define CONFIG_XILINX_UARTLITE + #define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR + #define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE + #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } + #define CONSOLE_ARG "console=console=ttyUL0,115200\0" #elif XILINX_UART16550_BASEADDR -#define CONFIG_SYS_NS16550 1 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 (XILINX_UART16550_BASEADDR + 0x1000 + 0x3) -#define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ -#define CONFIG_BAUDRATE 115200 + #define CONFIG_SYS_NS16550 1 + #define CONFIG_SYS_NS16550_SERIAL + #define CONFIG_SYS_NS16550_REG_SIZE -4 + #define CONFIG_CONS_INDEX 1 + #define CONFIG_SYS_NS16550_COM1 (XILINX_UART16550_BASEADDR + 0x1000 + 0x3) + #define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ + #define CONFIG_BAUDRATE 115200 -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + /* The following table includes the supported baudrates */ + #define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + #define CONSOLE_ARG "console=console=ttyS0,115200\0" #else -#error Undefined uart + #error Undefined uart #endif /* setting reset address */ @@ -57,44 +59,44 @@ /* ethernet */ #ifdef XILINX_EMAC_BASEADDR -#define CONFIG_XILINX_EMAC 1 -#define CONFIG_SYS_ENET -#else -#ifdef XILINX_EMACLITE_BASEADDR -#define CONFIG_XILINX_EMACLITE 1 -#define CONFIG_SYS_ENET -#endif + #define CONFIG_XILINX_EMAC 1 + #define CONFIG_SYS_ENET +#elif XILINX_EMACLITE_BASEADDR + #define CONFIG_XILINX_EMACLITE 1 + #define CONFIG_SYS_ENET +#elif XILINX_LLTEMAC_BASEADDR + #define CONFIG_XILINX_LL_TEMAC 1 + #define CONFIG_SYS_ENET #endif + #undef ET_DEBUG /* gpio */ #ifdef XILINX_GPIO_BASEADDR -#define CONFIG_SYS_GPIO_0 1 -#define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR + #define CONFIG_SYS_GPIO_0 1 + #define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR #endif /* interrupt controller */ #ifdef XILINX_INTC_BASEADDR -#define CONFIG_SYS_INTC_0 1 -#define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR -#define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS + #define CONFIG_SYS_INTC_0 1 + #define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR + #define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS #endif /* timer */ #ifdef XILINX_TIMER_BASEADDR -#if (XILINX_TIMER_IRQ != -1) -#define CONFIG_SYS_TIMER_0 1 -#define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR -#define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ -#define FREQUENCE XILINX_CLOCK_FREQ -#define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) -#endif + #if (XILINX_TIMER_IRQ != -1) + #define CONFIG_SYS_TIMER_0 1 + #define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR + #define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ + #define FREQUENCE XILINX_CLOCK_FREQ + #define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) + #endif +#elif XILINX_CLOCK_FREQ + #define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ #else -#ifdef XILINX_CLOCK_FREQ -#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ -#else -#error BAD CLOCK FREQ -#endif + #error BAD CLOCK FREQ #endif /* FSL */ /* #define CONFIG_SYS_FSL_2 */ @@ -159,7 +161,7 @@ #define CONFIG_FLASH_CFI_DRIVER 1 #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* ?empty sector */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ - #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */ #ifdef RAMENV @@ -169,9 +171,9 @@ #else /* !RAMENV */ #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) - #define CONFIG_ENV_SIZE 0x40000 + #define CONFIG_ENV_SIZE 0x20000 #endif /* !RAMBOOT */ #else /* !FLASH */ /* ENV in RAM */ @@ -209,6 +211,7 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_IRQ #define CONFIG_CMD_MFSL +#define CONFIG_CMD_ECHO #ifndef CONFIG_SYS_ENET #undef CONFIG_CMD_NET @@ -232,7 +235,9 @@ #define CONFIG_CMD_SAVES #endif #else + #undef CONFIG_CMD_IMLS #undef CONFIG_CMD_FLASH + #undef CONFIG_CMD_JFFS2 #endif #if defined(CONFIG_CMD_JFFS2) @@ -252,11 +257,11 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ #define CONFIG_SYS_MAXARGS 15 /* max number of command args */ #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_LOAD_ADDR 0x12000000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START /* default load address */ -#define CONFIG_BOOTDELAY 30 +#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ #define CONFIG_BOOTARGS "root=romfs" -#define CONFIG_HOSTNAME "ml401" +#define CONFIG_HOSTNAME XILINX_BOARD_NAME #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" #define CONFIG_IPADDR 192.168.0.3 #define CONFIG_SERVERIP 192.168.0.5 @@ -267,7 +272,7 @@ #define CONFIG_SYS_USR_EXCEP /* user exception */ #define CONFIG_SYS_HZ 1000 -#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo" +#define CONFIG_PREBOOT "echo U-BOOT for $(hostname);setenv preboot;echo" #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\ "nor0=ml401-0\0"\ From b4f8dda35bfad447b4106828232705b2e878d168 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 5 Jan 2009 13:28:40 +0100 Subject: [PATCH 129/188] microblaze: Add bootup messages to board.c --- lib_microblaze/board.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/lib_microblaze/board.c b/lib_microblaze/board.c index 4f48341f3..732f81e76 100644 --- a/lib_microblaze/board.c +++ b/lib_microblaze/board.c @@ -111,6 +111,10 @@ void board_init (void) gd = (gd_t *) CONFIG_SYS_GBL_DATA_OFFSET; #if defined(CONFIG_CMD_FLASH) ulong flash_size = 0; +#endif +#if defined(CONFIG_CMD_NET) + char *s, *e; + int i; #endif asm ("nop"); /* FIXME gd is not initialize - wait */ memset ((void *)gd, 0, CONFIG_SYS_GBL_DATA_SIZE); @@ -132,11 +136,37 @@ void board_init (void) } } + puts ("SDRAM :\n"); +#if defined(CONFIG_CMD_CACHE) + puts ("\tEnabling caches :\n"); + printf ("\t\tIcache:%s\n", icache_status() ? "OK" : "FAIL"); + printf ("\t\tDcache:%s\n", dcache_status() ? "OK" : "FAIL"); +#endif + printf ("\tU-Boot Start:0x%08x\n", TEXT_BASE); + #if defined(CONFIG_CMD_FLASH) + puts ("FLASH: "); bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; if (0 < (flash_size = flash_init ())) { bd->bi_flashsize = flash_size; bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + flash_size; +# ifdef CONFIG_SYS_FLASH_CHECKSUM + print_size (flash_size, ""); + /* + * Compute and print flash CRC if flashchecksum is set to 'y' + * + * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX + */ + s = getenv ("flashchecksum"); + if (s && (*s == 'y')) { + printf (" CRC: %08X", + crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size) + ); + } + putc ('\n'); +# else /* !CONFIG_SYS_FLASH_CHECKSUM */ + print_size (flash_size, "\n"); +# endif /* CONFIG_SYS_FLASH_CHECKSUM */ } else { puts ("Flash init FAILED"); bd->bi_flashstart = 0; @@ -146,10 +176,9 @@ void board_init (void) #endif #if defined(CONFIG_CMD_NET) - char *s, *e; - int i; /* board MAC address */ s = getenv ("ethaddr"); + printf ("MAC:%s\n",s); for (i = 0; i < 6; ++i) { bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; if (s) From e9b737deb2c30125362d20e24170617476026e94 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 5 Jan 2009 13:29:32 +0100 Subject: [PATCH 130/188] microblaze: Add cache flush --- include/configs/microblaze-generic.h | 19 ++++++++++++++++++- lib_microblaze/cache.c | 16 ++++++++++++++-- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 867f88513..4c6cc9fef 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -194,6 +194,18 @@ #define CONFIG_DOS_PARTITION #endif +#if defined(XILINX_USE_ICACHE) + #define CONFIG_ICACHE +#else + #undef CONFIG_ICACHE +#endif + +#if defined(XILINX_USE_DCACHE) + #define CONFIG_DCACHE +#else + #undef CONFIG_DCACHE +#endif + /* * BOOTP options */ @@ -208,11 +220,16 @@ #include #define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE #define CONFIG_CMD_IRQ #define CONFIG_CMD_MFSL #define CONFIG_CMD_ECHO +#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE) + #define CONFIG_CMD_CACHE +#else + #undef CONFIG_CMD_CACHE +#endif + #ifndef CONFIG_SYS_ENET #undef CONFIG_CMD_NET #else diff --git a/lib_microblaze/cache.c b/lib_microblaze/cache.c index a2f7493b6..4b2e8e379 100644 --- a/lib_microblaze/cache.c +++ b/lib_microblaze/cache.c @@ -26,6 +26,18 @@ void flush_cache (ulong addr, ulong size) { - /* MicroBlaze have write thruough cache. nothing to do. */ - return; + int i; + for (i = 0; i < size; i += 4) + asm volatile ( +#ifdef CONFIG_ICACHE + "wic %0, r0;" +#endif + "nop;" +#ifdef CONFIG_DCACHE + "wdc %0, r0;" +#endif + "nop;" + : + : "r" (addr + i) + : "memory"); } From e7f325be9edeb84bb457301776bbac1f7257dafc Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 5 Jan 2009 13:35:31 +0100 Subject: [PATCH 131/188] microblaze: Use cache functions (especially cache status) in systems which are configured without flash --- cpu/microblaze/cache.c | 3 --- lib_microblaze/board.c | 3 --- 2 files changed, 6 deletions(-) diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c index 4b7866fae..3b7c4d4f7 100644 --- a/cpu/microblaze/cache.c +++ b/cpu/microblaze/cache.c @@ -25,8 +25,6 @@ #include #include -#if defined(CONFIG_CMD_CACHE) - int dcache_status (void) { int i = 0; @@ -62,4 +60,3 @@ void dcache_enable (void) { void dcache_disable(void) { MSRCLR(0x80); } -#endif diff --git a/lib_microblaze/board.c b/lib_microblaze/board.c index 732f81e76..30d764186 100644 --- a/lib_microblaze/board.c +++ b/lib_microblaze/board.c @@ -137,11 +137,8 @@ void board_init (void) } puts ("SDRAM :\n"); -#if defined(CONFIG_CMD_CACHE) - puts ("\tEnabling caches :\n"); printf ("\t\tIcache:%s\n", icache_status() ? "OK" : "FAIL"); printf ("\t\tDcache:%s\n", dcache_status() ? "OK" : "FAIL"); -#endif printf ("\tU-Boot Start:0x%08x\n", TEXT_BASE); #if defined(CONFIG_CMD_FLASH) From ef0921d6b05aeb9034158f9bef5323d6da9c925e Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Tue, 4 Nov 2008 09:24:07 +0900 Subject: [PATCH 132/188] Sync with 2.6.27 Sync with OneNAND kernel codes Signed-off-by: Kyungmin Park --- drivers/mtd/onenand/onenand_base.c | 508 +++++++++++++++++++--------- drivers/mtd/onenand/onenand_bbt.c | 8 +- drivers/mtd/onenand/onenand_uboot.c | 10 +- include/linux/mtd/onenand.h | 44 ++- include/linux/mtd/onenand_regs.h | 1 + include/onenand_uboot.h | 14 +- 6 files changed, 406 insertions(+), 179 deletions(-) diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 9b7bf3aa3..66214e86d 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -78,20 +78,11 @@ static void onenand_writew(unsigned short value, void __iomem * addr) * * Setup Start Address 1 Register (F100h) */ -static int onenand_block_address(int device, int block) +static int onenand_block_address(struct onenand_chip *this, int block) { - if (device & ONENAND_DEVICE_IS_DDP) { - /* Device Flash Core select, NAND Flash Block Address */ - int dfs = 0, density, mask; - - density = device >> ONENAND_DEVICE_DENSITY_SHIFT; - mask = (1 << (density + 6)); - - if (block & mask) - dfs = 1; - - return (dfs << ONENAND_DDP_SHIFT) | (block & (mask - 1)); - } + /* Device Flash Core select, NAND Flash Block Address */ + if (block & this->density_mask) + return ONENAND_DDP_CHIP1 | (block ^ this->density_mask); return block; } @@ -104,22 +95,13 @@ static int onenand_block_address(int device, int block) * * Setup Start Address 2 Register (F101h) for DDP */ -static int onenand_bufferram_address(int device, int block) +static int onenand_bufferram_address(struct onenand_chip *this, int block) { - if (device & ONENAND_DEVICE_IS_DDP) { - /* Device BufferRAM Select */ - int dbs = 0, density, mask; + /* Device BufferRAM Select */ + if (block & this->density_mask) + return ONENAND_DDP_CHIP1; - density = device >> ONENAND_DEVICE_DENSITY_SHIFT; - mask = (1 << (density + 6)); - - if (block & mask) - dbs = 1; - - return (dbs << ONENAND_DDP_SHIFT); - } - - return 0; + return ONENAND_DDP_CHIP0; } /** @@ -168,6 +150,18 @@ static int onenand_buffer_address(int dataram1, int sectors, int count) return ((bsa << ONENAND_BSA_SHIFT) | bsc); } +/** + * onenand_get_density - [DEFAULT] Get OneNAND density + * @param dev_id OneNAND device ID + * + * Get OneNAND density from device ID + */ +static inline int onenand_get_density(int dev_id) +{ + int density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT; + return (density & ONENAND_DEVICE_DENSITY_MASK); +} + /** * onenand_command - [DEFAULT] Send command to OneNAND device * @param mtd MTD device structure @@ -192,6 +186,7 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, case ONENAND_CMD_UNLOCK: case ONENAND_CMD_LOCK: case ONENAND_CMD_LOCK_TIGHT: + case ONENAND_CMD_UNLOCK_ALL: block = -1; page = -1; break; @@ -212,7 +207,7 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, /* NOTE: The setting order of the registers is very important! */ if (cmd == ONENAND_CMD_BUFFERRAM) { /* Select DataRAM for DDP */ - value = onenand_bufferram_address(this->device_id, block); + value = onenand_bufferram_address(this, block); this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); @@ -224,9 +219,14 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, if (block != -1) { /* Write 'DFS, FBA' of Flash */ - value = onenand_block_address(this->device_id, block); + value = onenand_block_address(this, block); this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); + + /* Write 'DFS, FBA' of Flash */ + value = onenand_bufferram_address(this, block); + this->write_word(value, + this->base + ONENAND_REG_START_ADDRESS2); } if (page != -1) { @@ -252,15 +252,6 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, /* Write 'BSA, BSC' of DataRAM */ value = onenand_buffer_address(dataram, sectors, count); this->write_word(value, this->base + ONENAND_REG_START_BUFFER); - - if (readcmd) { - /* Select DataRAM for DDP */ - value = - onenand_bufferram_address(this->device_id, block); - this->write_word(value, - this->base + - ONENAND_REG_START_ADDRESS2); - } } /* Interrupt clear */ @@ -296,14 +287,11 @@ static int onenand_wait(struct mtd_info *mtd, int state) ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); if (ctrl & ONENAND_CTRL_ERROR) { - MTDDEBUG (MTD_DEBUG_LEVEL0, - "onenand_wait: controller error = 0x%04x\n", ctrl); - return -EAGAIN; - } + printk("onenand_wait: controller error = 0x%04x\n", ctrl); + if (ctrl & ONENAND_CTRL_LOCK) + printk("onenand_wait: it's locked error = 0x%04x\n", + ctrl); - if (ctrl & ONENAND_CTRL_LOCK) { - MTDDEBUG (MTD_DEBUG_LEVEL0, - "onenand_wait: it's locked error = 0x%04x\n", ctrl); return -EIO; } @@ -351,7 +339,7 @@ static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area) * * Read the BufferRAM area */ -static int onenand_read_bufferram(struct mtd_info *mtd, int area, +static int onenand_read_bufferram(struct mtd_info *mtd, loff_t addr, int area, unsigned char *buffer, int offset, size_t count) { @@ -376,7 +364,7 @@ static int onenand_read_bufferram(struct mtd_info *mtd, int area, * * Read the BufferRAM area with Sync. Burst Mode */ -static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area, +static int onenand_sync_read_bufferram(struct mtd_info *mtd, loff_t addr, int area, unsigned char *buffer, int offset, size_t count) { @@ -405,7 +393,7 @@ static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area, * * Write the BufferRAM area */ -static int onenand_write_bufferram(struct mtd_info *mtd, int area, +static int onenand_write_bufferram(struct mtd_info *mtd, loff_t addr, int area, const unsigned char *buffer, int offset, size_t count) { @@ -431,21 +419,39 @@ static int onenand_write_bufferram(struct mtd_info *mtd, int area, static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr) { struct onenand_chip *this = mtd->priv; - int block, page; - int i; + int blockpage, found = 0; + unsigned int i; - block = (int)(addr >> this->erase_shift); - page = (int)(addr >> this->page_shift); - page &= this->page_mask; +#ifdef CONFIG_S3C64XX + return 0; +#endif - i = ONENAND_CURRENT_BUFFERRAM(this); + if (ONENAND_IS_2PLANE(this)) + blockpage = onenand_get_2x_blockpage(mtd, addr); + else + blockpage = (int) (addr >> this->page_shift); /* Is there valid data? */ - if (this->bufferram[i].block == block && - this->bufferram[i].page == page && this->bufferram[i].valid) - return 1; + i = ONENAND_CURRENT_BUFFERRAM(this); + if (this->bufferram[i].blockpage == blockpage) + found = 1; + else { + /* Check another BufferRAM */ + i = ONENAND_NEXT_BUFFERRAM(this); + if (this->bufferram[i].blockpage == blockpage) { + ONENAND_SET_NEXT_BUFFERRAM(this); + found = 1; + } + } - return 0; + if (found && ONENAND_IS_DDP(this)) { + /* Select DataRAM for DDP */ + int block = (int) (addr >> this->erase_shift); + int value = onenand_bufferram_address(this, block); + this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); + } + + return found; } /** @@ -460,25 +466,25 @@ static int onenand_update_bufferram(struct mtd_info *mtd, loff_t addr, int valid) { struct onenand_chip *this = mtd->priv; - int block, page; - int i; + int blockpage; + unsigned int i; - block = (int)(addr >> this->erase_shift); - page = (int)(addr >> this->page_shift); - page &= this->page_mask; + if (ONENAND_IS_2PLANE(this)) + blockpage = onenand_get_2x_blockpage(mtd, addr); + else + blockpage = (int)(addr >> this->page_shift); - /* Invalidate BufferRAM */ - for (i = 0; i < MAX_BUFFERRAM; i++) { - if (this->bufferram[i].block == block && - this->bufferram[i].page == page) - this->bufferram[i].valid = 0; - } + /* Invalidate another BufferRAM */ + i = ONENAND_NEXT_BUFFERRAM(this); + if (this->bufferram[i].blockpage == blockpage) + this->bufferram[i].blockpage = -1; /* Update BufferRAM */ i = ONENAND_CURRENT_BUFFERRAM(this); - this->bufferram[i].block = block; - this->bufferram[i].page = page; - this->bufferram[i].valid = valid; + if (valid) + this->bufferram[i].blockpage = blockpage; + else + this->bufferram[i].blockpage = -1; return 0; } @@ -500,10 +506,10 @@ static void onenand_invalidate_bufferram(struct mtd_info *mtd, loff_t addr, /* Invalidate BufferRAM */ for (i = 0; i < MAX_BUFFERRAM; i++) { - loff_t buf_addr = this->bufferram[i].block << this->erase_shift; + loff_t buf_addr = this->bufferram[i].blockpage << this->page_shift; if (buf_addr >= addr && buf_addr < end_addr) - this->bufferram[i].valid = 0; + this->bufferram[i].blockpage = -1; } } @@ -556,7 +562,7 @@ static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, readend += free->offset - lastgap; lastgap = free->offset + free->length; } - this->read_bufferram(mtd, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize); + this->read_bufferram(mtd, 0, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize); free = this->ecclayout->oobfree; for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { int free_end = free->offset + free->length; @@ -594,9 +600,7 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, int ret = 0, boundary = 0; int writesize = this->writesize; - MTDDEBUG(MTD_DEBUG_LEVEL3, - "onenand_read_ops_nolock: from = 0x%08x, len = %i\n", - (unsigned int) from, (int) len); + MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_read_ops_nolock: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); if (ops->mode == MTD_OOB_AUTO) oobsize = this->ecclayout->oobavail; @@ -620,6 +624,7 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, /* Do first load to bufferRAM */ if (read < len) { if (!onenand_check_bufferram(mtd, from)) { + this->main_buf = buf; this->command(mtd, ONENAND_CMD_READ, from, writesize); ret = this->wait(mtd, FL_READING); onenand_update_bufferram(mtd, from, !ret); @@ -637,6 +642,7 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, /* If there is more to load then start next load */ from += thislen; if (read + thislen < len) { + this->main_buf = buf + thislen; this->command(mtd, ONENAND_CMD_READ, from, writesize); /* * Chip boundary handling in DDP @@ -653,7 +659,7 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, } /* While load is going, read from last bufferRAM */ - this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen); + this->read_bufferram(mtd, from - thislen, ONENAND_DATARAM, buf, column, thislen); /* Read oob area if needed */ if (oobbuf) { @@ -663,7 +669,7 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, if (ops->mode == MTD_OOB_AUTO) onenand_transfer_auto_oob(mtd, oobbuf, oobcolumn, thisooblen); else - this->read_bufferram(mtd, ONENAND_SPARERAM, oobbuf, oobcolumn, thisooblen); + this->read_bufferram(mtd, 0, ONENAND_SPARERAM, oobbuf, oobcolumn, thisooblen); oobread += thisooblen; oobbuf += thisooblen; oobcolumn = 0; @@ -726,9 +732,7 @@ static int onenand_read_oob_nolock(struct mtd_info *mtd, loff_t from, from += ops->ooboffs; - MTDDEBUG(MTD_DEBUG_LEVEL3, - "onenand_read_oob_nolock: from = 0x%08x, len = %i\n", - (unsigned int) from, (int) len); + MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob_nolock: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); /* Initialize return length value */ ops->oobretlen = 0; @@ -759,6 +763,7 @@ static int onenand_read_oob_nolock(struct mtd_info *mtd, loff_t from, thislen = oobsize - column; thislen = min_t(int, thislen, len); + this->spare_buf = buf; this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize); onenand_update_bufferram(mtd, from, 0); @@ -772,7 +777,7 @@ static int onenand_read_oob_nolock(struct mtd_info *mtd, loff_t from, if (mode == MTD_OOB_AUTO) onenand_transfer_auto_oob(mtd, buf, column, thislen); else - this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen); + this->read_bufferram(mtd, 0, ONENAND_SPARERAM, buf, column, thislen); read += thislen; @@ -886,12 +891,6 @@ static int onenand_bbt_wait(struct mtd_info *mtd, int state) interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); - /* Initial bad block case: 0x2400 or 0x0400 */ - if (ctrl & ONENAND_CTRL_ERROR) { - printk(KERN_DEBUG "onenand_bbt_wait: controller error = 0x%04x\n", ctrl); - return ONENAND_BBT_READ_ERROR; - } - if (interrupt & ONENAND_INT_READ) { int ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS); if (ecc & ONENAND_ECC_2BIT_ALL) @@ -902,6 +901,12 @@ static int onenand_bbt_wait(struct mtd_info *mtd, int state) return ONENAND_BBT_READ_FATAL_ERROR; } + /* Initial bad block case: 0x2400 or 0x0400 */ + if (ctrl & ONENAND_CTRL_ERROR) { + printk(KERN_DEBUG "onenand_bbt_wait: controller error = 0x%04x\n", ctrl); + return ONENAND_BBT_READ_ERROR; + } + return 0; } @@ -922,9 +927,7 @@ int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, size_t len = ops->ooblen; u_char *buf = ops->oobbuf; - MTDDEBUG(MTD_DEBUG_LEVEL3, - "onenand_bbt_read_oob: from = 0x%08x, len = %zi\n", - (unsigned int) from, len); + MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_bbt_read_oob: from = 0x%08x, len = %zi\n", (unsigned int) from, len); /* Initialize return value */ ops->oobretlen = 0; @@ -945,15 +948,16 @@ int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, thislen = mtd->oobsize - column; thislen = min_t(int, thislen, len); + this->spare_buf = buf; this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize); onenand_update_bufferram(mtd, from, 0); - ret = onenand_bbt_wait(mtd, FL_READING); + ret = this->bbt_wait(mtd, FL_READING); if (ret) break; - this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen); + this->read_spareram(mtd, 0, ONENAND_SPARERAM, buf, column, thislen); read += thislen; if (read == len) break; @@ -995,7 +999,7 @@ static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to if (status) return status; - this->read_bufferram(mtd, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize); + this->read_bufferram(mtd, 0, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize); for (i = 0; i < mtd->oobsize; i++) if (buf[i] != 0xFF && buf[i] != oob_buf[i]) return -EBADMSG; @@ -1115,9 +1119,7 @@ static int onenand_write_ops_nolock(struct mtd_info *mtd, loff_t to, u_char *oobbuf; int ret = 0; - MTDDEBUG(MTD_DEBUG_LEVEL3, - "onenand_write_ops_nolock: to = 0x%08x, len = %i\n", - (unsigned int) to, (int) len); + MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_write_ops_nolock: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); /* Initialize retlen, in case of early exit */ ops->retlen = 0; @@ -1161,7 +1163,7 @@ static int onenand_write_ops_nolock(struct mtd_info *mtd, loff_t to, wbuf = this->page_buf; } - this->write_bufferram(mtd, ONENAND_DATARAM, wbuf, 0, mtd->writesize); + this->write_bufferram(mtd, to, ONENAND_DATARAM, wbuf, 0, mtd->writesize); if (oob) { oobbuf = this->oob_buf; @@ -1180,7 +1182,7 @@ static int onenand_write_ops_nolock(struct mtd_info *mtd, loff_t to, } else oobbuf = (u_char *) ffchars; - this->write_bufferram(mtd, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize); + this->write_bufferram(mtd, 0, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize); this->command(mtd, ONENAND_CMD_PROG, to, mtd->writesize); @@ -1244,9 +1246,7 @@ static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to, to += ops->ooboffs; - MTDDEBUG(MTD_DEBUG_LEVEL3, - "onenand_write_oob_nolock: to = 0x%08x, len = %i\n", - (unsigned int) to, (int) len); + MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob_nolock: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); /* Initialize retlen, in case of early exit */ ops->oobretlen = 0; @@ -1293,7 +1293,7 @@ static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to, onenand_fill_auto_oob(mtd, oobbuf, buf, column, thislen); else memcpy(oobbuf + column, buf, thislen); - this->write_bufferram(mtd, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize); + this->write_bufferram(mtd, 0, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize); this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize); @@ -1466,7 +1466,14 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) while (len) { - /* TODO Check badblock */ + /* Check if we have a bad block, we do not erase bad blocks */ + if (instr->priv == 0 && onenand_block_isbad_nolock(mtd, addr, 0)) { + printk(KERN_WARNING "onenand_erase: attempt to erase" + " a bad block at addr 0x%08x\n", + (unsigned int) addr); + instr->state = MTD_ERASE_FAILED; + goto erase_exit; + } this->command(mtd, ONENAND_CMD_ERASE, addr, block_size); @@ -1482,8 +1489,16 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_erase: " "Failed erase, block %d\n", (unsigned)(addr >> this->erase_shift)); + if (ret == -EPERM) + printk("onenand_erase: " + "Device is write protected!!!\n"); + else + printk("onenand_erase: " + "Failed erase, block %d\n", + (unsigned)(addr >> this->erase_shift)); instr->state = MTD_ERASE_FAILED; instr->fail_addr = addr; + goto erase_exit; } @@ -1493,7 +1508,7 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) instr->state = MTD_ERASE_DONE; - erase_exit: +erase_exit: ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; /* Do call back function */ @@ -1569,23 +1584,30 @@ int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs) } /** - * onenand_unlock - [MTD Interface] Unlock block(s) - * @param mtd MTD device structure - * @param ofs offset relative to mtd start - * @param len number of bytes to unlock + * onenand_do_lock_cmd - [OneNAND Interface] Lock or unlock block(s) + * @param mtd MTD device structure + * @param ofs offset relative to mtd start + * @param len number of bytes to lock or unlock + * @param cmd lock or unlock command * - * Unlock one or more blocks + * Lock or unlock one or more blocks */ -int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) +static int onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, size_t len, int cmd) { struct onenand_chip *this = mtd->priv; int start, end, block, value, status; + int wp_status_mask; start = ofs >> this->erase_shift; end = len >> this->erase_shift; + if (cmd == ONENAND_CMD_LOCK) + wp_status_mask = ONENAND_WP_LS; + else + wp_status_mask = ONENAND_WP_US; + /* Continuous lock scheme */ - if (this->options & ONENAND_CONT_LOCK) { + if (this->options & ONENAND_HAS_CONT_LOCK) { /* Set start block address */ this->write_word(start, this->base + ONENAND_REG_START_BLOCK_ADDRESS); @@ -1593,7 +1615,7 @@ int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) this->write_word(end - 1, this->base + ONENAND_REG_END_BLOCK_ADDRESS); /* Write unlock command */ - this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0); + this->command(mtd, cmd, 0, 0); /* There's no return value */ this->wait(mtd, FL_UNLOCKING); @@ -1612,7 +1634,14 @@ int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) } /* Block lock scheme */ - for (block = start; block < end; block++) { + for (block = start; block < start + end; block++) { + /* Set block address */ + value = onenand_block_address(this, block); + this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); + /* Select DataRAM for DDP */ + value = onenand_bufferram_address(this, block); + this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); + /* Set start block address */ this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS); @@ -1627,11 +1656,6 @@ int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) & ONENAND_CTRL_ONGO) continue; - /* Set block address for read block status */ - value = onenand_block_address(this->device_id, block); - this->write_word(value, - this->base + ONENAND_REG_START_ADDRESS1); - /* Check lock status */ status = this->read_word(this->base + ONENAND_REG_WP_STATUS); if (!(status & ONENAND_WP_US)) @@ -1642,32 +1666,197 @@ int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) return 0; } +/** + * onenand_lock - [MTD Interface] Lock block(s) + * @param mtd MTD device structure + * @param ofs offset relative to mtd start + * @param len number of bytes to unlock + * + * Lock one or more blocks + */ +static int onenand_lock(struct mtd_info *mtd, loff_t ofs, size_t len) +{ + int ret; + + onenand_get_device(mtd, FL_LOCKING); + ret = onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_LOCK); + onenand_release_device(mtd); + return ret; +} + +/** + * onenand_unlock - [MTD Interface] Unlock block(s) + * @param mtd MTD device structure + * @param ofs offset relative to mtd start + * @param len number of bytes to unlock + * + * Unlock one or more blocks + */ +static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) +{ + int ret; + + onenand_get_device(mtd, FL_LOCKING); + ret = onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK); + onenand_release_device(mtd); + return ret; +} + +/** + * onenand_check_lock_status - [OneNAND Interface] Check lock status + * @param this onenand chip data structure + * + * Check lock status + */ +static int onenand_check_lock_status(struct onenand_chip *this) +{ + unsigned int value, block, status; + unsigned int end; + + end = this->chipsize >> this->erase_shift; + for (block = 0; block < end; block++) { + /* Set block address */ + value = onenand_block_address(this, block); + this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); + /* Select DataRAM for DDP */ + value = onenand_bufferram_address(this, block); + this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); + /* Set start block address */ + this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS); + + /* Check lock status */ + status = this->read_word(this->base + ONENAND_REG_WP_STATUS); + if (!(status & ONENAND_WP_US)) { + printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status); + return 0; + } + } + + return 1; +} + +/** + * onenand_unlock_all - [OneNAND Interface] unlock all blocks + * @param mtd MTD device structure + * + * Unlock all blocks + */ +static void onenand_unlock_all(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + loff_t ofs = 0; + size_t len = this->chipsize; + + if (this->options & ONENAND_HAS_UNLOCK_ALL) { + /* Set start block address */ + this->write_word(0, this->base + ONENAND_REG_START_BLOCK_ADDRESS); + /* Write unlock command */ + this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0); + + /* There's no return value */ + this->wait(mtd, FL_LOCKING); + + /* Sanity check */ + while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) + & ONENAND_CTRL_ONGO) + continue; + + return; + + /* Check lock status */ + if (onenand_check_lock_status(this)) + return; + + /* Workaround for all block unlock in DDP */ + if (ONENAND_IS_DDP(this)) { + /* All blocks on another chip */ + ofs = this->chipsize >> 1; + len = this->chipsize >> 1; + } + } + + onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK); +} + + +/** + * onenand_check_features - Check and set OneNAND features + * @param mtd MTD data structure + * + * Check and set OneNAND features + * - lock scheme + * - two plane + */ +static void onenand_check_features(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + unsigned int density, process; + + /* Lock scheme depends on density and process */ + density = onenand_get_density(this->device_id); + process = this->version_id >> ONENAND_VERSION_PROCESS_SHIFT; + + /* Lock scheme */ + switch (density) { + case ONENAND_DEVICE_DENSITY_4Gb: + this->options |= ONENAND_HAS_2PLANE; + + case ONENAND_DEVICE_DENSITY_2Gb: + /* 2Gb DDP don't have 2 plane */ + if (!ONENAND_IS_DDP(this)) + this->options |= ONENAND_HAS_2PLANE; + this->options |= ONENAND_HAS_UNLOCK_ALL; + + case ONENAND_DEVICE_DENSITY_1Gb: + /* A-Die has all block unlock */ + if (process) + this->options |= ONENAND_HAS_UNLOCK_ALL; + break; + + default: + /* Some OneNAND has continuous lock scheme */ + if (!process) + this->options |= ONENAND_HAS_CONT_LOCK; + break; + } + + if (this->options & ONENAND_HAS_CONT_LOCK) + printk(KERN_DEBUG "Lock scheme is Continuous Lock\n"); + if (this->options & ONENAND_HAS_UNLOCK_ALL) + printk(KERN_DEBUG "Chip support all block unlock\n"); + if (this->options & ONENAND_HAS_2PLANE) + printk(KERN_DEBUG "Chip has 2 plane\n"); +} + /** * onenand_print_device_info - Print device ID * @param device device ID * * Print device ID */ -char * onenand_print_device_info(int device) +char *onenand_print_device_info(int device, int version) { int vcc, demuxed, ddp, density; char *dev_info = malloc(80); + char *p = dev_info; vcc = device & ONENAND_DEVICE_VCC_MASK; demuxed = device & ONENAND_DEVICE_IS_DEMUX; ddp = device & ONENAND_DEVICE_IS_DDP; density = device >> ONENAND_DEVICE_DENSITY_SHIFT; - sprintf(dev_info, "%sOneNAND%s %dMB %sV 16-bit (0x%02x)", + p += sprintf(dev_info, "%sOneNAND%s %dMB %sV 16-bit (0x%02x)", demuxed ? "" : "Muxed ", ddp ? "(DDP)" : "", (16 << density), vcc ? "2.65/3.3" : "1.8", device); + sprintf(p, "\nOneNAND version = 0x%04x", version); + printk("%s\n", dev_info); + return dev_info; } static const struct onenand_manufacturers onenand_manuf_ids[] = { {ONENAND_MFR_SAMSUNG, "Samsung"}, - {ONENAND_MFR_UNKNOWN, "Unknown"} }; /** @@ -1678,19 +1867,24 @@ static const struct onenand_manufacturers onenand_manuf_ids[] = { */ static int onenand_check_maf(int manuf) { + int size = ARRAY_SIZE(onenand_manuf_ids); + char *name; int i; - for (i = 0; onenand_manuf_ids[i].id; i++) { + for (i = 0; size; i++) if (manuf == onenand_manuf_ids[i].id) break; - } + + if (i < size) + name = onenand_manuf_ids[i].name; + else + name = "Unknown"; #ifdef ONENAND_DEBUG - printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n", - onenand_manuf_ids[i].name, manuf); + printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n", name, manuf); #endif - return (i != ONENAND_MFR_UNKNOWN); + return i == size; } /** @@ -1703,9 +1897,14 @@ static int onenand_check_maf(int manuf) static int onenand_probe(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; - int bram_maf_id, bram_dev_id, maf_id, dev_id; - int version_id; + int bram_maf_id, bram_dev_id, maf_id, dev_id, ver_id; int density; + int syscfg; + + /* Save system configuration 1 */ + syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); + /* Clear Sync. Burst Read mode to read BootRAM */ + this->write_word((syscfg & ~ONENAND_SYS_CFG1_SYNC_READ), this->base + ONENAND_REG_SYS_CFG1); /* Send the command for reading device ID from BootRAM */ this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM); @@ -1714,19 +1913,23 @@ static int onenand_probe(struct mtd_info *mtd) bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0); bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2); - /* Check manufacturer ID */ - if (onenand_check_maf(bram_maf_id)) - return -ENXIO; - /* Reset OneNAND to read default register values */ this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM); /* Wait reset */ this->wait(mtd, FL_RESETING); + /* Restore system configuration 1 */ + this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); + + /* Check manufacturer ID */ + if (onenand_check_maf(bram_maf_id)) + return -ENXIO; + /* Read manufacturer and device IDs from Register */ maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID); dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID); + ver_id = this->read_word(this->base + ONENAND_REG_VERSION_ID); /* Check OneNAND device */ if (maf_id != bram_maf_id || dev_id != bram_dev_id) @@ -1739,11 +1942,16 @@ static int onenand_probe(struct mtd_info *mtd) } /* Flash device information */ - mtd->name = onenand_print_device_info(dev_id); + mtd->name = onenand_print_device_info(dev_id, ver_id); this->device_id = dev_id; - density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT; + density = onenand_get_density(dev_id); this->chipsize = (16 << density) << 20; + /* Set density mask. it is used for DDP */ + if (ONENAND_IS_DDP(this)) + this->density_mask = (1 << (density + 6)); + else + this->density_mask = 0; /* OneNAND page size & block size */ /* The data buffer size is equal to page size */ @@ -1764,18 +1972,8 @@ static int onenand_probe(struct mtd_info *mtd) mtd->size = this->chipsize; - /* Version ID */ - version_id = this->read_word(this->base + ONENAND_REG_VERSION_ID); -#ifdef ONENAND_DEBUG - printk(KERN_DEBUG "OneNAND version = 0x%04x\n", version_id); -#endif - - /* Lock scheme */ - if (density <= ONENAND_DEVICE_DENSITY_512Mb && - !(version_id >> ONENAND_VERSION_PROCESS_SHIFT)) { - printk(KERN_INFO "Lock scheme is Continues Lock\n"); - this->options |= ONENAND_CONT_LOCK; - } + /* Check OneNAND features */ + onenand_check_features(mtd); mtd->flags = MTD_CAP_NANDFLASH; mtd->erase = onenand_erase; @@ -1813,12 +2011,19 @@ int onenand_scan(struct mtd_info *mtd, int maxchips) this->command = onenand_command; if (!this->wait) this->wait = onenand_wait; + if (!this->bbt_wait) + this->bbt_wait = onenand_bbt_wait; if (!this->read_bufferram) this->read_bufferram = onenand_read_bufferram; + if (!this->read_spareram) + this->read_spareram = onenand_read_bufferram; if (!this->write_bufferram) this->write_bufferram = onenand_write_bufferram; + if (!this->scan_bbt) + this->scan_bbt = onenand_default_bbt; + if (onenand_probe(mtd)) return -ENXIO; @@ -1850,9 +2055,10 @@ int onenand_scan(struct mtd_info *mtd, int maxchips) this->options |= ONENAND_OOBBUF_ALLOC; } - onenand_unlock(mtd, 0, mtd->size); + /* Unlock whole block */ + onenand_unlock_all(mtd); - return onenand_default_bbt(mtd); + return this->scan_bbt(mtd); } /** diff --git a/drivers/mtd/onenand/onenand_bbt.c b/drivers/mtd/onenand/onenand_bbt.c index f6092b9be..d538f9582 100644 --- a/drivers/mtd/onenand/onenand_bbt.c +++ b/drivers/mtd/onenand/onenand_bbt.c @@ -3,7 +3,7 @@ * * Bad Block Table support for the OneNAND driver * - * Copyright(c) 2005-2007 Samsung Electronics + * Copyright(c) 2005-2008 Samsung Electronics * Kyungmin Park * * TODO: @@ -54,7 +54,7 @@ static int check_short_pattern(uint8_t * buf, int len, int paglen, * @param buf temporary buffer * @param bd descriptor for the good/bad block search pattern * @param chip create the table for a specific chip, -1 read all chips. - * Applies only if NAND_BBT_PERCHIP option is set + * Applies only if NAND_BBT_PERCHIP option is set * * Create a bad block table by scanning the device * for the given good/bad block identify pattern @@ -156,8 +156,8 @@ static int onenand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) res = (bbm->bbt[block >> 3] >> (block & 0x06)) & 0x03; MTDDEBUG (MTD_DEBUG_LEVEL2, - "onenand_isbad_bbt: bbt info for offs 0x%08x: (block %d) 0x%02x\n", - (unsigned int)offs, block >> 1, res); + "onenand_isbad_bbt: bbt info for offs 0x%08x: (block %d) 0x%02x\n", + (unsigned int)offs, block >> 1, res); switch ((int)res) { case 0x00: diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c index 08082f3ed..4541b2217 100644 --- a/drivers/mtd/onenand/onenand_uboot.c +++ b/drivers/mtd/onenand/onenand_uboot.c @@ -26,9 +26,17 @@ void onenand_init(void) memset(&onenand_mtd, 0, sizeof(struct mtd_info)); memset(&onenand_chip, 0, sizeof(struct onenand_chip)); - onenand_chip.base = (void *) CONFIG_SYS_ONENAND_BASE; onenand_mtd.priv = &onenand_chip; +#ifdef CONFIG_USE_ONENAND_BOARD_INIT + /* + * It's used for some board init required + */ + onenand_board_init(&onenand_mtd); +#else + onenand_chip.base = (void *) CONFIG_SYS_ONENAND_BASE; +#endif + onenand_scan(&onenand_mtd, 1); puts("OneNAND: "); diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h index 4467c2bb2..7547e96e7 100644 --- a/include/linux/mtd/onenand.h +++ b/include/linux/mtd/onenand.h @@ -30,14 +30,10 @@ extern void onenand_release (struct mtd_info *mtd); /** * struct onenand_bufferram - OneNAND BufferRAM Data - * @param block block address in BufferRAM - * @param page page address in BufferRAM - * @param valid valid flag + * @param blockpage block & page address in BufferRAM */ struct onenand_bufferram { - int block; - int page; - int valid; + int blockpage; }; /** @@ -70,6 +66,8 @@ struct onenand_chip { void __iomem *base; unsigned int chipsize; unsigned int device_id; + unsigned int version_id; + unsigned int density_mask; unsigned int options; unsigned int erase_shift; @@ -81,26 +79,35 @@ struct onenand_chip { unsigned int bufferram_index; struct onenand_bufferram bufferram[MAX_BUFFERRAM]; - int (*command) (struct mtd_info * mtd, int cmd, loff_t address, + int (*command) (struct mtd_info *mtd, int cmd, loff_t address, size_t len); - int (*wait) (struct mtd_info * mtd, int state); - int (*read_bufferram) (struct mtd_info * mtd, int area, + int (*wait) (struct mtd_info *mtd, int state); + int (*bbt_wait) (struct mtd_info *mtd, int state); + int (*read_bufferram) (struct mtd_info *mtd, loff_t addr, int area, unsigned char *buffer, int offset, size_t count); - int (*write_bufferram) (struct mtd_info * mtd, int area, + int (*read_spareram) (struct mtd_info *mtd, loff_t addr, int area, + unsigned char *buffer, int offset, size_t count); + int (*write_bufferram) (struct mtd_info *mtd, loff_t addr, int area, const unsigned char *buffer, int offset, size_t count); - unsigned short (*read_word) (void __iomem * addr); - void (*write_word) (unsigned short value, void __iomem * addr); - void (*mmcontrol) (struct mtd_info * mtd, int sync_read); + unsigned short (*read_word) (void __iomem *addr); + void (*write_word) (unsigned short value, void __iomem *addr); + void (*mmcontrol) (struct mtd_info *mtd, int sync_read); int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); int (*scan_bbt)(struct mtd_info *mtd); + unsigned char *main_buf; + unsigned char *spare_buf; +#ifdef DONT_USE_UBOOT + spinlock_t chip_lock; + wait_queue_head_t wq; +#endif int state; - unsigned char *page_buf; - unsigned char *oob_buf; + unsigned char *page_buf; + unsigned char *oob_buf; struct nand_oobinfo *autooob; - struct nand_ecclayout *ecclayout; + struct nand_ecclayout *ecclayout; void *bbm; @@ -125,7 +132,9 @@ struct onenand_chip { /* * Options bits */ -#define ONENAND_CONT_LOCK (0x0001) +#define ONENAND_HAS_CONT_LOCK (0x0001) +#define ONENAND_HAS_UNLOCK_ALL (0x0002) +#define ONENAND_HAS_2PLANE (0x0004) #define ONENAND_PAGEBUF_ALLOC (0x1000) #define ONENAND_OOBBUF_ALLOC (0x2000) @@ -133,7 +142,6 @@ struct onenand_chip { * OneNAND Flash Manufacturer ID Codes */ #define ONENAND_MFR_SAMSUNG 0xec -#define ONENAND_MFR_UNKNOWN 0x00 /** * struct nand_manufacturers - NAND Flash Manufacturer ID Structure diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h index a245e14bf..fc63380d9 100644 --- a/include/linux/mtd/onenand_regs.h +++ b/include/linux/mtd/onenand_regs.h @@ -119,6 +119,7 @@ #define ONENAND_CMD_UNLOCK (0x23) #define ONENAND_CMD_LOCK (0x2A) #define ONENAND_CMD_LOCK_TIGHT (0x2C) +#define ONENAND_CMD_UNLOCK_ALL (0x27) #define ONENAND_CMD_ERASE (0x94) #define ONENAND_CMD_RESET (0xF0) #define ONENAND_CMD_READID (0x90) diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h index e9602574b..5a4fded27 100644 --- a/include/onenand_uboot.h +++ b/include/onenand_uboot.h @@ -15,25 +15,29 @@ #define __UBOOT_ONENAND_H #include -#include struct mtd_info; struct erase_info; +struct onenand_chip; extern struct mtd_info onenand_mtd; +/* board */ +extern void onenand_board_init(struct mtd_info *); + /* Functions */ extern void onenand_init(void); extern int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf); -extern int onenand_read_oob(struct mtd_info *mtd, loff_t from, - struct mtd_oob_ops *ops); +extern int onenand_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops); extern int onenand_write(struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, const u_char * buf); extern int onenand_erase(struct mtd_info *mtd, struct erase_info *instr); -extern int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len); +extern char *onenand_print_device_info(int device, int version); -extern char *onenand_print_device_info(int device); +/* S3C64xx */ +extern void s3c64xx_onenand_init(struct mtd_info *); +extern void s3c64xx_set_width_regs(struct onenand_chip *); #endif /* __UBOOT_ONENAND_H */ From 1ac5744e33ee0aa6d6ddab3b99f9e70953156e69 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Tue, 4 Nov 2008 14:55:06 +0800 Subject: [PATCH 133/188] mpc83xx: enable eLBC NAND support for MPC8315ERDB board Signed-off-by: Dave Liu --- include/configs/MPC8315ERDB.h | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index add65f03d..48043c493 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -166,7 +166,7 @@ #undef CONFIG_SYS_RAMBOOT #endif -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -223,15 +223,17 @@ */ #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE +#define NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \ +#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \ | (2< Date: Tue, 11 Nov 2008 10:28:53 +0100 Subject: [PATCH 134/188] OneNAND: Fix compiler warnings Signed-off-by: Stefan Roese --- drivers/mtd/onenand/onenand_base.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 66214e86d..8d004d383 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -408,6 +408,30 @@ static int onenand_write_bufferram(struct mtd_info *mtd, loff_t addr, int area, return 0; } +/** + * onenand_get_2x_blockpage - [GENERIC] Get blockpage at 2x program mode + * @param mtd MTD data structure + * @param addr address to check + * @return blockpage address + * + * Get blockpage address at 2x program mode + */ +static int onenand_get_2x_blockpage(struct mtd_info *mtd, loff_t addr) +{ + struct onenand_chip *this = mtd->priv; + int blockpage, block, page; + + /* Calculate the even block number */ + block = (int) (addr >> this->erase_shift) & ~1; + /* Is it the odd plane? */ + if (addr & this->writesize) + block++; + page = (int) (addr >> (this->page_shift + 1)) & this->page_mask; + blockpage = (block << 7) | page; + + return blockpage; +} + /** * onenand_check_bufferram - [GENERIC] Check BufferRAM information * @param mtd MTD data structure @@ -1666,6 +1690,7 @@ static int onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, size_t len, int return 0; } +#ifdef ONENAND_LINUX /** * onenand_lock - [MTD Interface] Lock block(s) * @param mtd MTD device structure @@ -1701,6 +1726,7 @@ static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) onenand_release_device(mtd); return ret; } +#endif /** * onenand_check_lock_status - [OneNAND Interface] Check lock status From 8cf11f3aa78673730e9ecbbe4b75213b53f212c8 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 11 Nov 2008 10:29:09 +0100 Subject: [PATCH 135/188] OneNAND: Save version_id in onenand_chip struct The version (ver_id) was not stored in the onenand_chip structure and because of this the continuous locking scheme could be enabled on some chips. Signed-off-by: Stefan Roese --- drivers/mtd/onenand/onenand_base.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 8d004d383..f62b1aa25 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -1970,6 +1970,7 @@ static int onenand_probe(struct mtd_info *mtd) /* Flash device information */ mtd->name = onenand_print_device_info(dev_id, ver_id); this->device_id = dev_id; + this->version_id = ver_id; density = onenand_get_density(dev_id); this->chipsize = (16 << density) << 20; From c438ea175d8d002c1063b7a94b0c0e26668d1ac9 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 12 Nov 2008 13:47:24 +0100 Subject: [PATCH 136/188] OneNAND: Bad block aware read/write command support Update OneNAND command to support bad block awareness. Also change the OneNAND command style to better match the NAND version. Signed-off-by: Stefan Roese Acked-by: Kyungmin Park --- common/cmd_onenand.c | 528 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 419 insertions(+), 109 deletions(-) diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c index 8d87b787f..6a2c92492 100644 --- a/common/cmd_onenand.c +++ b/common/cmd_onenand.c @@ -1,7 +1,7 @@ /* * U-Boot command for OneNAND support * - * Copyright (C) 2005-2007 Samsung Electronics + * Copyright (C) 2005-2008 Samsung Electronics * Kyungmin Park * * This program is free software; you can redistribute it and/or modify @@ -11,6 +11,7 @@ #include #include +#include #include #include @@ -18,159 +19,468 @@ #include -extern struct mtd_info onenand_mtd; -extern struct onenand_chip onenand_chip; +static struct mtd_info *mtd; + +static loff_t next_ofs; +static loff_t skip_ofs; + +static inline int str2long(char *p, ulong *num) +{ + char *endptr; + + *num = simple_strtoul(p, &endptr, 16); + return (*p != '\0' && *endptr == '\0') ? 1 : 0; +} + +static int arg_off_size(int argc, char *argv[], ulong *off, size_t *size) +{ + if (argc >= 1) { + if (!(str2long(argv[0], off))) { + printf("'%s' is not a number\n", argv[0]); + return -1; + } + } else { + *off = 0; + } + + if (argc >= 2) { + if (!(str2long(argv[1], (ulong *)size))) { + printf("'%s' is not a number\n", argv[1]); + return -1; + } + } else { + *size = mtd->size - *off; + } + + if ((*off + *size) > mtd->size) { + printf("total chip size (0x%x) exceeded!\n", mtd->size); + return -1; + } + + if (*size == mtd->size) + puts("whole chip\n"); + else + printf("offset 0x%lx, size 0x%x\n", *off, *size); + + return 0; +} + +static int onenand_block_read(loff_t from, size_t len, + size_t *retlen, u_char *buf, int oob) +{ + struct onenand_chip *this = mtd->priv; + int blocks = (int) len >> this->erase_shift; + int blocksize = (1 << this->erase_shift); + loff_t ofs = from; + struct mtd_oob_ops ops = { + .retlen = 0, + }; + int ret; + + if (oob) + ops.ooblen = blocksize; + else + ops.len = blocksize; + + while (blocks) { + ret = mtd->block_isbad(mtd, ofs); + if (ret) { + printk("Bad blocks %d at 0x%x\n", + (u32)(ofs >> this->erase_shift), (u32)ofs); + ofs += blocksize; + continue; + } + + if (oob) + ops.oobbuf = buf; + else + ops.datbuf = buf; + + ops.retlen = 0; + ret = mtd->read_oob(mtd, ofs, &ops); + if (ret) { + printk("Read failed 0x%x, %d\n", (u32)ofs, ret); + ofs += blocksize; + continue; + } + ofs += blocksize; + buf += blocksize; + blocks--; + *retlen += ops.retlen; + } + + return 0; +} + +static int onenand_block_write(loff_t to, size_t len, + size_t *retlen, const u_char * buf) +{ + struct onenand_chip *this = mtd->priv; + int blocks = len >> this->erase_shift; + int blocksize = (1 << this->erase_shift); + loff_t ofs; + size_t _retlen = 0; + int ret; + + if (to == next_ofs) { + next_ofs = to + len; + to += skip_ofs; + } else { + next_ofs = to + len; + skip_ofs = 0; + } + ofs = to; + + while (blocks) { + ret = mtd->block_isbad(mtd, ofs); + if (ret) { + printk("Bad blocks %d at 0x%x\n", + (u32)(ofs >> this->erase_shift), (u32)ofs); + skip_ofs += blocksize; + goto next; + } + + ret = mtd->write(mtd, ofs, blocksize, &_retlen, buf); + if (ret) { + printk("Write failed 0x%x, %d", (u32)ofs, ret); + skip_ofs += blocksize; + goto next; + } + + buf += blocksize; + blocks--; + *retlen += _retlen; +next: + ofs += blocksize; + } + + return 0; +} + +static int onenand_block_erase(u32 start, u32 size, int force) +{ + struct onenand_chip *this = mtd->priv; + struct erase_info instr = { + .callback = NULL, + }; + loff_t ofs; + int ret; + int blocksize = 1 << this->erase_shift; + + for (ofs = start; ofs < (start + size); ofs += blocksize) { + ret = mtd->block_isbad(mtd, ofs); + if (ret && !force) { + printf("Skip erase bad block %d at 0x%x\n", + (u32)(ofs >> this->erase_shift), (u32)ofs); + continue; + } + + instr.addr = ofs; + instr.len = blocksize; + instr.priv = force; + instr.mtd = mtd; + ret = mtd->erase(mtd, &instr); + if (ret) { + printf("erase failed block %d at 0x%x\n", + (u32)(ofs >> this->erase_shift), (u32)ofs); + continue; + } + } + + return 0; +} + +static int onenand_block_test(u32 start, u32 size) +{ + struct onenand_chip *this = mtd->priv; + struct erase_info instr = { + .callback = NULL, + .priv = 0, + }; + + int blocks; + loff_t ofs; + int blocksize = 1 << this->erase_shift; + int start_block, end_block; + size_t retlen; + u_char *buf; + u_char *verify_buf; + int ret; + + buf = malloc(blocksize); + if (!buf) { + printf("Not enough malloc space available!\n"); + return -1; + } + + verify_buf = malloc(blocksize); + if (!verify_buf) { + printf("Not enough malloc space available!\n"); + return -1; + } + + start_block = start >> this->erase_shift; + end_block = (start + size) >> this->erase_shift; + + /* Protect boot-loader from badblock testing */ + if (start_block < 2) + start_block = 2; + + if (end_block > (mtd->size >> this->erase_shift)) + end_block = mtd->size >> this->erase_shift; + + blocks = start_block; + ofs = start; + while (blocks < end_block) { + printf("\rTesting block %d at 0x%x", (u32)(ofs >> this->erase_shift), (u32)ofs); + + ret = mtd->block_isbad(mtd, ofs); + if (ret) { + printf("Skip erase bad block %d at 0x%x\n", + (u32)(ofs >> this->erase_shift), (u32)ofs); + goto next; + } + + instr.addr = ofs; + instr.len = blocksize; + ret = mtd->erase(mtd, &instr); + if (ret) { + printk("Erase failed 0x%x, %d\n", (u32)ofs, ret); + goto next; + } + + ret = mtd->write(mtd, ofs, blocksize, &retlen, buf); + if (ret) { + printk("Write failed 0x%x, %d\n", (u32)ofs, ret); + goto next; + } + + ret = mtd->read(mtd, ofs, blocksize, &retlen, verify_buf); + if (ret) { + printk("Read failed 0x%x, %d\n", (u32)ofs, ret); + goto next; + } + + if (memcmp(buf, verify_buf, blocksize)) + printk("\nRead/Write test failed at 0x%x\n", (u32)ofs); + +next: + ofs += blocksize; + blocks++; + } + printf("...Done\n"); + + free(buf); + free(verify_buf); + + return 0; +} + +static int onenand_dump(struct mtd_info *mtd, ulong off, int only_oob) +{ + int i; + u_char *datbuf, *oobbuf, *p; + struct mtd_oob_ops ops; + loff_t addr; + + datbuf = malloc(mtd->writesize + mtd->oobsize); + oobbuf = malloc(mtd->oobsize); + if (!datbuf || !oobbuf) { + puts("No memory for page buffer\n"); + return 1; + } + off &= ~(mtd->writesize - 1); + addr = (loff_t) off; + memset(&ops, 0, sizeof(ops)); + ops.datbuf = datbuf; + ops.oobbuf = oobbuf; /* must exist, but oob data will be appended to ops.datbuf */ + ops.len = mtd->writesize; + ops.ooblen = mtd->oobsize; + ops.retlen = 0; + i = mtd->read_oob(mtd, addr, &ops); + if (i < 0) { + printf("Error (%d) reading page %08lx\n", i, off); + free(datbuf); + free(oobbuf); + return 1; + } + printf("Page %08lx dump:\n", off); + i = mtd->writesize >> 4; + p = datbuf; + + while (i--) { + if (!only_oob) + printf("\t%02x %02x %02x %02x %02x %02x %02x %02x" + " %02x %02x %02x %02x %02x %02x %02x %02x\n", + p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], + p[8], p[9], p[10], p[11], p[12], p[13], p[14], + p[15]); + p += 16; + } + puts("OOB:\n"); + i = mtd->oobsize >> 3; + while (i--) { + printf("\t%02x %02x %02x %02x %02x %02x %02x %02x\n", + p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); + p += 8; + } + free(datbuf); + free(oobbuf); + + return 0; +} int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - int ret = 0; + struct onenand_chip *this; + int blocksize; + ulong addr, ofs; + size_t len, retlen = 0; + int ret; + char *cmd, *s; + + mtd = &onenand_mtd; + this = mtd->priv; + blocksize = (1 << this->erase_shift); + + cmd = argv[1]; switch (argc) { case 0: case 1: - printf("Usage:\n%s\n", cmdtp->usage); - return 1; + goto usage; case 2: - if (strncmp(argv[1], "open", 4) == 0) { - onenand_init(); + if (strcmp(cmd, "info") == 0) { + printf("%s\n", mtd->name); + return 0; + } + + if (strcmp(cmd, "bad") == 0) { + /* Currently only one OneNAND device is supported */ + printf("\nDevice %d bad blocks:\n", 0); + for (ofs = 0; ofs < mtd->size; ofs += mtd->erasesize) { + if (mtd->block_isbad(mtd, ofs)) + printf(" %08x\n", (u32)ofs); + } + return 0; } - printf("%s\n", onenand_mtd.name); - return 0; default: /* At least 4 args */ - if (strncmp(argv[1], "erase", 5) == 0) { - struct erase_info instr = { - .callback = NULL, - }; - ulong start, end; - ulong block; - char *endtail; - if (strncmp(argv[2], "block", 5) == 0) { - start = simple_strtoul(argv[3], NULL, 10); - endtail = strchr(argv[3], '-'); - end = simple_strtoul(endtail + 1, NULL, 10); - } else { - start = simple_strtoul(argv[2], NULL, 10); - end = simple_strtoul(argv[3], NULL, 10); + /* + * Syntax is: + * 0 1 2 3 4 + * onenand erase [force] [off size] + */ + if ((strcmp(cmd, "erase") == 0) || (strcmp(cmd, "test") == 0)) { + int force = argc > 2 && !strcmp("force", argv[2]); + int o = force ? 3 : 2; + int erase; - start >>= onenand_chip.erase_shift; - end >>= onenand_chip.erase_shift; - /* Don't include the end block */ - end--; - } + erase = strcmp(cmd, "erase") == 0; /* 1 = erase, 0 = test */ + printf("\nOneNAND %s: ", erase ? "erase" : "test"); - if (!end || end < 0) - end = start; + /* skip first two or three arguments, look for offset and size */ + if (arg_off_size(argc - o, argv + o, &ofs, &len) != 0) + return 1; - printf("Erase block from %lu to %lu\n", start, end); + if (erase) + ret = onenand_block_erase(ofs, len, force); + else + ret = onenand_block_test(ofs, len); - for (block = start; block <= end; block++) { - instr.addr = block << onenand_chip.erase_shift; - instr.len = 1 << onenand_chip.erase_shift; - ret = onenand_erase(&onenand_mtd, &instr); - if (ret) { - printf("erase failed %lu\n", block); - break; - } - } + printf("%s\n", ret ? "ERROR" : "OK"); - return 0; + return ret == 0 ? 0 : 1; } - if (strncmp(argv[1], "read", 4) == 0) { - ulong addr = simple_strtoul(argv[2], NULL, 16); - ulong ofs = simple_strtoul(argv[3], NULL, 16); - size_t len = simple_strtoul(argv[4], NULL, 16); - int oob = strncmp(argv[1], "read.oob", 8) ? 0 : 1; - struct mtd_oob_ops ops; + if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) { + int read; + int oob = 0; - ops.mode = MTD_OOB_PLACE; + if (argc < 4) + goto usage; - if (oob) { - ops.len = 0; - ops.datbuf = NULL; - ops.ooblen = len; - ops.oobbuf = (u_char *) addr; + addr = (ulong)simple_strtoul(argv[2], NULL, 16); + + read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */ + printf("\nOneNAND %s: ", read ? "read" : "write"); + if (arg_off_size(argc - 3, argv + 3, &ofs, &len) != 0) + return 1; + + s = strchr(cmd, '.'); + if ((s != NULL) && (!strcmp(s, ".oob"))) + oob = 1; + + if (read) { + ret = onenand_block_read(ofs, len, &retlen, + (u8 *)addr, oob); } else { - ops.len = len; - ops.datbuf = (u_char *) addr; - ops.ooblen = 0; - ops.oobbuf = NULL; + ret = onenand_block_write(ofs, len, &retlen, + (u8 *)addr); } - ops.retlen = ops.oobretlen = 0; - onenand_mtd.read_oob(&onenand_mtd, ofs, &ops); - printf("Done\n"); + printf(" %d bytes %s: %s\n", retlen, + read ? "read" : "written", ret ? "ERROR" : "OK"); - return 0; + return ret == 0 ? 0 : 1; } - if (strncmp(argv[1], "write", 5) == 0) { - ulong addr = simple_strtoul(argv[2], NULL, 16); - ulong ofs = simple_strtoul(argv[3], NULL, 16); - size_t len = simple_strtoul(argv[4], NULL, 16); - size_t retlen = 0; + if (strcmp(cmd, "markbad") == 0) { + addr = (ulong)simple_strtoul(argv[2], NULL, 16); - onenand_write(&onenand_mtd, ofs, len, &retlen, - (u_char *) addr); - printf("Done\n"); - - return 0; + int ret = mtd->block_markbad(mtd, addr); + if (ret == 0) { + printf("block 0x%08lx successfully marked as bad\n", + (ulong) addr); + return 0; + } else { + printf("block 0x%08lx NOT marked as bad! ERROR %d\n", + (ulong) addr, ret); + } + return 1; } - if (strncmp(argv[1], "block", 5) == 0) { - ulong addr = simple_strtoul(argv[2], NULL, 16); - ulong block = simple_strtoul(argv[3], NULL, 10); - ulong page = simple_strtoul(argv[4], NULL, 10); - size_t len = simple_strtol(argv[5], NULL, 10); - ulong ofs; - int oob = strncmp(argv[1], "block.oob", 9) ? 0 : 1; - struct mtd_oob_ops ops; + if (strncmp(cmd, "dump", 4) == 0) { + if (argc < 3) + goto usage; - ops.mode = MTD_OOB_PLACE; + s = strchr(cmd, '.'); + ofs = (int)simple_strtoul(argv[2], NULL, 16); + if (s != NULL && strcmp(s, ".oob") == 0) + ret = onenand_dump(mtd, ofs, 1); + else + ret = onenand_dump(mtd, ofs, 0); - ofs = block << onenand_chip.erase_shift; - if (page) - ofs += page << onenand_chip.page_shift; - - if (!len) { - if (oob) - ops.ooblen = 64; - else - ops.len = 512; - } - - if (oob) { - ops.datbuf = NULL; - ops.oobbuf = (u_char *) addr; - } else { - ops.datbuf = (u_char *) addr; - ops.oobbuf = NULL; - } - ops.retlen = ops.oobretlen = 0; - - onenand_read_oob(&onenand_mtd, ofs, &ops); - return 0; + return ret == 0 ? 1 : 0; } break; } return 0; + +usage: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; } U_BOOT_CMD( onenand, 6, 1, do_onenand, "onenand - OneNAND sub-system\n", - "info - show available OneNAND devices\n" - "onenand read[.oob] addr ofs len - read data at ofs with len to addr\n" - "onenand write addr ofs len - write data at ofs with len from addr\n" - "onenand erase saddr eaddr - erase block start addr to end addr\n" - "onenand block[.oob] addr block [page] [len] - " - "read data with (block [, page]) to addr" + "info - show available OneNAND devices\n" + "onenand bad - show bad blocks\n" + "onenand read[.oob] addr off size\n" + "onenand write[.oob] addr off size\n" + " read/write 'size' bytes starting at offset 'off'\n" + " to/from memory address 'addr', skipping bad blocks.\n" + "onenand erase [force] [off size] - erase 'size' bytes from\n" + "onenand test [off size] - test 'size' bytes from\n" + " offset 'off' (entire device if not specified)\n" + "onenand dump[.oob] off - dump page\n" + "onenand markbad off - mark bad block at offset (UNSAFE)\n" ); From 1714f51a2009baaecf3d4f6e3bd8c4e93a8d3f23 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Thu, 13 Nov 2008 15:14:33 +0900 Subject: [PATCH 137/188] Add markbad function Add missing markbad function If not, it's hang when it entered the mtd->mark_bad(). Signed-off-by: Kyungmin Park --- drivers/mtd/onenand/onenand_base.c | 33 ++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index f62b1aa25..dcc969ff7 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -1583,6 +1583,37 @@ int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs) return ret; } +/** + * onenand_default_block_markbad - [DEFAULT] mark a block bad + * @param mtd MTD device structure + * @param ofs offset from device start + * + * This is the default implementation, which can be overridden by + * a hardware specific driver. + */ +static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) +{ + struct onenand_chip *this = mtd->priv; + struct bbm_info *bbm = this->bbm; + u_char buf[2] = {0, 0}; + struct mtd_oob_ops ops = { + .mode = MTD_OOB_PLACE, + .ooblen = 2, + .oobbuf = buf, + .ooboffs = 0, + }; + int block; + + /* Get block number */ + block = ((int) ofs) >> bbm->bbt_erase_shift; + if (bbm->bbt) + bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); + + /* We write two bytes, so we dont have to mess with 16 bit access */ + ofs += mtd->oobsize + (bbm->badblockpos & ~0x01); + return onenand_write_oob_nolock(mtd, ofs, &ops); +} + /** * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad * @param mtd MTD device structure @@ -2048,6 +2079,8 @@ int onenand_scan(struct mtd_info *mtd, int maxchips) if (!this->write_bufferram) this->write_bufferram = onenand_write_bufferram; + if (!this->block_markbad) + this->block_markbad = onenand_default_block_markbad; if (!this->scan_bbt) this->scan_bbt = onenand_default_bbt; From 1ae39862044ebb1e682234b51f94421e3f871d6a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 2 Dec 2008 11:06:47 +0100 Subject: [PATCH 138/188] OneNAND: Additional sync with 2.6.27 - Add subpage write support - Add onenand_oob_64/32 ecclayout This has been missing and without it UBI has some incompatibilies issues with the current (>= 2.6.27) Linux kernel version. vid_hdr_offset is placed differently (2048 instead of 512) without this fix. Signed-off-by: Stefan Roese Signed-off-by: Scott Wood --- drivers/mtd/onenand/onenand_base.c | 72 +++++++++++++++++++++++++++++- include/linux/mtd/onenand.h | 1 + 2 files changed, 72 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index dcc969ff7..d482437a4 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -36,6 +36,35 @@ static inline void *memcpy_16(void *dst, const void *src, unsigned int len) return ret; } +/** + * onenand_oob_64 - oob info for large (2KB) page + */ +static struct nand_ecclayout onenand_oob_64 = { + .eccbytes = 20, + .eccpos = { + 8, 9, 10, 11, 12, + 24, 25, 26, 27, 28, + 40, 41, 42, 43, 44, + 56, 57, 58, 59, 60, + }, + .oobfree = { + {2, 3}, {14, 2}, {18, 3}, {30, 2}, + {34, 3}, {46, 2}, {50, 3}, {62, 2} + } +}; + +/** + * onenand_oob_32 - oob info for middle (1KB) page + */ +static struct nand_ecclayout onenand_oob_32 = { + .eccbytes = 10, + .eccpos = { + 8, 9, 10, 11, 12, + 24, 25, 26, 27, 28, + }, + .oobfree = { {2, 3}, {14, 2}, {18, 3}, {30, 2} } +}; + static const unsigned char ffchars[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */ @@ -1079,7 +1108,7 @@ static int onenand_verify(struct mtd_info *mtd, const u_char *buf, loff_t addr, #define onenand_verify_oob(...) (0) #endif -#define NOTALIGNED(x) ((x & (mtd->writesize - 1)) != 0) +#define NOTALIGNED(x) ((x & (this->subpagesize - 1)) != 0) /** * onenand_fill_auto_oob - [Internal] oob auto-placement transfer @@ -2058,6 +2087,7 @@ static int onenand_probe(struct mtd_info *mtd) */ int onenand_scan(struct mtd_info *mtd, int maxchips) { + int i; struct onenand_chip *this = mtd->priv; if (!this->read_word) @@ -2115,6 +2145,46 @@ int onenand_scan(struct mtd_info *mtd, int maxchips) this->options |= ONENAND_OOBBUF_ALLOC; } + this->state = FL_READY; + + /* + * Allow subpage writes up to oobsize. + */ + switch (mtd->oobsize) { + case 64: + this->ecclayout = &onenand_oob_64; + mtd->subpage_sft = 2; + break; + + case 32: + this->ecclayout = &onenand_oob_32; + mtd->subpage_sft = 1; + break; + + default: + printk(KERN_WARNING "No OOB scheme defined for oobsize %d\n", + mtd->oobsize); + mtd->subpage_sft = 0; + /* To prevent kernel oops */ + this->ecclayout = &onenand_oob_32; + break; + } + + this->subpagesize = mtd->writesize >> mtd->subpage_sft; + + /* + * The number of bytes available for a client to place data into + * the out of band area + */ + this->ecclayout->oobavail = 0; + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && + this->ecclayout->oobfree[i].length; i++) + this->ecclayout->oobavail += + this->ecclayout->oobfree[i].length; + mtd->oobavail = this->ecclayout->oobavail; + + mtd->ecclayout = this->ecclayout; + /* Unlock whole block */ onenand_unlock_all(mtd); diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h index 7547e96e7..2597e347b 100644 --- a/include/linux/mtd/onenand.h +++ b/include/linux/mtd/onenand.h @@ -107,6 +107,7 @@ struct onenand_chip { unsigned char *oob_buf; struct nand_oobinfo *autooob; + int subpagesize; struct nand_ecclayout *ecclayout; void *bbm; From 69fb8be4fc07162fdf6edf04bdc7233b0e9a920e Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sat, 6 Dec 2008 02:40:55 -0500 Subject: [PATCH 139/188] NAND: move board_nand_init to nand.h Rather than putting the function prototype for board_nand_init() in the one place where it gets called, put it into nand.h so that every place that also defines it gets the prototype. Otherwise, errors can go silently unnoticed such as using the wrong return value (void rather than int) when defining the function. Signed-off-by: Mike Frysinger Signed-off-by: Scott Wood --- drivers/mtd/nand/nand.c | 2 -- include/nand.h | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c index eeb19ff1b..cf9261786 100644 --- a/drivers/mtd/nand/nand.c +++ b/drivers/mtd/nand/nand.c @@ -36,8 +36,6 @@ static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIS static const char default_nand_name[] = "nand"; -extern int board_nand_init(struct nand_chip *nand); - static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand, ulong base_addr) { diff --git a/include/nand.h b/include/nand.h index b4f316f71..065a42c3e 100644 --- a/include/nand.h +++ b/include/nand.h @@ -31,6 +31,8 @@ extern void nand_init(void); #include #include +extern int board_nand_init(struct nand_chip *nand); + typedef struct mtd_info nand_info_t; extern int nand_curr_device; From 50657c273278f74378e1ac39b41d612b92fdffa0 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Sat, 13 Dec 2008 09:43:06 -0600 Subject: [PATCH 140/188] NAND: Enable nand lock, unlock feature Enable nand lock, unlock and status of lock feature. Not every device and platform requires this, hence, it is under define for CONFIG_CMD_NAND_LOCK_UNLOCK Nand unlock and status operate on block boundary instead of page boundary. Details in: http://www.micron.com/products/partdetail?part=MT29C2G24MAKLAJG-6%20IT Intial solution provided by Vikram Pandita Includes preliminary suggestions from Scott Wood Signed-off-by: Nishanth Menon Signed-off-by: Scott Wood --- common/cmd_nand.c | 96 ++++++++++++++++++------------------ drivers/mtd/nand/nand_util.c | 79 +++++++++++++++-------------- 2 files changed, 92 insertions(+), 83 deletions(-) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 0a366d32c..a240c37b7 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -164,6 +164,47 @@ out: return 0; } +#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK +static void print_status(ulong start, ulong end, ulong erasesize, int status) +{ + printf("%08lx - %08lx: %08lx blocks %s%s%s\n", + start, + end - 1, + (end - start) / erasesize, + ((status & NAND_LOCK_STATUS_TIGHT) ? "TIGHT " : ""), + ((status & NAND_LOCK_STATUS_LOCK) ? "LOCK " : ""), + ((status & NAND_LOCK_STATUS_UNLOCK) ? "UNLOCK " : "")); +} + +static void do_nand_status(nand_info_t *nand) +{ + ulong block_start = 0; + ulong off; + int last_status = -1; + + struct nand_chip *nand_chip = nand->priv; + /* check the WP bit */ + nand_chip->cmdfunc(nand, NAND_CMD_STATUS, -1, -1); + printf("device is %swrite protected\n", + (nand_chip->read_byte(nand) & 0x80 ? + "NOT " : "")); + + for (off = 0; off < nand->size; off += nand->erasesize) { + int s = nand_get_lock_status(nand, off); + + /* print message only if status has changed */ + if (s != last_status && off != 0) { + print_status(block_start, off, nand->erasesize, + last_status); + block_start = off; + } + last_status = s; + } + /* Print the last block info */ + print_status(block_start, off, nand->erasesize, last_status); +} +#endif + int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int i, dev, ret = 0; @@ -383,8 +424,9 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 1; } +#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK if (strcmp(cmd, "lock") == 0) { - int tight = 0; + int tight = 0; int status = 0; if (argc == 3) { if (!strcmp("tight", argv[2])) @@ -392,44 +434,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) if (!strcmp("status", argv[2])) status = 1; } -/* - * ! BROKEN ! - * - * TODO: must be implemented and tested by someone with HW - */ -#if 0 if (status) { - ulong block_start = 0; - ulong off; - int last_status = -1; - - struct nand_chip *nand_chip = nand->priv; - /* check the WP bit */ - nand_chip->cmdfunc (nand, NAND_CMD_STATUS, -1, -1); - printf("device is %swrite protected\n", - (nand_chip->read_byte(nand) & 0x80 ? - "NOT " : "")); - - for (off = 0; off < nand->size; off += nand->writesize) { - int s = nand_get_lock_status(nand, off); - - /* print message only if status has changed - * or at end of chip - */ - if (off == nand->size - nand->writesize - || (s != last_status && off != 0)) { - - printf("%08lx - %08lx: %8d pages %s%s%s\n", - block_start, - off-1, - (off-block_start)/nand->writesize, - ((last_status & NAND_LOCK_STATUS_TIGHT) ? "TIGHT " : ""), - ((last_status & NAND_LOCK_STATUS_LOCK) ? "LOCK " : ""), - ((last_status & NAND_LOCK_STATUS_UNLOCK) ? "UNLOCK " : "")); - } - - last_status = s; - } + do_nand_status(nand); } else { if (!nand_lock(nand, tight)) { puts("NAND flash successfully locked\n"); @@ -438,7 +444,6 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 1; } } -#endif return 0; } @@ -446,12 +451,6 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) if (arg_off_size(argc - 2, argv + 2, nand, &off, &size) < 0) return 1; -/* - * ! BROKEN ! - * - * TODO: must be implemented and tested by someone with HW - */ -#if 0 if (!nand_unlock(nand, off, size)) { puts("NAND flash successfully unlocked\n"); } else { @@ -459,9 +458,9 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) "write and erase will probably fail\n"); return 1; } -#endif return 0; } +#endif usage: printf("Usage:\n%s\n", cmdtp->usage); @@ -483,9 +482,12 @@ U_BOOT_CMD(nand, 5, 1, do_nand, "nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n" "nand markbad off - mark bad block at offset (UNSAFE)\n" "nand biterr off - make a bit error at offset (UNSAFE)\n" +#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK "nand lock [tight] [status]\n" " bring nand to lock state or display locked pages\n" - "nand unlock [offset] [size] - unlock section\n"); + "nand unlock [offset] [size] - unlock section\n" +#endif +); static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, ulong offset, ulong addr, char *cmd) diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index d86c98737..77da53e26 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -238,7 +238,8 @@ static struct nand_ecclayout autoplace_ecclayout = { #endif /* XXX U-BOOT XXX */ -#if 0 +#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK + /****************************************************************************** * Support for locking / unlocking operations of some NAND devices *****************************************************************************/ @@ -253,7 +254,7 @@ static struct nand_ecclayout autoplace_ecclayout = { * nand_lock: Set all pages of NAND flash chip to the LOCK or LOCK-TIGHT * state * - * @param meminfo nand mtd instance + * @param mtd nand mtd instance * @param tight bring device in lock tight mode * * @return 0 on success, -1 in case of error @@ -270,21 +271,21 @@ static struct nand_ecclayout autoplace_ecclayout = { * calls will fail. It is only posible to leave lock-tight state by * an hardware signal (low pulse on _WP pin) or by power down. */ -int nand_lock(nand_info_t *meminfo, int tight) +int nand_lock(struct mtd_info *mtd, int tight) { int ret = 0; int status; - struct nand_chip *this = meminfo->priv; + struct nand_chip *chip = mtd->priv; /* select the NAND device */ - this->select_chip(meminfo, 0); + chip->select_chip(mtd, 0); - this->cmdfunc(meminfo, + chip->cmdfunc(mtd, (tight ? NAND_CMD_LOCK_TIGHT : NAND_CMD_LOCK), -1, -1); /* call wait ready function */ - status = this->waitfunc(meminfo, this, FL_WRITING); + status = chip->waitfunc(mtd, chip); /* see if device thinks it succeeded */ if (status & 0x01) { @@ -292,7 +293,7 @@ int nand_lock(nand_info_t *meminfo, int tight) } /* de-select the NAND device */ - this->select_chip(meminfo, -1); + chip->select_chip(mtd, -1); return ret; } @@ -300,7 +301,7 @@ int nand_lock(nand_info_t *meminfo, int tight) * nand_get_lock_status: - query current lock state from one page of NAND * flash * - * @param meminfo nand mtd instance + * @param mtd nand mtd instance * @param offset page address to query (muss be page aligned!) * * @return -1 in case of error @@ -311,19 +312,19 @@ int nand_lock(nand_info_t *meminfo, int tight) * NAND_LOCK_STATUS_UNLOCK: page unlocked * */ -int nand_get_lock_status(nand_info_t *meminfo, ulong offset) +int nand_get_lock_status(struct mtd_info *mtd, ulong offset) { int ret = 0; int chipnr; int page; - struct nand_chip *this = meminfo->priv; + struct nand_chip *chip = mtd->priv; /* select the NAND device */ - chipnr = (int)(offset >> this->chip_shift); - this->select_chip(meminfo, chipnr); + chipnr = (int)(offset >> chip->chip_shift); + chip->select_chip(mtd, chipnr); - if ((offset & (meminfo->writesize - 1)) != 0) { + if ((offset & (mtd->writesize - 1)) != 0) { printf ("nand_get_lock_status: " "Start address must be beginning of " "nand page!\n"); @@ -332,16 +333,16 @@ int nand_get_lock_status(nand_info_t *meminfo, ulong offset) } /* check the Lock Status */ - page = (int)(offset >> this->page_shift); - this->cmdfunc(meminfo, NAND_CMD_LOCK_STATUS, -1, page & this->pagemask); + page = (int)(offset >> chip->page_shift); + chip->cmdfunc(mtd, NAND_CMD_LOCK_STATUS, -1, page & chip->pagemask); - ret = this->read_byte(meminfo) & (NAND_LOCK_STATUS_TIGHT + ret = chip->read_byte(mtd) & (NAND_LOCK_STATUS_TIGHT | NAND_LOCK_STATUS_LOCK | NAND_LOCK_STATUS_UNLOCK); out: /* de-select the NAND device */ - this->select_chip(meminfo, -1); + chip->select_chip(mtd, -1); return ret; } @@ -349,59 +350,65 @@ int nand_get_lock_status(nand_info_t *meminfo, ulong offset) * nand_unlock: - Unlock area of NAND pages * only one consecutive area can be unlocked at one time! * - * @param meminfo nand mtd instance + * @param mtd nand mtd instance * @param start start byte address * @param length number of bytes to unlock (must be a multiple of * page size nand->writesize) * * @return 0 on success, -1 in case of error */ -int nand_unlock(nand_info_t *meminfo, ulong start, ulong length) +int nand_unlock(struct mtd_info *mtd, ulong start, ulong length) { int ret = 0; int chipnr; int status; int page; - struct nand_chip *this = meminfo->priv; + struct nand_chip *chip = mtd->priv; printf ("nand_unlock: start: %08x, length: %d!\n", (int)start, (int)length); /* select the NAND device */ - chipnr = (int)(start >> this->chip_shift); - this->select_chip(meminfo, chipnr); + chipnr = (int)(start >> chip->chip_shift); + chip->select_chip(mtd, chipnr); /* check the WP bit */ - this->cmdfunc(meminfo, NAND_CMD_STATUS, -1, -1); - if ((this->read_byte(meminfo) & 0x80) == 0) { + chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); + if (!(chip->read_byte(mtd) & NAND_STATUS_WP)) { printf ("nand_unlock: Device is write protected!\n"); ret = -1; goto out; } - if ((start & (meminfo->writesize - 1)) != 0) { + if ((start & (mtd->erasesize - 1)) != 0) { printf ("nand_unlock: Start address must be beginning of " - "nand page!\n"); + "nand block!\n"); ret = -1; goto out; } - if (length == 0 || (length & (meminfo->writesize - 1)) != 0) { - printf ("nand_unlock: Length must be a multiple of nand page " - "size!\n"); + if (length == 0 || (length & (mtd->erasesize - 1)) != 0) { + printf ("nand_unlock: Length must be a multiple of nand block " + "size %08x!\n", mtd->erasesize); ret = -1; goto out; } + /* + * Set length so that the last address is set to the + * starting address of the last block + */ + length -= mtd->erasesize; + /* submit address of first page to unlock */ - page = (int)(start >> this->page_shift); - this->cmdfunc(meminfo, NAND_CMD_UNLOCK1, -1, page & this->pagemask); + page = (int)(start >> chip->page_shift); + chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); /* submit ADDRESS of LAST page to unlock */ - page += (int)(length >> this->page_shift) - 1; - this->cmdfunc(meminfo, NAND_CMD_UNLOCK2, -1, page & this->pagemask); + page += (int)(length >> chip->page_shift); + chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, page & chip->pagemask); /* call wait ready function */ - status = this->waitfunc(meminfo, this, FL_WRITING); + status = chip->waitfunc(mtd, chip); /* see if device thinks it succeeded */ if (status & 0x01) { /* there was an error */ @@ -411,7 +418,7 @@ int nand_unlock(nand_info_t *meminfo, ulong start, ulong length) out: /* de-select the NAND device */ - this->select_chip(meminfo, -1); + chip->select_chip(mtd, -1); return ret; } #endif From c70564e6b1bd08f3230182392238907f3531a87e Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Tue, 2 Dec 2008 11:48:51 +0800 Subject: [PATCH 141/188] NAND: Fix cache and memory inconsistency issue We load the secondary stage u-boot image from NAND to system memory by nand_load, but we did not flush d-cache to memory, nor invalidate i-cache before we jump to RAM. When the system has cache enabled and the TLB/page attribute of system memory is cacheable, it will cause issues. - 83xx family is using the d-cache lock, so all of d-cache access is cache-inhibited. so you can't see the issue. - 85xx family is using d-cache, i-cache enable, partial cache lock. you will see the issue. This patch fixes the cache issue. Signed-off-by: Dave Liu Signed-off-by: Scott Wood --- nand_spl/board/freescale/mpc8313erdb/Makefile | 6 +++++- nand_spl/nand_boot_fsl_elbc.c | 5 +++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/nand_spl/board/freescale/mpc8313erdb/Makefile b/nand_spl/board/freescale/mpc8313erdb/Makefile index 3da1b1fff..1a8f6ff2c 100644 --- a/nand_spl/board/freescale/mpc8313erdb/Makefile +++ b/nand_spl/board/freescale/mpc8313erdb/Makefile @@ -34,7 +34,8 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o ticks.o -COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o time.o +COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \ + time.o cache.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -79,6 +80,9 @@ $(obj)ns16550.c: $(obj)nand_init.c: ln -sf $(SRCTREE)/cpu/mpc83xx/nand_init.c $(obj)nand_init.c +$(obj)cache.c: + ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c + $(obj)time.c: ln -sf $(SRCTREE)/lib_ppc/time.c $(obj)time.c diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c index 4a961ea7b..0d0c44e1e 100644 --- a/nand_spl/nand_boot_fsl_elbc.c +++ b/nand_spl/nand_boot_fsl_elbc.c @@ -143,6 +143,11 @@ void nand_boot(void) * Jump to U-Boot image */ puts("transfering control\n"); + /* + * Clean d-cache and invalidate i-cache, to + * make sure that no stale data is executed. + */ + flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE); uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; uboot(); } From 6c869637fef31e66380f0ea1d49690a2e26ec0d7 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Fri, 16 Jan 2009 18:55:54 +0100 Subject: [PATCH 142/188] NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and changes the default from 8 to 1 for the legacy and the new MTD NAND layer. This allows to remove all NAND_MAX_CHIPS definitions in the board config files because none of the boards use multi chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440 define #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE but that's bogus and did not work anyhow. Signed-off-by: Wolfgang Grandegger Signed-off-by: Scott Wood --- doc/README.nand | 2 +- drivers/mtd/nand/nand_base.c | 2 +- drivers/mtd/nand_legacy/nand_legacy.c | 2 +- include/configs/ASH405.h | 1 - include/configs/CATcenter.h | 1 - include/configs/CMS700.h | 1 - include/configs/DU440.h | 1 - include/configs/G2000.h | 1 - include/configs/HH405.h | 1 - include/configs/HUB405.h | 1 - include/configs/IDS8247.h | 1 - include/configs/M5329EVB.h | 1 - include/configs/M5373EVB.h | 1 - include/configs/MPC8313ERDB.h | 1 - include/configs/MPC8315ERDB.h | 1 - include/configs/MPC8360ERDK.h | 1 - include/configs/MPC837XEMDS.h | 1 - include/configs/MPC8536DS.h | 1 - include/configs/MPC8572DS.h | 1 - include/configs/NC650.h | 1 - include/configs/NETPHONE.h | 1 - include/configs/NETTA.h | 1 - include/configs/NETTA2.h | 1 - include/configs/NETVIA.h | 1 - include/configs/PLU405.h | 1 - include/configs/PMC440.h | 1 - include/configs/PPChameleonEVB.h | 2 -- include/configs/SXNI855T.h | 1 - include/configs/TQM8272.h | 1 - include/configs/TQM85xx.h | 1 - include/configs/VCMA9.h | 1 - include/configs/VOH405.h | 1 - include/configs/WUH405.h | 1 - include/configs/acadia.h | 1 - include/configs/afeb9260.h | 1 - include/configs/alpr.h | 1 - include/configs/at91cap9adk.h | 1 - include/configs/at91rm9200dk.h | 1 - include/configs/at91sam9260ek.h | 1 - include/configs/at91sam9261ek.h | 1 - include/configs/at91sam9263ek.h | 1 - include/configs/at91sam9rlek.h | 1 - include/configs/bamboo.h | 1 - include/configs/bf537-stamp.h | 1 - include/configs/canyonlands.h | 1 - include/configs/csb637.h | 1 - include/configs/davinci_dvevm.h | 1 - include/configs/davinci_schmoogie.h | 1 - include/configs/davinci_sffsdr.h | 1 - include/configs/davinci_sonata.h | 1 - include/configs/delta.h | 1 - include/configs/kilauea.h | 1 - include/configs/netstar.h | 1 - include/configs/omap2420h4.h | 1 - include/configs/pdnb3.h | 1 - include/configs/quad100hd.h | 1 - include/configs/sbc2410x.h | 1 - include/configs/sc3.h | 1 - include/configs/sequoia.h | 1 - include/configs/smdk6400.h | 1 - include/configs/socrates.h | 1 - include/configs/stxxtc.h | 1 - include/configs/zylonite.h | 1 - include/linux/mtd/bbm.h | 8 ++++---- include/linux/mtd/nand.h | 9 --------- include/linux/mtd/nand_legacy.h | 5 +++++ 66 files changed, 12 insertions(+), 77 deletions(-) diff --git a/doc/README.nand b/doc/README.nand index bf80bc0a5..fc62f92e0 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -172,7 +172,7 @@ More Definitions: #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 - #define NAND_MAX_CHIPS 1 + #define CONFIG_SYS_NAND_MAX_CHIPS 1 #define CONFIG_SYS_DAVINCI_BROKEN_ECC Versions of U-Boot <= 1.3.3 and Montavista Linux kernels diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 94a65d4e7..ef37f97b3 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2144,7 +2144,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, { int page, len, status, pages_per_block, ret, chipnr; struct nand_chip *chip = mtd->priv; - int rewrite_bbt[NAND_MAX_CHIPS]={0}; + int rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS]={0}; unsigned int bbt_masked_page = 0xffffffff; MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n", diff --git a/drivers/mtd/nand_legacy/nand_legacy.c b/drivers/mtd/nand_legacy/nand_legacy.c index 407e901a3..441780ac2 100644 --- a/drivers/mtd/nand_legacy/nand_legacy.c +++ b/drivers/mtd/nand_legacy/nand_legacy.c @@ -457,7 +457,7 @@ static void NanD_ScanChips(struct nand_chip *nand) { int floor, chip; int numchips[NAND_MAX_FLOORS]; - int maxchips = NAND_MAX_CHIPS; + int maxchips = CONFIG_SYS_NAND_MAX_CHIPS; int ret = 1; nand->numchips = 0; diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index a694083d5..a11a9b8db 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -150,7 +150,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25 diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index a44f3e16c..1e3666077 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -219,7 +219,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index d0e246409..eebce38e7 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -157,7 +157,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25 diff --git a/include/configs/DU440.h b/include/configs/DU440.h index 729153c2e..85c0e612b 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -411,7 +411,6 @@ int du440_phy_addr(int devnum); * NAND FLASH */ #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \ CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS} diff --git a/include/configs/G2000.h b/include/configs/G2000.h index d299044cb..b445faecb 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -205,7 +205,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 80e59bb26..e5de8ef01 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -209,7 +209,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25 diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index b3c7046fc..1106b0dcf 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -149,7 +149,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25 diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index a610ac9c2..fbcbddb40 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -275,7 +275,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define NAND_DISABLE_CE(nand) do \ { \ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index c207947ff..1f1586a21 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -215,7 +215,6 @@ # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE # define CONFIG_SYS_NAND_SIZE 1 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -# define NAND_MAX_CHIPS 1 # define NAND_ALLOW_ERASE_ALL 1 # define CONFIG_JFFS2_NAND 1 # define CONFIG_JFFS2_DEV "nand0" diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index a1bc32a6d..19916876d 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -215,7 +215,6 @@ # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE # define CONFIG_SYS_NAND_SIZE 1 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -# define NAND_MAX_CHIPS 1 # define NAND_ALLOW_ERASE_ALL 1 # define CONFIG_JFFS2_NAND 1 # define CONFIG_JFFS2_DEV "nand0" diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index fc3fa13c7..58a26e117 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -232,7 +232,6 @@ #endif #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 48043c493..e4ada652b 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -223,7 +223,6 @@ */ #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index a4f2862c4..c20f86aa2 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -211,7 +211,6 @@ #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_UPM 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index d49155fce..dbffb7121 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -271,7 +271,6 @@ #define CONFIG_CMD_NAND 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 532c3df77..505c48be2 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -248,7 +248,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); CONFIG_SYS_NAND_BASE + 0x80000, \ CONFIG_SYS_NAND_BASE + 0xC0000} #define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 6c7a36454..f84cc7e9c 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -267,7 +267,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); CONFIG_SYS_NAND_BASE + 0x80000,\ CONFIG_SYS_NAND_BASE + 0xC0000} #define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 diff --git a/include/configs/NC650.h b/include/configs/NC650.h index 423ca71c8..0b97f0ce6 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -250,7 +250,6 @@ * NAND flash support */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 /*----------------------------------------------------------------------- * SYPCR - System Protection Control 11-9 diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h index 34de94797..2d04d8925 100644 --- a/include/configs/NETPHONE.h +++ b/include/configs/NETPHONE.h @@ -514,7 +514,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 /* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */ #define NAND_DISABLE_CE(nand) \ diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index 004b3c8a4..34fdba59c 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -633,7 +633,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 /* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */ #define NAND_DISABLE_CE(nand) \ diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h index 70995faed..4a2702791 100644 --- a/include/configs/NETTA2.h +++ b/include/configs/NETTA2.h @@ -515,7 +515,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 /* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */ #define NAND_DISABLE_CE(nand) \ diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h index 87c920f42..f97bdcb72 100644 --- a/include/configs/NETVIA.h +++ b/include/configs/NETVIA.h @@ -411,7 +411,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define NAND_DISABLE_CE(nand) \ do { \ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 11ce0080f..e9f16461e 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -173,7 +173,6 @@ * NAND-FLASH stuff */ #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25 diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index f9f10021b..fc48bc1db 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -505,7 +505,6 @@ * NAND FLASH *----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ #define CONFIG_SYS_NAND_QUIET_TEST 1 diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 09a96417f..d4322b6ba 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -224,8 +224,6 @@ #define NAND_BIG_DELAY_US 25 #define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 - #define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h index 7fc455b8c..9857bf605 100644 --- a/include/configs/SXNI855T.h +++ b/include/configs/SXNI855T.h @@ -206,7 +206,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 /* DFBUSY is available on Port C, bit 12; 0 if busy */ #define NAND_WAIT_READY(nand) \ diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h index 1915a73a6..9cac696b9 100644 --- a/include/configs/TQM8272.h +++ b/include/configs/TQM8272.h @@ -424,7 +424,6 @@ #define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST) #define CONFIG_SYS_MAX_NAND_DEVICE 4 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \ CONFIG_SYS_NAND1_BASE, \ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 6d205a7a1..f5831ebaf 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -363,7 +363,6 @@ #define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST) #define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 #if (CONFIG_SYS_MAX_NAND_DEVICE == 1) #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE } diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 0bc2f6889..83d0d56c1 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -264,7 +264,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define NAND_WAIT_READY(nand) NF_WaitRB() diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 10ef620d8..f173bcc9b 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -159,7 +159,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25 diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index 01cdf3a6f..de6e12f51 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -147,7 +147,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25 diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 52ccdb5b9..9ffd86b1a 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -262,7 +262,6 @@ * NAND FLASH *----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index d63a1a07f..e996bbd32 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -97,7 +97,6 @@ #define DATAFLASH_TCHS (0x1 << 24) /* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 7ce820518..e6248e9df 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -335,7 +335,6 @@ * NAND-FLASH stuff *-----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE #define CONFIG_SYS_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \ CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 } diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index b2baf1b34..f1c5526d6 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -118,7 +118,6 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index c7e83ccfc..5a980d353 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -129,7 +129,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 15389296f..4501cae3c 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -100,7 +100,6 @@ #define DATAFLASH_TCHS (0x1 << 24) /* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 0016b4fbf..668fe3b08 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -111,7 +111,6 @@ #define DATAFLASH_TCHS (0x1 << 24) /* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index d9ebc87ae..c6603ff1f 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -123,7 +123,6 @@ #endif /* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 35fefc421..5bef1fe97 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -104,7 +104,6 @@ #define CONFIG_SYS_NO_FLASH 1 /* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index f3ffe1cca..8c4127da0 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -197,7 +197,6 @@ * NAND FLASH *----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 } #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 1b54d3b88..ac5aaa59a 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -278,7 +278,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define BFIN_NAND_READY PF3 #define NAND_WAIT_READY(nand) \ diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index faf630496..d814012c4 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -234,7 +234,6 @@ * NAND-FLASH related *----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ diff --git a/include/configs/csb637.h b/include/configs/csb637.h index 2df77cfa7..761c0dca3 100644 --- a/include/configs/csb637.h +++ b/include/configs/csb637.h @@ -131,7 +131,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 6885b2cbd..a727f5625 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -127,7 +127,6 @@ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ #define DEF_BOOTM "" #elif defined(CONFIG_SYS_USE_NOR) diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 8d7bcf57c..22d3808a3 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -89,7 +89,6 @@ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ /*=====================*/ /* Board related stuff */ diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index e9cd5a662..875bab6f7 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -85,7 +85,6 @@ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ /* I2C switch definitions for PCA9543 chip */ #define CONFIG_SYS_I2C_PCA9543_ADDR 0x70 diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 381eeb7a1..47ab27a87 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -122,7 +122,6 @@ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ #define DEF_BOOTM "" #elif defined(CONFIG_SYS_USE_NOR) diff --git a/include/configs/delta.h b/include/configs/delta.h index 08b28ca8a..fd97b746f 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -258,7 +258,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NO_FLASH 1 diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index b943f3153..4d3ccf568 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -214,7 +214,6 @@ * NAND FLASH *----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ diff --git a/include/configs/netstar.h b/include/configs/netstar.h index dda659784..fab22d16a 100644 --- a/include/configs/netstar.h +++ b/include/configs/netstar.h @@ -120,7 +120,6 @@ * NAND flash */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE 0x04000000 + (2 << 23) #define NAND_ALLOW_ERASE_ALL 1 diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index d11868e08..92df0b4fd 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -163,7 +163,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0) #define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0) diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index 8b7890e2c..f8aac1aba 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -264,7 +264,6 @@ * NAND-FLASH stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */ #endif diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h index 0f7fca38d..3ea854bec 100644 --- a/include/configs/quad100hd.h +++ b/include/configs/quad100hd.h @@ -224,7 +224,6 @@ #define CONFIG_SYS_NAND_CE 24 /* our CE is GPIO24 */ #define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */ #define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #endif diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h index d7a6ae46c..bf4a14e00 100644 --- a/include/configs/sbc2410x.h +++ b/include/configs/sbc2410x.h @@ -209,7 +209,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define NAND_WAIT_READY(nand) NF_WaitRB() #define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH) diff --git a/include/configs/sc3.h b/include/configs/sc3.h index d152a9670..515b09789 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -424,7 +424,6 @@ extern unsigned long offsetOfEnvironment; * NAND-FLASH stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE 0x77D00000 diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 9321bdc07..a3e2fcef4 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -373,7 +373,6 @@ * NAND FLASH */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index 1784cc622..57c82d1a1 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -227,7 +227,6 @@ /* NAND configuration */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x70200010 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_S3C_NAND_HWECC #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index cbf04e3f2..becd13eac 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -186,7 +186,6 @@ #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_CMD_NAND /* LIME GDC */ diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index bc078cf37..5a5f7728f 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -464,7 +464,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 /* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */ #define NAND_DISABLE_CE(nand) \ diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index 53397d807..f30eca1d2 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -227,7 +227,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NO_FLASH 1 diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h index abf8f1a7e..7db25465d 100644 --- a/include/linux/mtd/bbm.h +++ b/include/linux/mtd/bbm.h @@ -18,8 +18,8 @@ #define __LINUX_MTD_BBM_H /* The maximum number of NAND chips in an array */ -#ifndef NAND_MAX_CHIPS -#define NAND_MAX_CHIPS 8 +#ifndef CONFIG_SYS_NAND_MAX_CHIPS +#define CONFIG_SYS_NAND_MAX_CHIPS 1 #endif /** @@ -48,10 +48,10 @@ */ struct nand_bbt_descr { int options; - int pages[NAND_MAX_CHIPS]; + int pages[CONFIG_SYS_NAND_MAX_CHIPS]; int offs; int veroffs; - uint8_t version[NAND_MAX_CHIPS]; + uint8_t version[CONFIG_SYS_NAND_MAX_CHIPS]; int len; int maxblocks; int reserved_block_code; diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 24ad2bdaa..a4ad5711d 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -46,11 +46,6 @@ extern void nand_release (struct mtd_info *mtd); /* Internal helper for board drivers which need to override command function */ extern void nand_wait_ready(struct mtd_info *mtd); -/* The maximum number of NAND chips in an array */ -#ifndef NAND_MAX_CHIPS -#define NAND_MAX_CHIPS 8 -#endif - /* This constant declares the max. oobsize / page, which * is supported now. If you add a chip with bigger oobsize/page * adjust this accordingly. @@ -477,10 +472,6 @@ struct nand_manufacturers { extern struct nand_flash_dev nand_flash_ids[]; extern struct nand_manufacturers nand_manuf_ids[]; -#ifndef NAND_MAX_CHIPS -#define NAND_MAX_CHIPS 8 -#endif - extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); extern int nand_default_bbt(struct mtd_info *mtd); diff --git a/include/linux/mtd/nand_legacy.h b/include/linux/mtd/nand_legacy.h index 99eafbbcd..433444814 100644 --- a/include/linux/mtd/nand_legacy.h +++ b/include/linux/mtd/nand_legacy.h @@ -40,6 +40,11 @@ #error This module is for the legacy NAND support #endif +/* The maximum number of NAND chips in an array */ +#ifndef CONFIG_SYS_NAND_MAX_CHIPS +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#endif + /* * Standard NAND flash commands */ From 389e6620e2271096df3316917528003627db4021 Mon Sep 17 00:00:00 2001 From: Schlaegl Manfred jun Date: Tue, 20 Jan 2009 16:57:55 +0100 Subject: [PATCH 143/188] nand read.jffs2 (nand_legacy) in common/cmd_nand.c Error with CONFIG_NAND_LEGACY in common/cmd_nand.c: With current code "nand read.jffs2s" (read and skip bad blocks) is always interpreted as "nand read.jffs2" (read and fill bad blocks with 0xff). This is because ".jffs2" is tested before ".jffs2s" and only the first two characters are compared. Correction: Test for ".jffs2s" first and compare the first 7 characters. Signed-off-by: Scott Wood --- common/cmd_nand.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index a240c37b7..3d434e8a7 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -856,13 +856,12 @@ int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) (u_char *) addr); } return ret; - } else if (cmdtail && !strncmp (cmdtail, ".jffs2", 2)) - cmd |= NANDRW_JFFS2; /* skip bad blocks */ - else if (cmdtail && !strncmp (cmdtail, ".jffs2s", 2)) { + } else if (cmdtail && !strncmp (cmdtail, ".jffs2s", 7)) { cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ if (cmd & NANDRW_READ) cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ - } + } else if (cmdtail && !strncmp (cmdtail, ".jffs2", 2)) + cmd |= NANDRW_JFFS2; /* skip bad blocks */ #ifdef SXNI855T /* need ".e" same as ".j" for compatibility with older units */ else if (cmdtail && !strcmp (cmdtail, ".e")) From d4bade8d77aa20e2846fa4accff0e7fa7961a134 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sun, 18 Jan 2009 19:46:06 -0500 Subject: [PATCH 144/188] nand: fixup printf modifiers to match types used Signed-off-by: Mike Frysinger Signed-off-by: Scott Wood --- common/cmd_nand.c | 4 ++-- drivers/mtd/nand/nand_util.c | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 3d434e8a7..aedf8a624 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -160,7 +160,7 @@ out: if (*size == nand->size) puts("whole chip\n"); else - printf("offset 0x%lx, size 0x%x\n", *off, *size); + printf("offset 0x%lx, size 0x%zx\n", *off, *size); return 0; } @@ -398,7 +398,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 1; } - printf(" %d bytes %s: %s\n", size, + printf(" %zu bytes %s: %s\n", size, read ? "read" : "written", ret ? "ERROR" : "OK"); return ret == 0 ? 0 : 1; diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index 77da53e26..6ba52b30c 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -495,7 +495,7 @@ int nand_write_skip_bad(nand_info_t *nand, size_t offset, size_t *length, if (len_incl_bad == *length) { rval = nand_write (nand, offset, length, buffer); if (rval != 0) - printf ("NAND write to offset %x failed %d\n", + printf ("NAND write to offset %zx failed %d\n", offset, rval); return rval; @@ -506,7 +506,7 @@ int nand_write_skip_bad(nand_info_t *nand, size_t offset, size_t *length, size_t write_size; if (nand_block_isbad (nand, offset & ~(nand->erasesize - 1))) { - printf ("Skip bad block 0x%08x\n", + printf ("Skip bad block 0x%08zx\n", offset & ~(nand->erasesize - 1)); offset += nand->erasesize - block_offset; continue; @@ -519,7 +519,7 @@ int nand_write_skip_bad(nand_info_t *nand, size_t offset, size_t *length, rval = nand_write (nand, offset, &write_size, p_buffer); if (rval != 0) { - printf ("NAND write to offset %x failed %d\n", + printf ("NAND write to offset %zx failed %d\n", offset, rval); *length -= left_to_write; return rval; @@ -565,7 +565,7 @@ int nand_read_skip_bad(nand_info_t *nand, size_t offset, size_t *length, if (len_incl_bad == *length) { rval = nand_read (nand, offset, length, buffer); if (rval != 0) - printf ("NAND read from offset %x failed %d\n", + printf ("NAND read from offset %zx failed %d\n", offset, rval); return rval; @@ -576,7 +576,7 @@ int nand_read_skip_bad(nand_info_t *nand, size_t offset, size_t *length, size_t read_length; if (nand_block_isbad (nand, offset & ~(nand->erasesize - 1))) { - printf ("Skipping bad block 0x%08x\n", + printf ("Skipping bad block 0x%08zx\n", offset & ~(nand->erasesize - 1)); offset += nand->erasesize - block_offset; continue; @@ -589,7 +589,7 @@ int nand_read_skip_bad(nand_info_t *nand, size_t offset, size_t *length, rval = nand_read (nand, offset, &read_length, p_buffer); if (rval != 0) { - printf ("NAND read from offset %x failed %d\n", + printf ("NAND read from offset %zx failed %d\n", offset, rval); *length -= left_to_read; return rval; From 5bb907a4925397789c90d074f4f7e92ce6b39402 Mon Sep 17 00:00:00 2001 From: Ron Madrid Date: Thu, 22 Jan 2009 15:05:24 -0800 Subject: [PATCH 145/188] mpc83xx: New board support for SIMPC8313 This patch will create a new board, SIMPC8313, from Sheldon Instruments. This board boots from NAND devices and is configureable for either large or small page devices. The board supports non-soldered DDR2, one ethernet port, a Marvell 88E1118 PHY, and PCI host support. The board also has a FPGA connected to the eLBC providing glue logic to a TMS320C67xx DSP. Signed-off-by: Ron Madrid Signed-off-by: Kim Phillips --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 15 + board/sheldon/simpc8313/Makefile | 50 ++ board/sheldon/simpc8313/config.mk | 13 + board/sheldon/simpc8313/sdram.c | 193 +++++++ board/sheldon/simpc8313/simpc8313.c | 134 +++++ doc/README.simpc8313 | 80 +++ include/configs/SIMPC8313.h | 544 ++++++++++++++++++++ nand_spl/board/sheldon/simpc8313/Makefile | 100 ++++ nand_spl/board/sheldon/simpc8313/u-boot.lds | 52 ++ 11 files changed, 1186 insertions(+) create mode 100644 board/sheldon/simpc8313/Makefile create mode 100644 board/sheldon/simpc8313/config.mk create mode 100644 board/sheldon/simpc8313/sdram.c create mode 100644 board/sheldon/simpc8313/simpc8313.c create mode 100644 doc/README.simpc8313 create mode 100644 include/configs/SIMPC8313.h create mode 100644 nand_spl/board/sheldon/simpc8313/Makefile create mode 100644 nand_spl/board/sheldon/simpc8313/u-boot.lds diff --git a/MAINTAINERS b/MAINTAINERS index d07fe8612..b774938dc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -263,6 +263,10 @@ Jon Loeliger MPC8641HPCN MPC8641D +Ron Madrid + + SIMPC8313 MPC8313 + Dan Malek stxgp3 MPC85xx diff --git a/MAKEALL b/MAKEALL index 3e8c56b4f..1ca5e58de 100755 --- a/MAKEALL +++ b/MAKEALL @@ -353,6 +353,7 @@ LIST_83xx=" \ MPC837XERDB \ MVBLM7 \ sbc8349 \ + SIMPC8313_LP \ TQM834x \ " diff --git a/Makefile b/Makefile index 294efef94..9f6927815 100644 --- a/Makefile +++ b/Makefile @@ -2328,6 +2328,21 @@ MVBLM7_config: unconfig sbc8349_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349 +SIMPC8313_LP_config \ +SIMPC8313_SP_config: unconfig + @mkdir -p $(obj)include + @mkdir -p $(obj)board/sheldon/simpc8313 + @if [ "$(findstring _LP_,$@)" ] ; then \ + $(XECHO) -n "...Large Page NAND..." ; \ + echo "#define CONFIG_NAND_LP" >> $(obj)include/config.h ; \ + fi ; \ + if [ "$(findstring _SP_,$@)" ] ; then \ + $(XECHO) -n "...Small Page NAND..." ; \ + echo "#define CONFIG_NAND_SP" >> $(obj)include/config.h ; \ + fi ; + @$(MKCONFIG) -a SIMPC8313 ppc mpc83xx simpc8313 sheldon + @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk + TQM834x_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc diff --git a/board/sheldon/simpc8313/Makefile b/board/sheldon/simpc8313/Makefile new file mode 100644 index 000000000..7c34c5e16 --- /dev/null +++ b/board/sheldon/simpc8313/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o sdram.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/sheldon/simpc8313/config.mk b/board/sheldon/simpc8313/config.mk new file mode 100644 index 000000000..ce1c0d8d9 --- /dev/null +++ b/board/sheldon/simpc8313/config.mk @@ -0,0 +1,13 @@ +ifndef NAND_SPL +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp +endif + +ifndef TEXT_BASE +TEXT_BASE = 0x00100000 +endif + +ifdef CONFIG_NAND_LP +PAD_TO = 0xFFF20000 +else +PAD_TO = 0xFFF04000 +endif diff --git a/board/sheldon/simpc8313/sdram.c b/board/sheldon/simpc8313/sdram.c new file mode 100644 index 000000000..ebb70a232 --- /dev/null +++ b/board/sheldon/simpc8313/sdram.c @@ -0,0 +1,193 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 + * Copyright (C) Sheldon Instruments, Inc. 2008 + * + * Author: Ron Madrid + * + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static long fixed_sdram(void); + +#if defined(CONFIG_NAND_SPL) +void si_wait_i2c(void) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + + while (!(__raw_readb(&im->i2c[0].sr) & 0x02)) + ; + + __raw_writeb(0x00, &im->i2c[0].sr); + + sync(); + + return; +} + +void si_read_i2c(u32 lbyte, int count, u8 *buffer) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 i; + u8 chip = 0x50 << 1; /* boot sequencer I2C */ + u32 ubyte = (lbyte & 0xff00) >> 8; + + lbyte &= 0xff; + + /* + * Set up controller + */ + __raw_writeb(0x3f, &im->i2c[0].fdr); + __raw_writeb(0x00, &im->i2c[0].adr); + __raw_writeb(0x00, &im->i2c[0].sr); + __raw_writeb(0x00, &im->i2c[0].dr); + + while (__raw_readb(&im->i2c[0].sr) & 0x20) + ; + + /* + * Writing address to device + */ + __raw_writeb(0xb0, &im->i2c[0].cr); + sync(); + __raw_writeb(chip, &im->i2c[0].dr); + si_wait_i2c(); + + __raw_writeb(0xb0, &im->i2c[0].cr); + sync(); + __raw_writeb(ubyte, &im->i2c[0].dr); + si_wait_i2c(); + + __raw_writeb(lbyte, &im->i2c[0].dr); + si_wait_i2c(); + + __raw_writeb(0xb4, &im->i2c[0].cr); + sync(); + __raw_writeb(chip + 1, &im->i2c[0].dr); + si_wait_i2c(); + + __raw_writeb(0xa0, &im->i2c[0].cr); + sync(); + + /* + * Dummy read + */ + __raw_readb(&im->i2c[0].dr); + + si_wait_i2c(); + + /* + * Read actual data + */ + for (i = 0; i < count; i++) + { + if (i == (count - 2)) /* Reached next to last byte, No ACK */ + __raw_writeb(0xa8, &im->i2c[0].cr); + if (i == (count - 1)) /* Reached last byte, STOP */ + __raw_writeb(0x88, &im->i2c[0].cr); + + /* Read byte of data */ + buffer[i] = __raw_readb(&im->i2c[0].dr); + + if (i == (count - 1)) + break; + si_wait_i2c(); + } + + return; +} +#endif /* CONFIG_NAND_SPL */ + +phys_size_t initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + volatile fsl_lbus_t *lbc= &im->lbus; + u32 msize; + + if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + __raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar); + + msize = fixed_sdram(); + + /* Local Bus setup lbcr and mrtpr */ + __raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr); + __raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr); + sync(); + + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + +/************************************************************************* + * fixed sdram init -- reads values from boot sequencer I2C + ************************************************************************/ +static long fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msizelog2, msize = 1; +#if defined(CONFIG_NAND_SPL) + u32 i; + const u8 bytecount = 135; + u8 buffer[bytecount]; + u32 addr, data; + + si_read_i2c(0, bytecount, buffer); + + for (i = 18; i < bytecount; i += 7){ + addr = (u32)buffer[i]; + addr <<= 8; + addr |= (u32)buffer[i + 1]; + addr <<= 2; + data = (u32)buffer[i + 2]; + data <<= 8; + data |= (u32)buffer[i + 3]; + data <<= 8; + data |= (u32)buffer[i + 4]; + data <<= 8; + data |= (u32)buffer[i + 5]; + + __raw_writel(data, (u32 *)(CONFIG_SYS_IMMR + addr)); + } + + sync(); + + /* enable DDR controller */ + __raw_writel((__raw_readl(&im->ddr.sdram_cfg) | SDRAM_CFG_MEM_EN), &im->ddr.sdram_cfg); +#endif /* (CONFIG_NAND_SPL) */ + + msizelog2 = ((__raw_readl(&im->sysconf.ddrlaw[0].ar) & LAWAR_SIZE) + 1); + msize <<= (msizelog2 - 20); + + return msize; +} diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c new file mode 100644 index 000000000..25e5c2409 --- /dev/null +++ b/board/sheldon/simpc8313/simpc8313.c @@ -0,0 +1,134 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006-2007 + * Copyright (C) Sheldon Instruments, Inc. 2008 + * + * Author: Ron Madrid + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: Sheldon Instruments SIMPC8313\n"); + return 0; +} + +#ifndef CONFIG_NAND_SPL +static struct pci_region pci_regions[] = { + { + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci_regions }; + int warmboot; + + /* Enable all 3 PCI_CLK_OUTPUTs. */ + clk->occr |= 0xe0000000; + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; + + mpc83xx_pci_init(1, reg, warmboot); +} + +/* + * Miscellaneous late-boot configurations + */ +int misc_init_r(void) +{ + int rc = 0; + + return rc; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif +#else /* CONFIG_NAND_SPL */ +void board_init_f(ulong bootflag) +{ + NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), + CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + puts("NAND boot... "); + init_timebase(); + initdram(0); + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (gd->flags & GD_FLG_SILENT) + return; + + if (c == '\n') + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); + + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c); +} +#endif diff --git a/doc/README.simpc8313 b/doc/README.simpc8313 new file mode 100644 index 000000000..b362c6aee --- /dev/null +++ b/doc/README.simpc8313 @@ -0,0 +1,80 @@ +Sheldon Instruments SIMPC8313 Board +----------------------------------------- + +1. Board Switches and Jumpers + + S2 is used to set CFG_RESET_SOURCE. + + To boot the image in Large page NAND flash, use these DIP + switch settings for S2: + + +----------+ ON + | * * **** | + | * * | + +----------+ + 12345678 + + To boot the image in Small page NAND flash, use these DIP + switch settings for S2: + + +----------+ ON + | *** **** | + | * | + +----------+ + 12345678 + (where the '*' indicates the position of the tab of the switch.) + +2. Memory Map + The memory map looks like this: + + 0x0000_0000 0x1fff_ffff DDR 512M + 0x8000_0000 0x8fff_ffff PCI MEM 256M + 0x9000_0000 0x9fff_ffff PCI_MMIO 256M + 0xe000_0000 0xe00f_ffff IMMR 1M + 0xe200_0000 0xe20f_ffff PCI IO 16M + 0xe280_0000 0xe280_7fff NAND FLASH (CS0) 32K + or + 0xe280_0000 0xe281_ffff NAND FLASH (CS0) 128K + 0xff00_0000 0xff00_7fff FPGA (CS1) 1M + +3. Compilation + + Assuming you're using BASH (or similar) as your shell: + + export CROSS_COMPILE=your-cross-compiler-prefix- + make distclean + make SIMPC8313_LP_config + (or make SIMPC8313_SP_config, depending on the page size + of your NAND flash) + make + +4. Downloading and Flashing Images + +4.1 Reflash U-boot Image using U-boot + + =>run update_uboot + + You may want to try + =>tftp $loadaddr $uboot + first, to make sure that the TFTP load will succeed before it + goes ahead and wipes out your current firmware. And of course, + if the new u-boot doesn't boot, you can plug the board into + your PCI slot and with the supplied driver and sample app + you can reburn a working u-boot. + +4.2 Downloading and Booting Linux Kernel + + Ensure that all networking-related environment variables are set + properly (including ipaddr, serverip, gatewayip (if needed), + netmask, ethaddr, eth1addr, fdtfile, and bootfile). + + =>tftp $loadaddr uImage + =>nand write $loadaddr kernel $filesize + =>tftp $loadaddr $fdtfile + =>nand write $loadaddr 7e0000 1800 + + =>boot + +5 Notes + + The console baudrate for SIMPC8313 is 115200bps. diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h new file mode 100644 index 000000000..a616236b7 --- /dev/null +++ b/include/configs/SIMPC8313.h @@ -0,0 +1,544 @@ +/* + * Copyright (C) Sheldon Instruments, Inc. 2008 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * simpc8313 board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_NAND_U_BOOT + +#define CONFIG_E300 1 +#define CONFIG_MPC83XX 1 +#define CONFIG_MPC831X 1 +#define CONFIG_MPC8313 1 + +#define CONFIG_PCI +#define CONFIG_83XX_GENERIC_PCI + +#define CONFIG_MISC_INIT_R + +/* + * On-board devices + * + * TSEC1 is Marvell PHY 88E1118 + */ + +#define CONFIG_SYS_33MHZ + +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ + +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +#define CONFIG_SYS_IMMR 0xE0000000 + +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR +#endif + +#define CONFIG_SYS_MEMTEST_START 0x00001000 +#define CONFIG_SYS_MEMTEST_END 0x07f00000 + +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ + +/* + * Device configurations + */ +#define CONFIG_TSEC1 + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE + +#define CONFIG_VERY_BIG_RAM +#define CONFIG_MAX_MEM_MAPPED (512 << 20) + +#define CONFIG_SYS_DDRCDR ( DDRCDR_EN \ + | DDRCDR_PZ_NOMZ \ + | DDRCDR_NZ_NOMZ \ + | DDRCDR_M_ODR ) + /* 0x73000002 TODO ODR & DRN ? */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + */ +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ + | (0xFF << LBCR_BMT_SHIFT) \ + | 0xF ) /* 0x0004ff0f */ + +#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ + +/* drivers/mtd/nand/nand.c */ +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_NAND_BASE 0xFFF00000 +#else +#define CONFIG_SYS_NAND_BASE 0xE2800000 +#endif + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 + +#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ + | (2< " + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +/* + * TSEC + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ + +#define CONFIG_NET_MULTI +#define CONFIG_GMII /* MII PHY management */ + +#ifdef CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 0x0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC1_PHYIDX 0 +#endif + +#ifdef CONFIG_TSEC2 +#define CONFIG_HAS_ETH1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define TSEC2_PHY_ADDR 4 +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC2_PHYIDX 0 +#endif + + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC1" + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * Environment + */ +#if defined(CONFIG_NAND_U_BOOT) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET (768 * 1024) + #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) + #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) +#elif !defined(CONFIG_SYS_RAMBOOT) + #define CONFIG_ENV_IS_IN_FLASH 1 + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ + #define CONFIG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#else + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_FLASH + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PCI +#define CONFIG_CMD_JFFS2 + +#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS +#endif + +#define CONFIG_CMDLINE_EDITING 1 + + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_PBSIZE ( CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) \ + + 16 ) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#define CONFIG_SYS_HRCW_LOW ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \ + | 0x20000000 /* reserved */ \ + | HRCWL_DDR_TO_SCB_CLK_2X1 \ + | HRCWL_CSB_TO_CLKIN_4X1 \ + | HRCWL_CORE_TO_CSB_2_5X1 ) + +#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4) + +#define CONFIG_SYS_HRCW_HIGH_BASE ( HRCWH_PCI_HOST \ + | HRCWH_PCI1_ARBITER_ENABLE \ + | HRCWH_CORE_ENABLE \ + | HRCWH_BOOTSEQ_DISABLE \ + | HRCWH_SW_WATCHDOG_DISABLE \ + | HRCWH_TSEC1M_IN_RGMII \ + | HRCWH_TSEC2M_IN_RGMII \ + | HRCWH_BIG_ENDIAN \ + | HRCWH_LALE_NORMAL ) + +#ifdef CONFIG_NAND_LP +#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \ + | HRCWH_FROM_0XFFF00100 \ + | HRCWH_ROM_LOC_NAND_LP_8BIT \ + | HRCWH_RL_EXT_NAND) +#else +#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \ + | HRCWH_FROM_0XFFF00100 \ + | HRCWH_ROM_LOC_NAND_SP_8BIT \ + | HRCWH_RL_EXT_NAND ) +#endif + +/* System IO Config */ +#define CONFIG_SYS_SICRH ( SICRH_ETSEC2_B \ + | SICRH_ETSEC2_C \ + | SICRH_ETSEC2_D \ + | SICRH_ETSEC2_E \ + | SICRH_ETSEC2_F \ + | SICRH_ETSEC2_G \ + | SICRH_TSOBI1 \ + | SICRH_TSOBI2 ) +#define CONFIG_SYS_SICRL (SICRL_USBDR \ + | SICRL_ETSEC2_A ) + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ + | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT ) + +#define CONFIG_SYS_HID2 HID2_HBE + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR @ 0x00000000 */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10) +#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI @ 0x80000000 */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI2 not supported on 8313 */ +#define CONFIG_SYS_IBAT4L (0) +#define CONFIG_SYS_IBAT4U (0) + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10) +#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) + +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U +#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_NETDEV eth1 + +#define CONFIG_HOSTNAME simpc8313 +#define CONFIG_ROOTPATH /tftpboot/ +#define CONFIG_BOOTFILE /tftpboot/uImage +#define CONFIG_UBOOTPATH u-boot-nand.bin /* U-Boot image on TFTP server */ +#define CONFIG_FDTFILE simpc8313.dtb + +#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY 5 /* 5 second delay */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr" + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "ethprime=TSEC1\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "fdtaddr=ae0000\0" \ + "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ + "console=ttyS0\0" \ + "setbootargs=setenv bootargs " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "load_uboot=tftp 100000 u-boot-nand.bin\0" \ + "burn_uboot=nand erase u-boot 80000; " \ + "nand write 100000 u-boot $filesize\0" \ + "update_uboot=run load_uboot;run burn_uboot\0" \ + "mtdids=nand0=nand0\0" \ + "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \ + "console=ttyS0,115200\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setbootargs;" \ + "run setipargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv rootdev /dev/ram;" \ + "run setbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#undef MK_STR +#undef XMK_STR + +#endif /* __CONFIG_H */ diff --git a/nand_spl/board/sheldon/simpc8313/Makefile b/nand_spl/board/sheldon/simpc8313/Makefile new file mode 100644 index 000000000..b0967a30b --- /dev/null +++ b/nand_spl/board/sheldon/simpc8313/Makefile @@ -0,0 +1,100 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# (C) Copyright 2008 Freescale Semiconductor +# (C) Copyright Sheldon Instruments, Inc. 2008 +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +NAND_SPL := y +TEXT_BASE := 0xfff00000 + +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o ticks.o +COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o time.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +$(obj)start.S: + ln -sf $(SRCTREE)/cpu/mpc83xx/start.S $< + +$(obj)nand_boot_fsl_elbc.c: + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $< + +$(obj)sdram.c: + ln -sf $(SRCTREE)/board/$(BOARDDIR)/sdram.c $< + +$(obj)$(BOARD).c: + ln -sf $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $< + +$(obj)ns16550.c: + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $< + +$(obj)nand_init.c: + ln -sf $(SRCTREE)/cpu/mpc83xx/nand_init.c $< + +$(obj)time.c: + ln -sf $(SRCTREE)/lib_ppc/time.c $< + +$(obj)ticks.S: + ln -sf $(SRCTREE)/lib_ppc/ticks.S $< + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/sheldon/simpc8313/u-boot.lds b/nand_spl/board/sheldon/simpc8313/u-boot.lds new file mode 100644 index 000000000..40c414549 --- /dev/null +++ b/nand_spl/board/sheldon/simpc8313/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + . = 0xfff00000; + .text : { + *(.text*) + . = ALIGN(16); + *(.rodata*) + *(.eh_frame) + } + + . = ALIGN(8); + .data : { + *(.data*) + *(.sdata*) + _GOT2_TABLE_ = .; + *(.got2) + __got2_entries = (. - _GOT2_TABLE_) >> 2; + } + + . = ALIGN(8); + __bss_start = .; + .bss (NOLOAD) : { *(.*bss) } + _end = .; +} +ENTRY(_start) +ASSERT(_end <= 0xfff01000, "NAND bootstrap too big"); From 6dadc9195ad642cc662632f4d92f92d3d71e8bf2 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 20 Oct 2008 16:15:04 -0400 Subject: [PATCH 146/188] Blackfin: use common strmhz() in system output Signed-off-by: Mike Frysinger --- common/cmd_bdinfo.c | 10 ++++++---- lib_blackfin/board.c | 6 ++++-- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 667524188..b660d2ab9 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -328,18 +328,20 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } #elif defined(CONFIG_BLACKFIN) +static void print_str(const char *, const char *); int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int i; bd_t *bd = gd->bd; + char buf[32]; printf("U-Boot = %s\n", bd->bi_r_version); printf("CPU = %s\n", bd->bi_cpu); printf("Board = %s\n", bd->bi_board_name); - printf("VCO = %lu MHz\n", bd->bi_vco / 1000000); - printf("CCLK = %lu MHz\n", bd->bi_cclk / 1000000); - printf("SCLK = %lu MHz\n", bd->bi_sclk / 1000000); + print_str("VCO", strmhz(buf, bd->bi_vco)); + print_str("CCLK", strmhz(buf, bd->bi_cclk)); + print_str("SCLK", strmhz(buf, bd->bi_sclk)); print_num("boot_params", (ulong)bd->bi_boot_params); print_num("memstart", (ulong)bd->bi_memstart); @@ -430,7 +432,7 @@ static void print_lnum(const char *name, u64 value) } #endif -#if defined(CONFIG_PPC) || defined(CONFIG_M68K) +#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_BLACKFIN) static void print_str(const char *name, const char *str) { printf ("%-12s= %6s MHz\n", name, str); diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index 05e66e3c5..ddf814428 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -257,6 +257,7 @@ void board_init_f(ulong bootflag) { ulong addr; bd_t *bd; + char buf[32]; #ifdef CONFIG_BOARD_EARLY_INIT_F serial_early_puts("Board early init flash\n"); @@ -315,8 +316,9 @@ void board_init_f(ulong bootflag) checkboard(); timer_init(); - printf("Clock: VCO: %lu MHz, Core: %lu MHz, System: %lu MHz\n", - get_vco() / 1000000, get_cclk() / 1000000, get_sclk() / 1000000); + printf("Clock: VCO: %s MHz, ", strmhz(buf, get_vco())); + printf("Core: %s MHz, ", strmhz(buf, get_cclk())); + printf("System: %s MHz\n", strmhz(buf, get_sclk())); printf("RAM: "); print_size(initdram(0), "\n"); From 30837e5b21d5a742983581ab9ee3fac085311d19 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 11 Nov 2008 08:52:09 -0500 Subject: [PATCH 147/188] Add README file for MPC8572DS board Signed-off-by: Haiying Wang Acked-by: Andy Fleming --- doc/README.mpc8572ds | 167 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 167 insertions(+) create mode 100644 doc/README.mpc8572ds diff --git a/doc/README.mpc8572ds b/doc/README.mpc8572ds new file mode 100644 index 000000000..f9ffde445 --- /dev/null +++ b/doc/README.mpc8572ds @@ -0,0 +1,167 @@ +Overview +-------- +MPC8572DS is a high-performance computing, evaluation and development platform +supporting the mpc8572 PowerTM processor. + +Building U-boot +----------- + make MPC8572DS_config + make + +Flash Banks +----------- +MPC8572DS board has two flash banks. They are both present on boot, but their +locations can be swapped using the dip-switch SW9[1:2]. + +Booting is always from the boot bank at 0xec00_0000. + + +Memory Map +---------- + +0xe800_0000 - 0xebff_ffff Alernate bank 64MB +0xec00_0000 - 0xefff_ffff Boot bank 64MB + +0xebf8_0000 - 0xebff_ffff Alternate u-boot address 512KB +0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB + + +Flashing Images +--------------- + +To place a new u-boot image in the alternate flash bank and then reset with that + new image temporarily, use this: + + tftp 1000000 u-boot.bin + erase ebf80000 ebffffff + cp.b 1000000 ebf80000 80000 + pixis_reset altbank + + +To program the image in the boot flash bank: + + tftp 1000000 u-boot.bin + protect off all + erase eff80000 ffffffff + cp.b 1000000 eff80000 80000 + + +The pixis_reset command +----------------------- +The command - "pixis_reset", is introduced to reset mpc8572ds board +using the FPGA sequencer. When the board restarts, it has the option +of using either the current or alternate flash bank as the boot +image, with or without the watchdog timer enabled, and finally with +or without frequency changes. + +Usage is; + + pixis_reset + pixis_reset altbank + pixis_reset altbank wd + pixis_reset altbank cf + pixis_reset cf + +Examples: + + /* reset to current bank, like "reset" command */ + pixis_reset + + /* reset board but use the to alternate flash bank */ + pixis_reset altbank + + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb mpc8572ds.dts > mpc8572ds.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/mpc8572ds.dts + + +Booting Linux +------------- + +Place a linux uImage in the TFTP disk area. + + tftp 1000000 uImage.8572 + tftp c00000 mpc8572ds.dtb + bootm 1000000 - c00000 + + +Implementing AMP(Asymmetric MultiProcessing) +------------- +1. Build kernel image for core0: + + a. $ make 85xx/mpc8572_ds_defconfig + + b. $ make menuconfig + - un-select "Processor support"->"Symetric multi-processing support" + + c. $ make uImage + + d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0 + +2. Build kernel image for core1: + + a. $ make 85xx/mpc8572_ds_defconfig + + b. $ make menuconfig + - Un-select "Processor support"->"Symetric multi-processing support" + - Select "Advanced setup" -> " Prompt for advanced kernel + configuration options" + - Select "Set physical address where the kernel is loaded" and + set it to 0x20000000, asssuming core1 will start from 512MB. + - Select "Set custom page offset address" + - Select "Set custom kernel base address" + - Select "Set maximum low memory" + - "Exit" and save the selection. + + c. $ make uImage + + d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1 + +3. Create dtb for core0: + + $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb + +4. Create dtb for core1: + + $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb + +5. Bring up two cores separately: + + a. Power on the board, under u-boot prompt: + => setenv + => setenv + => setenv bootargs root=/dev/ram rw console=ttyS0,115200 + b. Bring up core1's kernel first: + => setenv bootm_low 0x20000000 + => setenv bootm_size 0x10000000 + => tftp 21000000 8572/uImage.core1 + => tftp 22000000 8572/ramdiskfile + => tftp 20c00000 8572/mpc8572ds_core1.dtb + => interrupts off + => bootm start 21000000 22000000 20c00000 + => bootm loados + => bootm ramdisk + => bootm fdt + => fdt boardsetup + => fdt chosen $initrd_start $initrd_end + => bootm prep + => cpu 1 release $bootm_low - $fdtaddr - + c. Bring up core0's kernel(on the same u-boot console): + => setenv bootm_low 0 + => setenv bootm_size 0x20000000 + => tftp 1000000 8572/uImage.core0 + => tftp 2000000 8572/ramdiskfile + => tftp c00000 8572/mpc8572ds_core0.dtb + => bootm 1000000 2000000 c00000 + +Please note only core0 will run u-boot, core1 starts kernel directly after +"cpu release" command is issued. + From 52b565f5ad23b682489055b187767d8bf1c2e444 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 2 Dec 2008 14:19:33 -0600 Subject: [PATCH 148/188] 85xx: separate PIXIS virtual from physical address Added a PIXIS_BASE_PHYS for use as the physical address and maintain PIXIS_BASE as the virtual address of the PIXIS fpga registers. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala Acked-by: Andy Fleming --- board/freescale/mpc8536ds/law.c | 2 +- board/freescale/mpc8536ds/tlb.c | 2 +- board/freescale/mpc8572ds/law.c | 2 +- board/freescale/mpc8572ds/tlb.c | 2 +- include/configs/MPC8536DS.h | 3 ++- include/configs/MPC8572DS.h | 3 ++- 6 files changed, 8 insertions(+), 6 deletions(-) diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c index 0861fa708..caccce425 100644 --- a/board/freescale/mpc8536ds/law.c +++ b/board/freescale/mpc8536ds/law.c @@ -37,7 +37,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), - SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC), + SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c index c81a95922..89d5097be 100644 --- a/board/freescale/mpc8536ds/tlb.c +++ b/board/freescale/mpc8536ds/tlb.c @@ -41,7 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE, + SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 0), diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c index 83eb6811c..9814479f6 100644 --- a/board/freescale/mpc8572ds/law.c +++ b/board/freescale/mpc8572ds/law.c @@ -35,7 +35,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), - SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC), + SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index 829896ac0..d54085933 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -82,7 +82,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE, + SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_4K, 1), }; diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 505c48be2..3ea1b4816 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -194,8 +194,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#define PIXIS_BASE_PHYS PIXIS_BASE -#define CONFIG_SYS_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */ +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index f84cc7e9c..6e42b289d 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -197,8 +197,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#define PIXIS_BASE_PHYS PIXIS_BASE -#define CONFIG_SYS_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */ +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ From c953ddfd56b3ae3f28910fe3aed6de6968d1c9aa Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 2 Dec 2008 14:19:34 -0600 Subject: [PATCH 149/188] 85xx: separate FLASH BASE virtual from physical address Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala Acked-by: Andy Fleming --- board/freescale/mpc8536ds/law.c | 2 +- board/freescale/mpc8536ds/mpc8536ds.c | 2 +- board/freescale/mpc8536ds/tlb.c | 2 +- board/freescale/mpc8572ds/law.c | 2 +- board/freescale/mpc8572ds/mpc8572ds.c | 2 +- board/freescale/mpc8572ds/tlb.c | 2 +- include/configs/MPC8536DS.h | 9 +++++---- include/configs/MPC8572DS.h | 9 +++++---- 8 files changed, 16 insertions(+), 14 deletions(-) diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c index caccce425..31614d238 100644 --- a/board/freescale/mpc8536ds/law.c +++ b/board/freescale/mpc8536ds/law.c @@ -30,7 +30,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_2), diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 2b17612b3..e369d090c 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -433,7 +433,7 @@ int board_early_init_r(void) /* invalidate existing TLB entry for flash + promjet */ disable_tlb(flash_esel); - set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */ + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c index 89d5097be..f4bab550c 100644 --- a/board/freescale/mpc8536ds/tlb.c +++ b/board/freescale/mpc8536ds/tlb.c @@ -53,7 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* W**G* - Flash/promjet, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c index 9814479f6..02ea0ec59 100644 --- a/board/freescale/mpc8572ds/law.c +++ b/board/freescale/mpc8572ds/law.c @@ -28,7 +28,7 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index c2487e5b8..88ab06d78 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -358,7 +358,7 @@ int board_early_init_r(void) /* invalidate existing TLB entry for flash + promjet */ disable_tlb(flash_esel); - set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */ + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index d54085933..6cb3eb1d9 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* W**G* - Flash/promjet, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 3ea1b4816..fb9fc2e02 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -166,12 +166,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Local Bus Definitions */ #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BR0_PRELIM 0xe8001001 -#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 +#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 -#define CONFIG_SYS_BR1_PRELIM 0xe0001001 -#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE} #define CONFIG_SYS_FLASH_QUIET_TEST diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 6e42b289d..6b56a0e08 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -169,12 +169,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Local Bus Definitions */ #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BR0_PRELIM 0xe8001001 -#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 +#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 -#define CONFIG_SYS_BR1_PRELIM 0xe0001001 -#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE} #define CONFIG_SYS_FLASH_QUIET_TEST From 10795f42cb94e71bcb262b615084f69dd886399a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 2 Dec 2008 16:08:36 -0600 Subject: [PATCH 150/188] 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boards Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala Acked-by: Andy Fleming --- board/freescale/mpc8536ds/mpc8536ds.c | 20 +++++++++---------- board/freescale/mpc8540ads/law.c | 2 +- board/freescale/mpc8540ads/tlb.c | 4 ++-- board/freescale/mpc8544ds/mpc8544ds.c | 26 ++++++++++++------------- board/freescale/mpc8548cds/mpc8548cds.c | 4 ++-- board/freescale/mpc8548cds/tlb.c | 4 ++-- board/freescale/mpc8560ads/law.c | 2 +- board/freescale/mpc8560ads/tlb.c | 4 ++-- board/freescale/mpc8568mds/law.c | 2 +- board/freescale/mpc8568mds/mpc8568mds.c | 4 ++-- board/freescale/mpc8572ds/mpc8572ds.c | 6 +++--- cpu/mpc85xx/pci.c | 16 +++++++++++---- include/configs/MPC8536DS.h | 16 +++++++-------- include/configs/MPC8540ADS.h | 8 ++++---- include/configs/MPC8541CDS.h | 8 ++++---- include/configs/MPC8544DS.h | 20 +++++++++---------- include/configs/MPC8548CDS.h | 14 ++++++------- include/configs/MPC8555CDS.h | 8 ++++---- include/configs/MPC8560ADS.h | 8 ++++---- include/configs/MPC8568MDS.h | 10 +++++----- include/configs/MPC8572DS.h | 12 ++++++------ 21 files changed, 103 insertions(+), 95 deletions(-) diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index e369d090c..280ae1a31 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -192,7 +192,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BASE, + CONFIG_SYS_PCIE3_MEM_BUS, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_SIZE, PCI_REGION_MEM); @@ -247,7 +247,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); @@ -259,10 +259,10 @@ pci_init_board(void) CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); -#ifdef CONFIG_SYS_PCIE1_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE1_MEM_BUS2 /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE2, + CONFIG_SYS_PCIE1_MEM_BUS2, CONFIG_SYS_PCIE1_MEM_PHYS2, CONFIG_SYS_PCIE1_MEM_SIZE2, PCI_REGION_MEM); @@ -310,7 +310,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BASE, + CONFIG_SYS_PCIE2_MEM_BUS, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); @@ -322,10 +322,10 @@ pci_init_board(void) CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); -#ifdef CONFIG_SYS_PCIE2_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE2_MEM_BUS2 /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BASE2, + CONFIG_SYS_PCIE2_MEM_BUS2, CONFIG_SYS_PCIE2_MEM_PHYS2, CONFIG_SYS_PCIE2_MEM_SIZE2, PCI_REGION_MEM); @@ -378,7 +378,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); @@ -390,10 +390,10 @@ pci_init_board(void) CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); -#ifdef CONFIG_SYS_PCI1_MEM_BASE2 +#ifdef CONFIG_SYS_PCI1_MEM_BUS2 /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE2, + CONFIG_SYS_PCI1_MEM_BUS2, CONFIG_SYS_PCI1_MEM_PHYS2, CONFIG_SYS_PCI1_MEM_SIZE2, PCI_REGION_MEM); diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c index 7dd8f2958..ff56e87dd 100644 --- a/board/freescale/mpc8540ads/law.c +++ b/board/freescale/mpc8540ads/law.c @@ -52,7 +52,7 @@ struct law_entry law_table[] = { /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_BUS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c index 2ec3ccce9..758bd7006 100644 --- a/board/freescale/mpc8540ads/tlb.c +++ b/board/freescale/mpc8540ads/tlb.c @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_BUS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 977731289..c3bf60a46 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -139,7 +139,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BASE, + CONFIG_SYS_PCIE3_MEM_BUS, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_SIZE, PCI_REGION_MEM); @@ -151,10 +151,10 @@ pci_init_board(void) CONFIG_SYS_PCIE3_IO_SIZE, PCI_REGION_IO); -#ifdef CONFIG_SYS_PCIE3_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE3_MEM_BUS2 /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BASE2, + CONFIG_SYS_PCIE3_MEM_BUS2, CONFIG_SYS_PCIE3_MEM_PHYS2, CONFIG_SYS_PCIE3_MEM_SIZE2, PCI_REGION_MEM); @@ -173,7 +173,7 @@ pci_init_board(void) * Activate ULI1575 legacy chip by performing a fake * memory access. Needed to make ULI RTC work. */ - in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BASE); + in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS); } else { printf (" PCIE3: disabled\n"); } @@ -206,7 +206,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); @@ -218,10 +218,10 @@ pci_init_board(void) CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); -#ifdef CONFIG_SYS_PCIE1_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE1_MEM_BUS2 /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE2, + CONFIG_SYS_PCIE1_MEM_BUS2, CONFIG_SYS_PCIE1_MEM_PHYS2, CONFIG_SYS_PCIE1_MEM_SIZE2, PCI_REGION_MEM); @@ -269,7 +269,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BASE, + CONFIG_SYS_PCIE2_MEM_BUS, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); @@ -281,10 +281,10 @@ pci_init_board(void) CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); -#ifdef CONFIG_SYS_PCIE2_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE2_MEM_BUS2 /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BASE2, + CONFIG_SYS_PCIE2_MEM_BUS2, CONFIG_SYS_PCIE2_MEM_PHYS2, CONFIG_SYS_PCIE2_MEM_SIZE2, PCI_REGION_MEM); @@ -337,7 +337,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); @@ -349,10 +349,10 @@ pci_init_board(void) CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); -#ifdef CONFIG_SYS_PCIE3_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE3_MEM_BUS2 /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BASE2, + CONFIG_SYS_PCIE3_MEM_BUS2, CONFIG_SYS_PCIE3_MEM_PHYS2, CONFIG_SYS_PCIE3_MEM_SIZE2, PCI_REGION_MEM); diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 90e89bc71..ff8d26fb9 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -306,7 +306,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); @@ -390,7 +390,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index eab212a4c..e96c9a7fc 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -62,14 +62,14 @@ struct fsl_e_tlb_entry tlb_table[] = { /* * TLB 2: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_BUS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), /* * TLB 3: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), #endif diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c index 7dd8f2958..ff56e87dd 100644 --- a/board/freescale/mpc8560ads/law.c +++ b/board/freescale/mpc8560ads/law.c @@ -52,7 +52,7 @@ struct law_entry law_table[] = { /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_BUS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c index 2ec3ccce9..758bd7006 100644 --- a/board/freescale/mpc8560ads/tlb.c +++ b/board/freescale/mpc8560ads/tlb.c @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_BUS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c index da7b6dcb7..a06ac2a0e 100644 --- a/board/freescale/mpc8568mds/law.c +++ b/board/freescale/mpc8568mds/law.c @@ -54,7 +54,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_SRIO_MEM_BUS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 7a23b338a..20f70fb52 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -397,7 +397,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); @@ -450,7 +450,7 @@ pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 88ab06d78..01143ec89 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -185,7 +185,7 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BASE, + CONFIG_SYS_PCIE3_MEM_BUS, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_SIZE, PCI_REGION_MEM); @@ -252,7 +252,7 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BASE, + CONFIG_SYS_PCIE2_MEM_BUS, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); @@ -307,7 +307,7 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index 787c6eb74..7a8184a50 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -31,6 +31,14 @@ #if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT) +#ifndef CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE +#endif + +#ifndef CONFIG_SYS_PCI2_MEM_BUS +#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE +#endif + static struct pci_controller *pci_hose; void @@ -80,7 +88,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose) pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16); } - pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff; pcix->potear1 = 0x00000000; pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff; pcix->powbear1 = 0x00000000; @@ -105,7 +113,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose) pcix->piwar3 = 0; pci_set_region(hose->regions + 0, - CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); @@ -165,7 +173,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose) */ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & 0x000fffff; + pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff; pcix2->potear1 = 0x00000000; pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff; pcix2->powbear1 = 0x00000000; @@ -190,7 +198,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose) pcix2->piwar3 = 0; pci_set_region(hose->regions + 0, - CONFIG_SYS_PCI2_MEM_BASE, + CONFIG_SYS_PCI2_MEM_BUS, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM); diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index fb9fc2e02..e280311a0 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -357,32 +357,32 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_BASE 0x90000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_BASE 0x98000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE +#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, direct to uli, tgtid 3, Base address 8000 */ -#define CONFIG_SYS_PCIE3_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE +#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BUS #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index f22b7529d..2483d507e 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -308,16 +308,16 @@ #define CONFIG_SYS_I2C_OFFSET 0x3000 /* RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE +#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ +#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BUS #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 399189c59..850384a9e 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -341,15 +341,15 @@ extern unsigned long get_clock_freq(void); * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 9b1b34cc8..e31c65b0c 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -266,38 +266,38 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ -#define CONFIG_SYS_PCI1_MEM_BASE 0xc0000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 1, tgtid 1, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE +#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 2,tgtid 2, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 3, direct to uli, tgtid 3, Base address b000 */ -#define CONFIG_SYS_PCIE3_MEM_BASE 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE +#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BUS #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ #define CONFIG_SYS_PCIE3_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ -#define CONFIG_SYS_PCIE3_MEM_BASE2 0xb0200000 -#define CONFIG_SYS_PCIE3_MEM_PHYS2 CONFIG_SYS_PCIE3_MEM_BASE2 +#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 +#define CONFIG_SYS_PCIE3_MEM_PHYS2 CONFIG_SYS_PCIE3_MEM_BUS2 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ #if defined(CONFIG_PCI) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index e1bd45ef1..2477c4839 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -367,16 +367,16 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ #ifdef CONFIG_PCI2 -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 @@ -384,8 +384,8 @@ extern unsigned long get_clock_freq(void); #endif #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 @@ -396,7 +396,7 @@ extern unsigned long get_clock_freq(void); /* * RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 +#define CONFIG_SYS_RIO_MEM_BUS 0xC0000000 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ #endif diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index c92f82d48..7c6e68a9b 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -339,15 +339,15 @@ extern unsigned long get_clock_freq(void); * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index bf4bd2c1a..91512056d 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -300,16 +300,16 @@ #define CONFIG_SYS_I2C_OFFSET 0x3000 /* RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE +#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ +#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BUS #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index da1f45422..6cc0685ad 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -322,21 +322,21 @@ extern unsigned long get_clock_freq(void); * General PCI * Memory Addresses are mapped 1-1. I/O is mapped from 0 */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ -#define CONFIG_SYS_SRIO_MEM_BASE 0xc0000000 +#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 #ifdef CONFIG_QE /* diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 6b56a0e08..58b92acff 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -380,24 +380,24 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ /* controller 3, direct to uli, tgtid 3, Base address 8000 */ -#define CONFIG_SYS_PCIE3_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BUS #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 From 5f91ef6acdbadec33e0192049e2b24a1d9692f1d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 2 Dec 2008 16:08:37 -0600 Subject: [PATCH 151/188] 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boards Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead of _IO_BASE so we are more explicit. Signed-off-by: Kumar Gala --- board/freescale/mpc8536ds/mpc8536ds.c | 8 ++++---- board/freescale/mpc8544ds/mpc8544ds.c | 8 ++++---- board/freescale/mpc8548cds/mpc8548cds.c | 4 ++-- board/freescale/mpc8568mds/mpc8568mds.c | 4 ++-- board/freescale/mpc8572ds/mpc8572ds.c | 6 +++--- cpu/mpc85xx/pci.c | 16 ++++++++++++---- include/configs/MPC8536DS.h | 12 ++++++------ include/configs/MPC8540ADS.h | 2 +- include/configs/MPC8541CDS.h | 4 ++-- include/configs/MPC8544DS.h | 12 ++++++------ include/configs/MPC8548CDS.h | 6 +++--- include/configs/MPC8555CDS.h | 4 ++-- include/configs/MPC8560ADS.h | 2 +- include/configs/MPC8568MDS.h | 4 ++-- include/configs/MPC8572DS.h | 10 +++++----- 15 files changed, 55 insertions(+), 47 deletions(-) diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 280ae1a31..1e2e2dc13 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -199,7 +199,7 @@ pci_init_board(void) /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE3_IO_BASE, + CONFIG_SYS_PCIE3_IO_BUS, CONFIG_SYS_PCIE3_IO_PHYS, CONFIG_SYS_PCIE3_IO_SIZE, PCI_REGION_IO); @@ -254,7 +254,7 @@ pci_init_board(void) /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); @@ -317,7 +317,7 @@ pci_init_board(void) /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BASE, + CONFIG_SYS_PCIE2_IO_BUS, CONFIG_SYS_PCIE2_IO_PHYS, CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); @@ -385,7 +385,7 @@ pci_init_board(void) /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_BUS, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index c3bf60a46..7ff5a9bb8 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -146,7 +146,7 @@ pci_init_board(void) /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE3_IO_BASE, + CONFIG_SYS_PCIE3_IO_BUS, CONFIG_SYS_PCIE3_IO_PHYS, CONFIG_SYS_PCIE3_IO_SIZE, PCI_REGION_IO); @@ -213,7 +213,7 @@ pci_init_board(void) /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); @@ -276,7 +276,7 @@ pci_init_board(void) /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BASE, + CONFIG_SYS_PCIE2_IO_BUS, CONFIG_SYS_PCIE2_IO_PHYS, CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); @@ -344,7 +344,7 @@ pci_init_board(void) /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_BUS, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index ff8d26fb9..70320ea1a 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -313,7 +313,7 @@ pci_init_board(void) /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_BUS, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); @@ -397,7 +397,7 @@ pci_init_board(void) /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 20f70fb52..915fae7fa 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -404,7 +404,7 @@ pci_init_board(void) /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_BUS, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); @@ -457,7 +457,7 @@ pci_init_board(void) /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 01143ec89..5148d337d 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -192,7 +192,7 @@ void pci_init_board(void) /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE3_IO_BASE, + CONFIG_SYS_PCIE3_IO_BUS, CONFIG_SYS_PCIE3_IO_PHYS, CONFIG_SYS_PCIE3_IO_SIZE, PCI_REGION_IO); @@ -259,7 +259,7 @@ void pci_init_board(void) /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BASE, + CONFIG_SYS_PCIE2_IO_BUS, CONFIG_SYS_PCIE2_IO_PHYS, CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); @@ -314,7 +314,7 @@ void pci_init_board(void) /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index 7a8184a50..fedf1a54d 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -35,10 +35,18 @@ #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE #endif +#ifndef CONFIG_SYS_PCI1_IO_BUS +#define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE +#endif + #ifndef CONFIG_SYS_PCI2_MEM_BUS #define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE #endif +#ifndef CONFIG_SYS_PCI2_IO_BUS +#define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE +#endif + static struct pci_controller *pci_hose; void @@ -95,7 +103,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose) pcix->powar1 = (POWAR_EN | POWAR_MEM_READ | POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1)); - pcix->potar2 = (CONFIG_SYS_PCI1_IO_BASE >> 12) & 0x000fffff; + pcix->potar2 = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff; pcix->potear2 = 0x00000000; pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff; pcix->powbear2 = 0x00000000; @@ -119,7 +127,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose) PCI_REGION_MEM); pci_set_region(hose->regions + 1, - CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_BUS, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); @@ -180,7 +188,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose) pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ | POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1)); - pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BASE >> 12) & 0x000fffff; + pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff; pcix2->potear2 = 0x00000000; pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff; pcix2->powbear2 = 0x00000000; @@ -204,7 +212,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose) PCI_REGION_MEM); pci_set_region(hose->regions + 1, - CONFIG_SYS_PCI2_IO_BASE, + CONFIG_SYS_PCI2_IO_BUS, CONFIG_SYS_PCI2_IO_PHYS, CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index e280311a0..b2a7d9ef0 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -360,7 +360,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ @@ -368,7 +368,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ @@ -376,7 +376,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ @@ -384,7 +384,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BUS #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ @@ -424,8 +424,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #endif #ifndef CONFIG_PCI_PNP - #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BASE + #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS + #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ #endif diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 2483d507e..18e4105ae 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -319,7 +319,7 @@ #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 850384a9e..03f6a6993 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -344,14 +344,14 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index e31c65b0c..8d0d7848d 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -269,7 +269,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ @@ -277,7 +277,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ @@ -285,7 +285,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ @@ -293,7 +293,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BUS #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ -#define CONFIG_SYS_PCIE3_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 @@ -336,8 +336,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif #ifndef CONFIG_PCI_PNP - #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BASE + #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS + #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ #endif diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 2477c4839..d76e38cca 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -370,7 +370,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ @@ -378,7 +378,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ #endif @@ -387,7 +387,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ #endif diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 7c6e68a9b..738fe52a5 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -342,14 +342,14 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 91512056d..0ef5acdf1 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -311,7 +311,7 @@ #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 6cc0685ad..8b067394e 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -325,14 +325,14 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 58b92acff..f665fecc7 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -383,7 +383,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BUS #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ @@ -391,7 +391,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ @@ -399,7 +399,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ @@ -436,8 +436,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #endif #ifndef CONFIG_PCI_PNP - #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BASE - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BASE + #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS + #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ #endif From a6e04c344ad1eefd47a75484441b385da815b8df Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 2 Dec 2008 16:08:38 -0600 Subject: [PATCH 152/188] 85xx: Use CONFIG_SYS_{PCI*,RIO*}_MEM_PHYS for physical address on FSL boards Use the _MEM_PHYS defines instead of _MEM_BUS for LAW and real address fields of TLBs. This is what we should have always been using from the start. Signed-off-by: Kumar Gala Acked-by: Andy Fleming --- board/freescale/mpc8540ads/law.c | 2 +- board/freescale/mpc8540ads/tlb.c | 4 ++-- board/freescale/mpc8548cds/tlb.c | 4 ++-- board/freescale/mpc8560ads/law.c | 2 +- board/freescale/mpc8560ads/tlb.c | 4 ++-- board/freescale/mpc8568mds/law.c | 2 +- include/configs/MPC8568MDS.h | 1 + 7 files changed, 10 insertions(+), 9 deletions(-) diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c index ff56e87dd..f5644e154 100644 --- a/board/freescale/mpc8540ads/law.c +++ b/board/freescale/mpc8540ads/law.c @@ -52,7 +52,7 @@ struct law_entry law_table[] = { /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BUS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c index 758bd7006..205c06ada 100644 --- a/board/freescale/mpc8540ads/tlb.c +++ b/board/freescale/mpc8540ads/tlb.c @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_BUS, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index e96c9a7fc..b7af25da6 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -62,14 +62,14 @@ struct fsl_e_tlb_entry tlb_table[] = { /* * TLB 2: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_BUS, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), /* * TLB 3: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), #endif diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c index ff56e87dd..f5644e154 100644 --- a/board/freescale/mpc8560ads/law.c +++ b/board/freescale/mpc8560ads/law.c @@ -52,7 +52,7 @@ struct law_entry law_table[] = { /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BUS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c index 758bd7006..205c06ada 100644 --- a/board/freescale/mpc8560ads/tlb.c +++ b/board/freescale/mpc8560ads/tlb.c @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_BUS, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c index a06ac2a0e..3114e8a17 100644 --- a/board/freescale/mpc8568mds/law.c +++ b/board/freescale/mpc8568mds/law.c @@ -54,7 +54,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_SRIO_MEM_BUS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 8b067394e..77abe4f5b 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -337,6 +337,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ #define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 +#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 #ifdef CONFIG_QE /* From 5af0fdd81c3370c3a51421208fda568bdcbbec23 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 2 Dec 2008 16:08:39 -0600 Subject: [PATCH 153/188] 85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards Introduce a new define to seperate out the virtual address that PCI memory is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala Acked-by: Andy Fleming --- board/freescale/mpc8536ds/tlb.c | 2 +- board/freescale/mpc8540ads/tlb.c | 8 ++++---- board/freescale/mpc8541cds/tlb.c | 8 ++++---- board/freescale/mpc8544ds/tlb.c | 6 +++--- board/freescale/mpc8548cds/tlb.c | 6 +++--- board/freescale/mpc8555cds/tlb.c | 8 ++++---- board/freescale/mpc8560ads/tlb.c | 8 ++++---- board/freescale/mpc8568mds/tlb.c | 2 +- board/freescale/mpc8572ds/mpc8572ds.c | 2 +- board/freescale/mpc8572ds/tlb.c | 6 +++--- include/configs/MPC8536DS.h | 14 +++++++++----- include/configs/MPC8540ADS.h | 6 ++++-- include/configs/MPC8541CDS.h | 6 ++++-- include/configs/MPC8544DS.h | 17 ++++++++++++----- include/configs/MPC8548CDS.h | 11 ++++++++--- include/configs/MPC8555CDS.h | 6 ++++-- include/configs/MPC8560ADS.h | 6 ++++-- include/configs/MPC8568MDS.h | 7 +++++-- include/configs/MPC8572DS.h | 9 ++++++--- 19 files changed, 84 insertions(+), 54 deletions(-) diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c index f4bab550c..ec76d5c79 100644 --- a/board/freescale/mpc8536ds/tlb.c +++ b/board/freescale/mpc8536ds/tlb.c @@ -58,7 +58,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 1, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1G, 1), diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c index 205c06ada..a9925d542 100644 --- a/board/freescale/mpc8540ads/tlb.c +++ b/board/freescale/mpc8540ads/tlb.c @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c index bf957c08c..ae6812fc9 100644 --- a/board/freescale/mpc8541cds/tlb.c +++ b/board/freescale/mpc8541cds/tlb.c @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xa0000000 256M PCI2 MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xb0000000 256M PCI2 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c index c7442b26f..d99441b2c 100644 --- a/board/freescale/mpc8544ds/tlb.c +++ b/board/freescale/mpc8544ds/tlb.c @@ -52,21 +52,21 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 1G Non-cacheable, guarded * 0x80000000 1G PCIE 8,9,a,b */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_PHYS, CONFIG_SYS_PCIE_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1G, 1), /* * TLB 2: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), /* * TLB 3: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index b7af25da6..2267ad747 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 1G Non-cacheable, guarded * 0x80000000 1G PCI1/PCIE 8,9,a,b */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1G, 1), @@ -62,14 +62,14 @@ struct fsl_e_tlb_entry tlb_table[] = { /* * TLB 2: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), /* * TLB 3: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), #endif diff --git a/board/freescale/mpc8555cds/tlb.c b/board/freescale/mpc8555cds/tlb.c index bf957c08c..ae6812fc9 100644 --- a/board/freescale/mpc8555cds/tlb.c +++ b/board/freescale/mpc8555cds/tlb.c @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xa0000000 256M PCI2 MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xb0000000 256M PCI2 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c index 205c06ada..a9925d542 100644 --- a/board/freescale/mpc8560ads/tlb.c +++ b/board/freescale/mpc8560ads/tlb.c @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c index 107755273..8470c878e 100644 --- a/board/freescale/mpc8568mds/tlb.c +++ b/board/freescale/mpc8568mds/tlb.c @@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0x80000000 512M PCI1 MEM * 0xa0000000 512M PCIe MEM */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1G, 1), diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 5148d337d..e57f9fff2 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -215,7 +215,7 @@ void pci_init_board(void) pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ), PCI_BASE_ADDRESS_1, &temp32); - if (temp32 >= CONFIG_SYS_PCIE3_MEM_PHYS) { + if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { debug(" uli1572 read to %x\n", temp32); in_be32((unsigned *)temp32); } diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index 6cb3eb1d9..594ff0560 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -59,16 +59,16 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 2, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index b2a7d9ef0..d537940f8 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -357,32 +357,36 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, direct to uli, tgtid 3, Base address 8000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BUS +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 18e4105ae..645736bc3 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -308,16 +308,18 @@ #define CONFIG_SYS_I2C_OFFSET 0x3000 /* RapidIO MMU */ +#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BUS +#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 03f6a6993..ed628a0c3 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -341,15 +341,17 @@ extern unsigned long get_clock_freq(void); * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ +#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS +#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 8d0d7848d..4a43edf1c 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -263,41 +263,48 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ +#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 1, tgtid 1, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 2,tgtid 2, Base address a000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 3, direct to uli, tgtid 3, Base address b000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BUS +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ +#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 -#define CONFIG_SYS_PCIE3_MEM_PHYS2 CONFIG_SYS_PCIE3_MEM_BUS2 +#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ #if defined(CONFIG_PCI) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index d76e38cca..7110c3416 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -365,18 +365,21 @@ extern unsigned long get_clock_freq(void); * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ #ifdef CONFIG_PCI2 +#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS +#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 @@ -384,8 +387,9 @@ extern unsigned long get_clock_freq(void); #endif #ifdef CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 @@ -396,6 +400,7 @@ extern unsigned long get_clock_freq(void); /* * RapidIO MMU */ +#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000 #define CONFIG_SYS_RIO_MEM_BUS 0xC0000000 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ #endif diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 738fe52a5..78fd683bf 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -339,15 +339,17 @@ extern unsigned long get_clock_freq(void); * General PCI * Addresses are mapped 1-1. */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ +#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS +#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 0ef5acdf1..4d18dd824 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -300,16 +300,18 @@ #define CONFIG_SYS_I2C_OFFSET 0x3000 /* RapidIO MMU */ +#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BUS +#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 77abe4f5b..fcaca1a4c 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -322,20 +322,23 @@ extern unsigned long get_clock_freq(void); * General PCI * Memory Addresses are mapped 1-1. I/O is mapped from 0 */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ +#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 #define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 #define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index f665fecc7..8c4aa7d52 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -380,24 +380,27 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ /* controller 3, direct to uli, tgtid 3, Base address 8000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BUS +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 From aca5f018a8386b85469482ed9867e3e29a2437d0 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 2 Dec 2008 16:08:40 -0600 Subject: [PATCH 154/188] 85xx: Introduce CONFIG_SYS_PCI*_IO_VIRT for FSL boards Introduce a new define to seperate out the virtual address that PCI IO space is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT. Signed-off-by: Kumar Gala Acked-by: Andy Fleming --- board/freescale/mpc8536ds/tlb.c | 2 +- board/freescale/mpc8572ds/tlb.c | 2 +- include/configs/MPC8536DS.h | 10 +++++++--- include/configs/MPC8540ADS.h | 1 + include/configs/MPC8541CDS.h | 2 ++ include/configs/MPC8544DS.h | 8 ++++++-- include/configs/MPC8548CDS.h | 3 +++ include/configs/MPC8555CDS.h | 2 ++ include/configs/MPC8560ADS.h | 1 + include/configs/MPC8568MDS.h | 2 ++ include/configs/MPC8572DS.h | 5 ++++- 11 files changed, 30 insertions(+), 8 deletions(-) diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c index ec76d5c79..35a13d449 100644 --- a/board/freescale/mpc8536ds/tlb.c +++ b/board/freescale/mpc8536ds/tlb.c @@ -63,7 +63,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 2, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256K, 1), diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index 594ff0560..d832f8974 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -73,7 +73,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 5, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_PHYS, CONFIG_SYS_PCIE3_IO_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index d537940f8..63a0f7e67 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -361,6 +361,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ @@ -370,6 +371,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ @@ -379,6 +381,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ @@ -388,6 +391,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ @@ -398,10 +402,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_PCI_PNP /* do pci plug-and-play */ /*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_PHYS +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT /*PCI video card used*/ -/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/ +/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ /* video */ #define CONFIG_VIDEO @@ -414,7 +418,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_ATI_RADEON_FB #define CONFIG_VIDEO_LOGO /*#define CONFIG_CONSOLE_CURSOR*/ -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_PHYS +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT #endif #undef CONFIG_EEPRO100 diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 645736bc3..0d03b0b85 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -321,6 +321,7 @@ #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index ed628a0c3..fa82fbc6f 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -345,6 +345,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ @@ -353,6 +354,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 4a43edf1c..59cfde628 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -272,6 +272,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ @@ -281,6 +282,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ @@ -290,6 +292,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ @@ -299,6 +302,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ @@ -310,10 +314,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_PCI) /*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_PHYS +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT /*PCI video card used*/ -/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/ +/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ /* video */ #define CONFIG_VIDEO diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 7110c3416..95bce9514 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -372,6 +372,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ @@ -381,6 +382,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ @@ -391,6 +393,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 78fd683bf..6bf09613b 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -343,6 +343,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ @@ -351,6 +352,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 4d18dd824..3f78a6e12 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -313,6 +313,7 @@ #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index fcaca1a4c..58ff52b33 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -326,6 +326,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ @@ -334,6 +335,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 8c4aa7d52..0277a42a2 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -384,6 +384,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ @@ -393,6 +394,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ @@ -402,6 +404,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ @@ -409,7 +412,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #if defined(CONFIG_PCI) /*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_PHYS +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT /* video */ #define CONFIG_VIDEO From 80ee3ce6d7fe9441b4352d7cfaf6afc2507b1106 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Fri, 21 Nov 2008 16:31:22 +0800 Subject: [PATCH 155/188] fsl-ddr: update the bit mask for DDR3 controller According to the latest 8572 UM, the DDR3 controller is expanding the bit mask, and we use the extend ACTTOPRE mode when tRAS more than 19 MCLK. Signed-off-by: Dave Liu --- cpu/mpc8xxx/ddr/ctrl_regs.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 1783e927a..d5cdc362f 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -185,10 +185,14 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */ unsigned int cntl_adj = 0; /* Control Adjust */ + /* If the tRAS > 19 MCLK, we use the ext mode */ + if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13) + ext_acttopre = 1; + ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4; ddr->timing_cfg_3 = (0 | ((ext_acttopre & 0x1) << 24) - | ((ext_refrec & 0x7) << 16) + | ((ext_refrec & 0xF) << 16) | ((ext_caslat & 0x1) << 12) | ((cntl_adj & 0x7) << 0) ); @@ -251,12 +255,12 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps); ddr->timing_cfg_1 = (0 - | ((pretoact_mclk & 0x07) << 28) + | ((pretoact_mclk & 0x0F) << 28) | ((acttopre_mclk & 0x0F) << 24) - | ((acttorw_mclk & 0x7) << 20) + | ((acttorw_mclk & 0xF) << 20) | ((caslat_ctrl & 0xF) << 16) | ((refrec_ctrl & 0xF) << 12) - | ((wrrec_mclk & 0x07) << 8) + | ((wrrec_mclk & 0x0F) << 8) | ((acttoact_mclk & 0x07) << 4) | ((wrtord_mclk & 0x07) << 0) ); From 22ff3d01348e0a2dc369b7efcbac30e4ce86d178 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Fri, 21 Nov 2008 16:31:29 +0800 Subject: [PATCH 156/188] fsl-ddr: clean up the ddr code for DDR3 controller - The DDR3 controller is expanding the bits for timing config - Add the DDR3 32-bit bus mode support Signed-off-by: Dave Liu Acked-by: Andy Fleming --- cpu/mpc8xxx/ddr/ctrl_regs.c | 24 +++++++++++++----------- include/asm-ppc/fsl_ddr_sdram.h | 3 +++ 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index d5cdc362f..eae794c76 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -167,7 +167,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) | ((trrt_mclk & 0x3) << 26) /* RRT */ | ((twwt_mclk & 0x3) << 24) /* WWT */ | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */ - | ((pre_pd_exit_mclk & 0x7) << 16) /* PRE_PD_EXIT */ + | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */ | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */ | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */ ); @@ -313,13 +313,13 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps); ddr->timing_cfg_2 = (0 - | ((add_lat_mclk & 0x7) << 28) + | ((add_lat_mclk & 0xf) << 28) | ((cpo & 0x1f) << 23) - | ((wr_lat & 0x7) << 19) + | ((wr_lat & 0xf) << 19) | ((rd_to_pre & 0x7) << 13) | ((wr_data_delay & 0x7) << 10) | ((cke_pls & 0x7) << 6) - | ((four_act & 0x1f) << 0) + | ((four_act & 0x3f) << 0) ); debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); } @@ -336,7 +336,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, unsigned int sdram_type; /* Type of SDRAM */ unsigned int dyn_pwr; /* Dynamic power management mode */ unsigned int dbw; /* DRAM dta bus width */ - unsigned int eight_be; /* 8-beat burst enable */ + unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */ unsigned int ncap = 0; /* Non-concurrent auto-precharge */ unsigned int threeT_en; /* Enable 3T timing */ unsigned int twoT_en; /* Enable 2T timing */ @@ -363,7 +363,9 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, dyn_pwr = popts->dynamic_power; dbw = popts->data_bus_width; - eight_be = 0; /* always 0 for DDR2 */ + /* DDR3 must use 8-beat bursts when using 32-bit bus mode */ + if ((sdram_type == SDRAM_TYPE_DDR3) && (dbw == 0x1)) + eight_be = 1; threeT_en = popts->threeT_en; twoT_en = popts->twoT_en; ba_intlv_ctl = popts->ba_intlv_ctl; @@ -695,10 +697,10 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr) unsigned int wodt_off = 0; /* Write to ODT off */ ddr->timing_cfg_5 = (0 - | ((rodt_on & 0xf) << 24) - | ((rodt_off & 0xf) << 20) - | ((wodt_on & 0xf) << 12) - | ((wodt_off & 0xf) << 8) + | ((rodt_on & 0x1f) << 24) + | ((rodt_off & 0x7) << 20) + | ((wodt_on & 0x1f) << 12) + | ((wodt_off & 0x7) << 8) ); debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); } @@ -748,7 +750,7 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr) | ((wrlvl_dqsen & 0x7) << 16) | ((wrlvl_smpl & 0xf) << 12) | ((wrlvl_wlr & 0x7) << 8) - | ((wrlvl_start & 0xF) << 0) + | ((wrlvl_start & 0x1F) << 0) ); } diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index c1ea7cd6b..0006c21a0 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -34,7 +34,10 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; #elif defined(CONFIG_FSL_DDR3) #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 #endif +#endif /* #if defined(CONFIG_FSL_DDR1) */ /* define bank(chip select) interleaving mode */ #define FSL_DDR_CS0_CS1 0x40 From 22cca7e1cd54590e967c73558b07ffbdccd39504 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Fri, 21 Nov 2008 16:31:35 +0800 Subject: [PATCH 157/188] fsl-ddr: make the self refresh idle threshold configurable Some 85xx processors have the advanced power management feature, such as wake up ARP, that needs enable the automatic self refresh. If the DDR controller pass the SR_IT (self refresh idle threshold) idle cycles, it will automatically enter self refresh. However, anytime one transaction is issued to the DDR controller, it will reset the counter and exit self refresh state. Signed-off-by: Dave Liu Acked-by: Andy Fleming --- cpu/mpc8xxx/ddr/ctrl_regs.c | 12 ++++++++---- include/asm-ppc/fsl_ddr_sdram.h | 4 ++++ 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index eae794c76..292980d0b 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -755,10 +755,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr) } /* DDR Self Refresh Counter (DDR_SR_CNTR) */ -static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr) +static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) { - unsigned int sr_it = 0; /* Self Refresh Idle Threshold */ - + /* Self Refresh Idle Threshold */ ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; } @@ -861,6 +860,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, unsigned int i; unsigned int cas_latency; unsigned int additive_latency; + unsigned int sr_it; memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); @@ -882,6 +882,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, ? popts->additive_latency_override_value : common_dimm->additive_latency; + sr_it = (popts->auto_self_refresh_en) + ? popts->sr_it + : 0; + /* Chip Select Memory Bounds (CSn_BNDS) */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { phys_size_t sa = 0; @@ -1042,7 +1046,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_wrlvl_cntl(ddr); set_ddr_pd_cntl(ddr); - set_ddr_sr_cntr(ddr); + set_ddr_sr_cntr(ddr, sr_it); set_ddr_sdram_rcw_1(ddr); set_ddr_sdram_rcw_2(ddr); diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index 0006c21a0..b213af35e 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -146,6 +146,10 @@ typedef struct memctl_options_s { unsigned int bstopre; unsigned int tCKE_clock_pulse_width_ps; /* tCKE */ unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */ + + /* Automatic self refresh */ + unsigned int auto_self_refresh_en; + unsigned int sr_it; } memctl_options_t; extern phys_size_t fsl_ddr_sdram(void); From b4983e16d150ab7d039704c310aacbd2f4dc1e0f Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Fri, 21 Nov 2008 16:31:43 +0800 Subject: [PATCH 158/188] fsl-ddr: use the 1T timing as default configuration For light loaded system, we use the 1T timing to gain better memory performance, but for some heavily loaded system, you have to add the 2T timing options to board files. Signed-off-by: Dave Liu Acked-by: Andy Fleming --- board/freescale/mpc8540ads/ddr.c | 3 +++ board/freescale/mpc8544ds/ddr.c | 3 +++ board/freescale/mpc8560ads/ddr.c | 3 +++ board/freescale/mpc8610hpcd/ddr.c | 3 +++ board/freescale/mpc8641hpcn/ddr.c | 2 ++ board/stxgp3/ddr.c | 3 +++ board/stxssa/ddr.c | 3 +++ cpu/mpc8xxx/ddr/options.c | 2 +- 8 files changed, 21 insertions(+), 1 deletion(-) diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c index 7850794d6..93d110071 100644 --- a/board/freescale/mpc8540ads/ddr.c +++ b/board/freescale/mpc8540ads/ddr.c @@ -65,6 +65,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, */ popts->write_data_delay = 3; + /* 2T timing enable */ + popts->twoT_en = 1; + /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c index 34f84a265..b8330eb96 100644 --- a/board/freescale/mpc8544ds/ddr.c +++ b/board/freescale/mpc8544ds/ddr.c @@ -75,6 +75,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, */ popts->write_data_delay = 3; + /* 2T timing enable */ + popts->twoT_en = 1; + /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c index 7850794d6..93d110071 100644 --- a/board/freescale/mpc8560ads/ddr.c +++ b/board/freescale/mpc8560ads/ddr.c @@ -65,6 +65,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, */ popts->write_data_delay = 3; + /* 2T timing enable */ + popts->twoT_en = 1; + /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c index 414ac243a..0117d136b 100644 --- a/board/freescale/mpc8610hpcd/ddr.c +++ b/board/freescale/mpc8610hpcd/ddr.c @@ -74,6 +74,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, */ popts->write_data_delay = 3; + /* 2T timing enable */ + popts->twoT_en = 1; + /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c index 3789b5442..8dc249b99 100644 --- a/board/freescale/mpc8641hpcn/ddr.c +++ b/board/freescale/mpc8641hpcn/ddr.c @@ -162,4 +162,6 @@ void fsl_ddr_board_options(memctl_options_t *popts, } } + /* 2T timing enable */ + popts->twoT_en = 1; } diff --git a/board/stxgp3/ddr.c b/board/stxgp3/ddr.c index 7850794d6..93d110071 100644 --- a/board/stxgp3/ddr.c +++ b/board/stxgp3/ddr.c @@ -65,6 +65,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, */ popts->write_data_delay = 3; + /* 2T timing enable */ + popts->twoT_en = 1; + /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed diff --git a/board/stxssa/ddr.c b/board/stxssa/ddr.c index 7850794d6..93d110071 100644 --- a/board/stxssa/ddr.c +++ b/board/stxssa/ddr.c @@ -65,6 +65,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, */ popts->write_data_delay = 3; + /* 2T timing enable */ + popts->twoT_en = 1; + /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c index af7f73a83..d4702d73b 100644 --- a/cpu/mpc8xxx/ddr/options.c +++ b/cpu/mpc8xxx/ddr/options.c @@ -142,7 +142,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * - number of components, number of active ranks * - how much time you want to spend playing around */ - popts->twoT_en = 1; + popts->twoT_en = 0; popts->threeT_en = 0; /* From bf5b1f0c0d28ce062e1d368680632dfb099de692 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Fri, 21 Nov 2008 16:31:53 +0800 Subject: [PATCH 159/188] 85xx: enable the auto self refresh for wake up ARP The wake up ARP feature need use the memory to process wake up packet, we enable auto self refresh to support it. Signed-off-by: Dave Liu Acked-by: Andy Fleming --- board/freescale/mpc8536ds/ddr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c index 3135d6dfe..2bad787d6 100644 --- a/board/freescale/mpc8536ds/ddr.c +++ b/board/freescale/mpc8536ds/ddr.c @@ -79,4 +79,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; + + /* + * For wake up arp feature, we need enable auto self refresh + */ + popts->auto_self_refresh_en = 1; + popts->sr_it = 0x6; } From 2fc7eb0cfc608c9369001d57a0411af5e6a58f7c Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Thu, 15 Jan 2009 11:58:35 -0500 Subject: [PATCH 160/188] Add secondary CPUs processor frequency for e500 core This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS, and prints each CPU's frequency separately. It also fixes up each CPU's frequency in "clock-frequency" of fdt blob. Signed-off-by: James Yang Signed-off-by: Haiying Wang --- cpu/mpc85xx/cpu.c | 7 +++++-- cpu/mpc85xx/fdt.c | 15 +++++++++++++-- cpu/mpc85xx/speed.c | 10 ++++++---- include/e500.h | 6 +++++- 4 files changed, 29 insertions(+), 9 deletions(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 15ba7f1c5..a34e2515e 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -90,6 +90,7 @@ int checkcpu (void) #else u32 ddr_ratio = 0; #endif + int i; svr = get_svr(); ver = SVR_SOC_VER(svr); @@ -141,8 +142,10 @@ int checkcpu (void) get_sys_info(&sysinfo); - puts("Clock Configuration:\n"); - printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor)); + puts("Clock Configuration:\n "); + for (i = 0; i < CONFIG_NUM_CPUS; i++) + printf("CPU%d:%-4s MHz, ", + i,strmhz(buf1, sysinfo.freqProcessor[i])); printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); switch (ddr_ratio) { diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 69fab9952..1fae47c2d 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -213,6 +213,10 @@ void fdt_add_enet_stashing(void *fdt) void ft_cpu_setup(void *blob, bd_t *bd) { + int off; + int val; + sys_info_t sysinfo; + /* delete crypto node if not on an E-processor */ if (!IS_E_PROCESSOR(get_svr())) fdt_fixup_crypto_node(blob, 0); @@ -228,8 +232,15 @@ void ft_cpu_setup(void *blob, bd_t *bd) "timebase-frequency", bd->bi_busfreq / 8, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "clock-frequency", bd->bi_intfreq, 1); + get_sys_info(&sysinfo); + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]); + fdt_setprop(blob, off, "clock-frequency", &val, 4); + off = fdt_node_offset_by_prop_value(blob, off, "device_type", + "cpu", 4); + } do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 0d55228b6..b0f47e042 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -39,17 +39,19 @@ void get_sys_info (sys_info_t * sysInfo) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint plat_ratio,e500_ratio,half_freqSystemBus; uint lcrr_div; + int i; plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; - e500_ratio = (gur->porpllsr) & 0x003f0000; - e500_ratio >>= 16; /* Divide before multiply to avoid integer * overflow for processor speeds above 2GHz */ half_freqSystemBus = sysInfo->freqSystemBus/2; - sysInfo->freqProcessor = e500_ratio*half_freqSystemBus; + for (i = 0; i < CONFIG_NUM_CPUS; i++) { + e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; + sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus; + } /* Note: freqDDRBus is the MCLK frequency, not the data rate. */ sysInfo->freqDDRBus = sysInfo->freqSystemBus; @@ -105,7 +107,7 @@ int get_clocks (void) dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; #endif get_sys_info (&sys_info); - gd->cpu_clk = sys_info.freqProcessor; + gd->cpu_clk = sys_info.freqProcessor[0]; gd->bus_clk = sys_info.freqSystemBus; gd->mem_clk = sys_info.freqDDRBus; gd->lbc_clk = sys_info.freqLocalBus; diff --git a/include/e500.h b/include/e500.h index 9d3c8417c..4c5eeb74e 100644 --- a/include/e500.h +++ b/include/e500.h @@ -8,9 +8,13 @@ #ifndef __ASSEMBLY__ +#ifndef CONFIG_NUM_CPUS +#define CONFIG_NUM_CPUS 1 +#endif + typedef struct { - unsigned long freqProcessor; + unsigned long freqProcessor[CONFIG_NUM_CPUS]; unsigned long freqSystemBus; unsigned long freqDDRBus; unsigned long freqLocalBus; From 72a9414a8e21e9536822c7353bc08d21ce5ad53d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 23 Jan 2009 14:22:12 -0600 Subject: [PATCH 161/188] 85xx: Use BR_ADDR macro for NAND chipselects Use the new BR_ADDR macro to properly setup the address field of the localbus chipselects used by NAND. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala --- include/configs/MPC8536DS.h | 8 ++++---- include/configs/MPC8572DS.h | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 63a0f7e67..1898e265c 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -256,7 +256,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ +#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2< Date: Fri, 23 Jan 2009 14:22:13 -0600 Subject: [PATCH 162/188] 85xx: Handle eLBC difference w/36-bit physical The eLBC only handles 32-bit physical address in systems with 36-bit physical. The previos generation of LBC handled 34-bit physical address in 36-bit systems. Added a new CONFIG option to convey the difference between the LBC and eLBC. Also added defines for XAM bits used in LBC for the extended 34-bit support. Signed-off-by: Kumar Gala --- include/asm-ppc/fsl_lbc.h | 8 +++++++- include/configs/MPC8536DS.h | 1 + include/configs/MPC8572DS.h | 1 + 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index e492c62a8..9fa0b6594 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -28,6 +28,8 @@ #define BR_BA 0xFFFF8000 #define BR_BA_SHIFT 15 +#define BR_XBA 0x00006000 +#define BR_XBA_SHIFT 13 #define BR_PS 0x00001800 #define BR_PS_SHIFT 11 #define BR_PS_8 0x00000800 /* Port Size 8 bit */ @@ -70,7 +72,7 @@ #endif /* Convert an address into the right format for the BR registers */ -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC) #define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \ ((x & 0x300000000ULL) >> 19))) #else @@ -90,6 +92,8 @@ #define OR_GPCM_AM 0xFFFF8000 #define OR_GPCM_AM_SHIFT 15 +#define OR_GPCM_XAM 0x00006000 +#define OR_GPCM_XAM_SHIFT 13 #define OR_GPCM_BCTLD 0x00001000 #define OR_GPCM_BCTLD_SHIFT 12 #define OR_GPCM_CSNT 0x00000800 @@ -132,6 +136,8 @@ #define OR_FCM_AM 0xFFFF8000 #define OR_FCM_AM_SHIFT 15 +#define OR_FCM_XAM 0x00006000 +#define OR_FCM_XAM_SHIFT 13 #define OR_FCM_BCTLD 0x00001000 #define OR_FCM_BCTLD_SHIFT 12 #define OR_FCM_PGS 0x00000400 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 1898e265c..e379d5327 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -34,6 +34,7 @@ #define CONFIG_MPC8536 1 #define CONFIG_MPC8536DS 1 +#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 332a0e337..a0f4fcccb 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -36,6 +36,7 @@ #define CONFIG_MP 1 /* support multiple processors */ #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ +#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ From 18af1c5f0f7402dc0d6a71b012c68025dd97cf72 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 23 Jan 2009 14:22:14 -0600 Subject: [PATCH 163/188] 85xx: Add a 36-bit physical configuration for MPC8572DS We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary to allow for larger memory sizes. Signed-off-by: Kumar Gala --- MAKEALL | 1 + Makefile | 8 ++++++- include/configs/MPC8572DS.h | 47 ++++++++++++++++++++++++++++++++++++- 3 files changed, 54 insertions(+), 2 deletions(-) diff --git a/MAKEALL b/MAKEALL index f6271a29f..49d5d2f76 100755 --- a/MAKEALL +++ b/MAKEALL @@ -372,6 +372,7 @@ LIST_85xx=" \ MPC8560ADS \ MPC8568MDS \ MPC8572DS \ + MPC8572DS_36BIT \ PM854 \ PM856 \ sbc8540 \ diff --git a/Makefile b/Makefile index 5cc950dea..ad79a2a6a 100644 --- a/Makefile +++ b/Makefile @@ -2398,8 +2398,14 @@ MPC8555CDS_config: unconfig MPC8568MDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale +MPC8572DS_36BIT_config \ MPC8572DS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8572ds freescale + @mkdir -p $(obj)include + @if [ "$(findstring _36BIT_,$@)" ] ; then \ + echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \ + $(XECHO) "... enabling 36-bit physical addressing." ; \ + fi + @$(MKCONFIG) -a MPC8572DS ppc mpc85xx mpc8572ds freescale PM854_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854 diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index a0f4fcccb..ac0a4641e 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -75,6 +75,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_ENABLE_36BIT_PHYS 1 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x7fffffff #define CONFIG_PANIC_HANG /* do not reset board on panic */ @@ -85,7 +90,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ +#else #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) @@ -170,7 +179,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Local Bus Definitions */ #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#else #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 @@ -178,7 +191,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -199,7 +212,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#ifdef CONFIG_PHYS_64BIT +#define PIXIS_BASE_PHYS 0xfffdf0000ull +#else #define PIXIS_BASE_PHYS PIXIS_BASE +#endif #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ @@ -264,7 +281,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ #define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#else #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ CONFIG_SYS_NAND_BASE + 0x40000, \ CONFIG_SYS_NAND_BASE + 0x80000,\ @@ -383,31 +404,55 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* controller 3, direct to uli, tgtid 3, Base address 8000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull +#else #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 +#endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull +#else #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 +#endif #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull +#else #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull +#else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 +#endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #if defined(CONFIG_PCI) From 3feb647f3fd0881382c7a29f4cf280b66473ae0a Mon Sep 17 00:00:00 2001 From: Sergei Poselenov Date: Tue, 4 Nov 2008 13:51:18 +0100 Subject: [PATCH 164/188] Add a do_div() wrapper macro, lldiv(). Add a do_div() wrapper, lldiv(). The new inline function doesn't modify the dividend and returns the result of division, so it is useful in complex expressions, i.e. "return(a/b)" -> "return(lldiv(a,b))" Signed-off-by: Sergei Poselenov --- include/div64.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/div64.h b/include/div64.h index c495aefb0..d83314435 100644 --- a/include/div64.h +++ b/include/div64.h @@ -36,4 +36,14 @@ extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor); __rem; \ }) +/* Wrapper for do_div(). Doesn't modify dividend and returns + * the result, not reminder. + */ +static inline uint64_t lldiv(uint64_t dividend, uint32_t divisor) +{ + uint64_t __res = dividend; + do_div(__res, divisor); + return(__res); +} + #endif /* _ASM_GENERIC_DIV64_H */ From de0443614af4d16675ab436665aeb11ddc9f7214 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 20 Nov 2008 09:57:47 +0100 Subject: [PATCH 165/188] powerpc: 83xx: add support for the kmeter1 board This patch adds support for the kmeter1 board from Keymile, based on a Freescale MPC8360 CPU. - serial console on UART 1 - 256 MB DDR2 RAM - 64 MB NOR Flash - Ethernet RMII Mode over UCC4 - PHY SMSC LAN8700 Signed-off-by: Heiko Schocher --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/keymile/kmeter1/Makefile | 51 ++++ board/keymile/kmeter1/config.mk | 24 ++ board/keymile/kmeter1/kmeter1.c | 153 ++++++++++ doc/README.kmeter1 | 91 ++++++ include/configs/kmeter1.h | 523 ++++++++++++++++++++++++++++++++ 8 files changed, 847 insertions(+) create mode 100644 board/keymile/kmeter1/Makefile create mode 100644 board/keymile/kmeter1/config.mk create mode 100644 board/keymile/kmeter1/kmeter1.c create mode 100644 doc/README.kmeter1 create mode 100644 include/configs/kmeter1.h diff --git a/MAINTAINERS b/MAINTAINERS index dfe54a7cb..ef53a7905 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -374,6 +374,7 @@ Heiko Schocher ids8247 MPC8247 jupiter MPC5200 + kmeter1 MPC8360 mgcoge MPC8247 mgsuvd MPC852 mucmc52 MPC5200 diff --git a/MAKEALL b/MAKEALL index f6271a29f..485fb884a 100755 --- a/MAKEALL +++ b/MAKEALL @@ -335,6 +335,7 @@ LIST_8260=" \ ######################################################################### LIST_83xx=" \ + kmeter1 \ MPC8313ERDB_33 \ MPC8313ERDB_NAND_66 \ MPC8315ERDB \ diff --git a/Makefile b/Makefile index 5cc950dea..685c8ae43 100644 --- a/Makefile +++ b/Makefile @@ -2186,6 +2186,9 @@ TASREG_config : unconfig ## MPC83xx Systems ######################################################################### +kmeter1_config: unconfig + @$(MKCONFIG) kmeter1 ppc mpc83xx kmeter1 keymile + MPC8313ERDB_33_config \ MPC8313ERDB_66_config \ MPC8313ERDB_NAND_33_config \ diff --git a/board/keymile/kmeter1/Makefile b/board/keymile/kmeter1/Makefile new file mode 100644 index 000000000..88b79f3f0 --- /dev/null +++ b/board/keymile/kmeter1/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/keymile/kmeter1/config.mk b/board/keymile/kmeter1/config.mk new file mode 100644 index 000000000..20f298bdb --- /dev/null +++ b/board/keymile/kmeter1/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2008 +# Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xF0000000 diff --git a/board/keymile/kmeter1/kmeter1.c b/board/keymile/kmeter1/kmeter1.c new file mode 100644 index 000000000..f9a59a644 --- /dev/null +++ b/board/keymile/kmeter1/kmeter1.c @@ -0,0 +1,153 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* port pin dir open_drain assign */ + + /* MDIO */ + {0, 1, 3, 0, 2}, /* MDIO */ + {0, 2, 1, 0, 1}, /* MDC */ + + /* UCC4 - UEC */ + {1, 14, 1, 0, 1}, /* TxD0 */ + {1, 15, 1, 0, 1}, /* TxD1 */ + {1, 20, 2, 0, 1}, /* RxD0 */ + {1, 21, 2, 0, 1}, /* RxD1 */ + {1, 18, 1, 0, 1}, /* TX_EN */ + {1, 26, 2, 0, 1}, /* RX_DV */ + {1, 27, 2, 0, 1}, /* RX_ER */ + {1, 24, 2, 0, 1}, /* COL */ + {1, 25, 2, 0, 1}, /* CRS */ + {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */ + {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */ + + /* DUART - UART2 */ + {5, 0, 1, 0, 2}, /* UART2_SOUT */ + {5, 2, 1, 0, 1}, /* UART2_RTS */ + {5, 3, 2, 0, 2}, /* UART2_SIN */ + {5, 1, 2, 0, 3}, /* UART2_CTS */ + + /* END of table */ + {0, 0, 0, 0, QE_IOP_TAB_END}, +}; + +int board_early_init_r (void) +{ + void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8); + u32 val; + + /* + * Because of errata in the UCCs, we have to write to the reserved + * registers to slow the clocks down. + */ + val = in_be32 (reg); + /* UCC1 */ + val |= 0x00003000; + /* UCC2 */ + val |= 0x0c000000; + out_be32 (reg, val); + /* enable the PHY on the PIGGY */ + setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01); + + return 0; +} + +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CONFIG_SYS_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { + if (ddr_size & 1) + return -1; + } + + im->sysconf.ddrlaw[0].ar = + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); + + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; + udelay (200); + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + return msize; +} + +phys_size_t initdram (int board_type) +{ +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) + extern void ddr_enable_ecc (unsigned int dram_size); +#endif + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + msize = fixed_sdram (); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) + /* + * Initialize DDR ECC byte + */ + ddr_enable_ecc (msize * 1024 * 1024); +#endif + + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + +int checkboard (void) +{ + puts ("Board: Keymile kmeter1\n"); + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup (void *blob, bd_t *bd) +{ + ft_cpu_setup (blob, bd); +} +#endif diff --git a/doc/README.kmeter1 b/doc/README.kmeter1 new file mode 100644 index 000000000..44ebb7a78 --- /dev/null +++ b/doc/README.kmeter1 @@ -0,0 +1,91 @@ +Keymile kmeter1 Board +----------------------------------------- +1. Alternative Boot EEPROM + + Upon the kmeter1 startup the I2C_1 controller is used to fetch the boot + configuration from a serial EEPROM. During the development and debugging + phase it might be helpful to apply an alternative boot configuration in + a simple way. Therefore it is an alternative boot eeprom on the PIGGY, + which can be activated by setting the "ST" jumper on the PIGGY board. + +2. Memory Map + + BaseAddr PortSz Size Device + ----------- ------ ----- ------ + 0x0000_0000 64 bit 256MB DDR + 0x8000_0000 8 bit 256KB GPIO/PIGGY on CS1 + 0xa000_0000 8 bit 256MB PAXE on CS3 + 0xe000_0000 2MB Int Mem Reg Space + 0xf000_0000 16 bit 256MB FLASH on CS0 + + + DDR-SDRAM: + The current realization is made with four 16-bits memory devices. + Mounting options have been foreseen for device architectures from + 4Mx16 to 512Mx16. The kmeter1 is equipped with four 32Mx16 devices + thus resulting in a total capacity of 256MBytes. + +3. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + make kmeter1_config + make + +4. Downloading and Flashing Images + +4.0 Download over serial line using Kermit: + + loadb + [Drop to kermit: + ^\c + send + c + ] + + + Or via tftp: + + tftp 10000 u-boot.bin + => run load + Using FSL UEC0 device + TFTP from server 192.168.1.1; our IP address is 192.168.205.4 + Filename '/tftpboot/kmeter1/u-boot.bin'. + Load address: 0x200000 + Loading: ############## + done + Bytes transferred = 204204 (31dac hex) + => + +4.1 Reflash U-boot Image using U-boot + + => run update + ..... done + Un-Protected 5 sectors + + ..... done + Erased 5 sectors + Copy to Flash... done + ..... done + Protected 5 sectors + Total of 204204 bytes were the same + Saving Environment to Flash... + . done + Un-Protected 1 sectors + . done + Un-Protected 1 sectors + Erasing Flash... + . done + Erased 1 sectors + Writing to Flash... done + . done + Protected 1 sectors + . done + Protected 1 sectors + => + +5. Notes + 1) The console baudrate for kmeter1 is 115200bps. diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h new file mode 100644 index 000000000..e105c3bd2 --- /dev/null +++ b/include/configs/kmeter1.h @@ -0,0 +1,523 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ +#define CONFIG_KMETER1 1 /* KMETER1 board specific */ + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_CSB_TO_CLKIN_4X1 | \ + HRCWL_CORE_TO_CSB_2X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X6 ) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_NORMAL | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LDP_CLEAR ) + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x00000006 +#define CONFIG_SYS_SICRL 0x00000000 + +#define CONFIG_BOARD_EARLY_INIT_R + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +#undef CONFIG_DDR_ECC + +/* + * DDRCDR - DDR Control Driver Register + */ + +#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS) + +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_SREN) +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x100 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x406 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_MODE 0x04440242 +#define CONFIG_SYS_DDR_MODE2 0x00800000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_40) | \ + ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \ + ( 1 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + ( 2 << TIMING_CFG1_WRREC_SHIFT) | \ + ( 2 << TIMING_CFG1_REFREC_SHIFT) | \ + ( 2 << TIMING_CFG1_ACTTORW_SHIFT) | \ + ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + ( 2 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((5 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (4 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +/* + * Memory test + */ +#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */ +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x00F00000 + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 +#define CONFIG_SYS_FLASH_BASE_1 0xF2000000 +#define CONFIG_SYS_PIGGY_BASE 0x80000000 +#define CONFIG_SYS_PAXE_BASE 0xA0000000 +#define CONFIG_SYS_PAXE_SIZE 256 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 256KB GPIO/PIGGY + * 3 Local GPCM 8 bit 256MB PAXE + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */ + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 } + +#undef CONFIG_SYS_FLASH_CHECKSUM + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWAR1_PRELIM 0x80000011 /* 256KB window size */ + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \ + (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (0xfffc0000 | /* 256KB */ \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +/* + * PAXE on the local bus CS3 + */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001b /* 256MB window size */ + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \ + (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ + BR_V) +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200,} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#undef CONFIG_PCI /* No PCI */ + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "FSL UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_RAMBOOT */ +#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ +#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_RAMBOOT */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#endif + +#if defined(CFG_RAMBOOT) +#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_LOADS +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +#define CONFIG_SYS_HZ 1000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_256K | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* PAXE: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256K | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else /* CONFIG_PCI */ +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U +#endif /* CONFIG_PCI */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=ttyS0,${baudrate}\0" \ + "fdt_addr=f0080000\0" \ + "kernel_addr=f00a0000\0" \ + "ramdisk_addr=f03a0000\0" \ + "kernel_addr_r=400000\0" \ + "fdt_addr_r=800000\0" \ + "ramdisk_addr_r=810000\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${boot_file}; " \ + "tftp ${fdt_addr_r} ${fdt_file}; " \ + "run nfsargs addip addtty;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "fdt_file=/tftpboot/kmeter1/kmeter1.dtb\0" \ + "boot_file=/tftpboot/kmeter1/uImage\0" \ + "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0" \ + "u-boot=/tftpboot/kmeter1/u-boot.bin\0" \ + "loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \ + "load=tftp $loadaddr ${u-boot}\0" \ + "update=protect off " MK_STR(TEXT_BASE) " +$filesize;" \ + "erase " MK_STR(TEXT_BASE) " +$filesize;" \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \ + "protect on " MK_STR(TEXT_BASE) " +$filesize;" \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \ + "setenv filesize;saveenv\0" \ + "upd=run load update\0" \ + "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0" \ + "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \ + "loadkernel=tftp ${kernel_addr_r} ${boot_file}\0" \ + "unlock=yes\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#endif /* __CONFIG_H */ From 210c8c00aad3328145204adab434bb7d70b06b75 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 21 Nov 2008 08:29:40 +0100 Subject: [PATCH 166/188] powerpc: keymile: Add a check for the PIGGY debug board Check the presence of the PIGGY on the keymile boards mgcoge, mgsuvd and kmeter1. If the PIGGY is not present, dont register this Ethernet device. Signed-off-by: Heiko Schocher Acked-by: Ben Warren --- board/keymile/common/common.c | 23 +++++++++++++++++++++-- board/keymile/common/common.h | 20 ++++++++++++++++++++ board/keymile/kmeter1/Makefile | 6 ++++-- board/keymile/kmeter1/kmeter1.c | 7 ++++++- board/keymile/mgcoge/mgcoge.c | 10 +++++++--- board/keymile/mgsuvd/mgsuvd.c | 8 ++++++-- include/configs/kmeter1.h | 9 +++++++++ include/configs/mgcoge.h | 10 ++++++++++ include/configs/mgsuvd.h | 9 +++++++++ 9 files changed, 92 insertions(+), 10 deletions(-) create mode 100644 board/keymile/common/common.h diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index a4cf24cf7..133895081 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -22,10 +22,14 @@ */ #include +#if defined(CONFIG_MGCOGE) #include +#endif #include #include #include +#include +#include #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) #include @@ -33,8 +37,6 @@ #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) #include -#endif -#include extern int i2c_soft_read_pin (void); @@ -495,6 +497,7 @@ void i2c_init_board(void) #endif } #endif +#endif #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) int fdt_set_node_and_value (void *blob, @@ -521,3 +524,19 @@ int fdt_set_node_and_value (void *blob, return ret; } #endif + +int ethernet_present (void) +{ + return (in_8((u8 *)CONFIG_SYS_PIGGY_BASE + CONFIG_SYS_SLOT_ID_OFF) & 0x80); +} + +int board_eth_init (bd_t *bis) +{ +#ifdef CONFIG_KEYMILE_HDLC_ENET + (void)keymile_hdlc_enet_initialize (bis); +#endif + if (ethernet_present ()) { + return -1; + } + return 0; +} diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h new file mode 100644 index 000000000..d3d681424 --- /dev/null +++ b/board/keymile/common/common.h @@ -0,0 +1,20 @@ +/* + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __KEYMILE_COMMON_H +#define __KEYMILE_COMMON_H + +int ethernet_present (void); +int ivm_read_eeprom (void); + +#ifdef CONFIG_KEYMILE_HDLC_ENET +int keymile_hdlc_enet_initialize (bd_t *bis); +#endif +#endif /* __KEYMILE_COMMON_H */ diff --git a/board/keymile/kmeter1/Makefile b/board/keymile/kmeter1/Makefile index 88b79f3f0..12a1518ff 100644 --- a/board/keymile/kmeter1/Makefile +++ b/board/keymile/kmeter1/Makefile @@ -22,12 +22,14 @@ # include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif LIB = $(obj)lib$(BOARD).a -COBJS-y += $(BOARD).o +COBJS += $(BOARD).o ../common/common.o -COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/keymile/kmeter1/kmeter1.c b/board/keymile/kmeter1/kmeter1.c index f9a59a644..f04a57a9c 100644 --- a/board/keymile/kmeter1/kmeter1.c +++ b/board/keymile/kmeter1/kmeter1.c @@ -27,6 +27,8 @@ #include #include +#include "../common/common.h" + const qe_iop_conf_t qe_iop_conf_tab[] = { /* port pin dir open_drain assign */ @@ -141,7 +143,10 @@ phys_size_t initdram (int board_type) int checkboard (void) { - puts ("Board: Keymile kmeter1\n"); + puts ("Board: Keymile kmeter1"); + if (ethernet_present ()) + puts (" with PIGGY."); + puts ("\n"); return 0; } diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c index 3683417f5..5c5073964 100644 --- a/board/keymile/mgcoge/mgcoge.c +++ b/board/keymile/mgcoge/mgcoge.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) @@ -35,7 +36,8 @@ #include #endif -extern int ivm_read_eeprom (void); +#include "../common/common.h" + /* * I/O Port configuration table * @@ -285,8 +287,10 @@ phys_size_t initdram (int board_type) int checkboard(void) { - puts ("Board: mgcoge\n"); - + puts ("Board: Keymile mgcoge"); + if (ethernet_present ()) + puts (" with PIGGY."); + puts ("\n"); return 0; } diff --git a/board/keymile/mgsuvd/mgsuvd.c b/board/keymile/mgsuvd/mgsuvd.c index 3726acf4a..02baf622e 100644 --- a/board/keymile/mgsuvd/mgsuvd.c +++ b/board/keymile/mgsuvd/mgsuvd.c @@ -22,13 +22,14 @@ */ #include #include +#include #include #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) #include #endif -extern int ivm_read_eeprom (void); +#include "../common/common.h" DECLARE_GLOBAL_DATA_PTR; @@ -60,7 +61,10 @@ const uint sdram_table[] = int checkboard (void) { - puts ("Board: Keymile mgsuvd\n"); + puts ("Board: Keymile mgsuvd"); + if (ethernet_present ()) + puts (" with PIGGY."); + puts ("\n"); return (0); } diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index e105c3bd2..7a63a4189 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -313,6 +313,15 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * How to get access to the slot ID. Put this here to make it easy + * to modify in a centralized location. This is used in the HDLC + * driver to set the MAC. +*/ +#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE +#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ +#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ + /* * BOOTP options */ diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index dc9b311d4..31428ea09 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -400,4 +400,14 @@ #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" +/* + * How to get access to the slot ID. Put this here to make it easy + * to modify in a centralized location. This is used in the HDLC + * driver to set the MAC. +*/ +#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE +#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ +#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ + + #endif /* __CONFIG_H */ diff --git a/include/configs/mgsuvd.h b/include/configs/mgsuvd.h index fca2e5513..b862130ae 100644 --- a/include/configs/mgsuvd.h +++ b/include/configs/mgsuvd.h @@ -211,6 +211,15 @@ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +/* + * How to get access to the slot ID. Put this here to make it easy + * to modify in a centralized location. This is used in the HDLC + * driver to set the MAC. +*/ +#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE +#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ +#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ + /*----------------------------------------------------------------------- * Cache Configuration */ From 1e8f4e78ca393b3d8e86bd8055758dd465d9113f Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 20 Nov 2008 09:59:09 +0100 Subject: [PATCH 167/188] powerpc, keymile boards: extract identical config options This patch extracts the identical config options for the keymile boards mgcoge, mgsuvd and kmeter1 in a new common config file keymile-common.h. Signed-off-by: Heiko Schocher --- include/configs/keymile-common.h | 113 +++++++++++++++++++++++++++++++ include/configs/kmeter1.h | 81 +--------------------- include/configs/mgcoge.h | 61 +---------------- include/configs/mgsuvd.h | 81 +--------------------- 4 files changed, 120 insertions(+), 216 deletions(-) create mode 100644 include/configs/keymile-common.h diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h new file mode 100644 index 000000000..d70bc4808 --- /dev/null +++ b/include/configs/keymile-common.h @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_KEYMILE_H +#define __CONFIG_KEYMILE_H + +/* Do boardspecific init for all boards */ +#define CONFIG_BOARD_EARLY_INIT_R 1 + +#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD) +#define CONFIG_BOOTCOUNT_LIMIT +#endif + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + +/* should go away, if kmeter I2C support is enabled */ +#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD) +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#endif + +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ + +#define CONFIG_BOOTCOMMAND "run net_nfs" +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +/* should go away, if kmeter I2C support is enabled */ +#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD) +#define CONFIG_HUSH_INIT_VAR 1 +#endif + +#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */ +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ + +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * How to get access to the slot ID. Put this here to make it easy + * to modify in a centralized location. This is used in the HDLC + * driver to set the MAC. +*/ +#define CONFIG_CHECK_ETHERNET_PRESENT 1 +#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE +#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ +#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +#endif /* __CONFIG_KEYMILE_H */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 7a63a4189..25b1c172e 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -29,6 +29,9 @@ #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ #define CONFIG_KMETER1 1 /* KMETER1 board specific */ +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" + /* * System Clock Setup */ @@ -60,8 +63,6 @@ #define CONFIG_SYS_SICRH 0x00000006 #define CONFIG_SYS_SICRL 0x00000000 -#define CONFIG_BOARD_EARLY_INIT_R - /* * IMMR new address */ @@ -134,13 +135,6 @@ #define CONFIG_SYS_DDR_TIMING_3 0x00000000 -/* - * Memory test - */ -#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00F00000 - /* * The reserved memory */ @@ -249,9 +243,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200,} - #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) @@ -269,7 +260,6 @@ #ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI 1 #endif - /* * QE UEC ethernet configuration */ @@ -310,37 +300,6 @@ #define CONFIG_ENV_SIZE 0x2000 #endif /* CFG_RAMBOOT */ -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * How to get access to the slot ID. Put this here to make it easy - * to modify in a centralized location. This is used in the HDLC - * driver to set the MAC. -*/ -#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE -#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ -#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING - #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI #endif @@ -350,28 +309,6 @@ #undef CONFIG_CMD_LOADS #endif -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#define CONFIG_SYS_HZ 1000 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is @@ -464,11 +401,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - /* * Environment Configuration */ @@ -478,11 +410,6 @@ #define CONFIG_HAS_ETH0 #endif -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "rootpath=/opt/eldk/ppc_82xx\0" \ @@ -527,6 +454,4 @@ "unlock=yes\0" \ "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - #endif /* __CONFIG_H */ diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index 31428ea09..233bee002 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -35,8 +35,8 @@ #define CONFIG_CPM2 1 /* Has a CPM2 */ -/* Do boardspecific init */ -#define CONFIG_BOARD_EARLY_INIT_R 1 +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" /* * Select serial console configuration @@ -74,23 +74,6 @@ #define CONFIG_8260_CLKIN 66000000 /* in Hz */ #endif -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTCOUNT_LIMIT - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DTT -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING - /* * Default environment settings */ @@ -124,36 +107,6 @@ "run ramargs addip; " \ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ "" -#define CONFIG_BOOTCOMMAND "run net_nfs" -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_HUSH_INIT_VAR 1 -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_FLASH_BASE 0xFE000000 @@ -400,14 +353,4 @@ #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" -/* - * How to get access to the slot ID. Put this here to make it easy - * to modify in a centralized location. This is used in the HDLC - * driver to set the MAC. -*/ -#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE -#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ -#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ - - #endif /* __CONFIG_H */ diff --git a/include/configs/mgsuvd.h b/include/configs/mgsuvd.h index b862130ae..f53b6d382 100644 --- a/include/configs/mgsuvd.h +++ b/include/configs/mgsuvd.h @@ -36,8 +36,8 @@ #define CONFIG_MPC866 1 /* This is a MPC866 CPU */ #define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */ -/* Do boardspecific init */ -#define CONFIG_BOARD_EARLY_INIT_R 1 +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" #define CONFIG_8xx_GCLK_FREQ 66000000 @@ -45,22 +45,13 @@ #define CONFIG_SYS_SMC_DPMEM_OFFSET 0x1fc0 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT #define CONFIG_SYS_CPM_BOOTCOUNT_ADDR 0x1eb0 /* In case of SMC relocation, the * default value is not working */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - #define CONFIG_PREBOOT "echo;" \ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ "echo" -#undef CONFIG_BOOTARGS - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \ @@ -88,70 +79,11 @@ "cp.b 200000 f0000000 ${filesize};" \ "protect on f0000000 +${filesize}\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ #define CONFIG_TIMESTAMP /* but print image timestmps */ -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_HUSH_INIT_VAR 1 -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) @@ -211,15 +143,6 @@ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -/* - * How to get access to the slot ID. Put this here to make it easy - * to modify in a centralized location. This is used in the HDLC - * driver to set the MAC. -*/ -#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE -#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ -#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ - /*----------------------------------------------------------------------- * Cache Configuration */ From 0c0ccf401ee03a5008fc2c19b05a662bce1a1086 Mon Sep 17 00:00:00 2001 From: Gary Jennejohn Date: Thu, 20 Nov 2008 11:37:26 +0100 Subject: [PATCH 168/188] POWERPC 82xx: add the SCC as an HDLC controller Right now this is only used by keymile. Signed-off-by: Gary Jennejohn --- include/asm-ppc/cpm_8260.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/include/asm-ppc/cpm_8260.h b/include/asm-ppc/cpm_8260.h index 7e06940c9..8302404ab 100644 --- a/include/asm-ppc/cpm_8260.h +++ b/include/asm-ppc/cpm_8260.h @@ -546,6 +546,34 @@ typedef struct scc_trans { #define BD_SCC_TX_LAST ((ushort)0x0800) +/* SCC as HDLC controller - taken from commproc.h + */ +typedef struct scc_hdlc { + sccp_t sh_genscc; + /* + * HDLC specific parameter RAM + */ + uchar res[4]; /* reserved */ + ulong sh_cmask; /* CRC constant */ + ulong sh_cpres; /* CRC preset */ + ushort sh_disfc; /* discarded frame counter */ + ushort sh_crcec; /* CRC error counter */ + ushort sh_abtsc; /* abort sequence counter */ + ushort sh_nmarc; /* nonmatching address rx cnt */ + ushort sh_retrc; /* frame retransmission cnt */ + ushort sh_mflr; /* maximum frame length reg */ + ushort sh_maxcnt; /* maximum length counter */ + ushort sh_rfthr; /* received frames threshold */ + ushort sh_rfcnt; /* received frames count */ + ushort sh_hmask; /* user defined frm addr mask */ + ushort sh_haddr1; /* user defined frm address 1 */ + ushort sh_haddr2; /* user defined frm address 2 */ + ushort sh_haddr3; /* user defined frm address 3 */ + ushort sh_haddr4; /* user defined frm address 4 */ + ushort tmp; /* temp */ + ushort tmp_mb; /* temp */ +} scc_hdlc_t; + /* How about some FCCs..... */ #define FCC_GFMR_DIAG_NORM ((uint)0x00000000) From c620c01e96814558470698ed5cab1bf2f504d1b5 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 7 Dec 2008 10:28:57 +1100 Subject: [PATCH 169/188] Added initial eNET board support Signed-off-by: Graeme Russ --- MAKEALL | 1 + Makefile | 3 + board/eNET/Makefile | 57 +++++++++ board/eNET/config.mk | 24 ++++ board/eNET/eNET.c | 167 +++++++++++++++++++++++++ board/eNET/eNET_start.S | 50 ++++++++ board/eNET/eNET_start16.S | 90 ++++++++++++++ board/eNET/hardware.h | 35 ++++++ board/eNET/u-boot.lds | 90 ++++++++++++++ include/configs/eNET.h | 249 ++++++++++++++++++++++++++++++++++++++ 10 files changed, 766 insertions(+) create mode 100644 board/eNET/Makefile create mode 100644 board/eNET/config.mk create mode 100644 board/eNET/eNET.c create mode 100644 board/eNET/eNET_start.S create mode 100644 board/eNET/eNET_start16.S create mode 100644 board/eNET/hardware.h create mode 100644 board/eNET/u-boot.lds create mode 100644 include/configs/eNET.h diff --git a/MAKEALL b/MAKEALL index 485fb884a..0733dfc74 100755 --- a/MAKEALL +++ b/MAKEALL @@ -659,6 +659,7 @@ LIST_mips_el=" \ LIST_I486=" \ sc520_cdp \ + sc520_eNET \ sc520_spunk \ sc520_spunk_rel \ " diff --git a/Makefile b/Makefile index 685c8ae43..eeb913cb5 100644 --- a/Makefile +++ b/Makefile @@ -2996,6 +2996,9 @@ smdk6400_config : unconfig sc520_cdp_config : unconfig @$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp +eNET_config : unconfig + @$(MKCONFIG) $(@:_config=) i386 i386 eNET + sc520_spunk_config : unconfig @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk diff --git a/board/eNET/Makefile b/board/eNET/Makefile new file mode 100644 index 000000000..4813b4b53 --- /dev/null +++ b/board/eNET/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2008 +# Graeme Russ, graeme.russ@gmail.com. +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := eNET.o +SOBJS := eNET_start16.o eNET_start.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/eNET/config.mk b/board/eNET/config.mk new file mode 100644 index 000000000..a76384130 --- /dev/null +++ b/board/eNET/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x38040000 diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c new file mode 100644 index 000000000..57dd6359e --- /dev/null +++ b/board/eNET/eNET.c @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_HW_WATCHDOG +#include +#endif + +#include "hardware.h" + +DECLARE_GLOBAL_DATA_PTR; + +#undef SC520_CDP_DEBUG + +#ifdef SC520_CDP_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; + +void init_sc520_enet (void) +{ + /* Set CPU Speed to 100MHz */ + write_mmcr_byte(SC520_CPUCTL, 1); + gd->cpu_clk = 100000000; + + /* wait at least one millisecond */ + asm("movl $0x2000,%%ecx\n" + "wait_loop: pushl %%ecx\n" + "popl %%ecx\n" + "loop wait_loop\n": : : "ecx"); + + /* turn on the SDRAM write buffer */ + write_mmcr_byte(SC520_DBCTL, 0x11); + + /* turn on the cache and disable write through */ + asm("movl %%cr0, %%eax\n" + "andl $0x9fffffff, %%eax\n" + "movl %%eax, %%cr0\n" : : : "eax"); +} + +/* + * Miscellaneous platform dependent initializations + */ +int board_init(void) +{ + init_sc520_enet(); + + write_mmcr_byte(SC520_GPCSRT, 0x01); /* GP Chip Select Recovery Time */ + write_mmcr_byte(SC520_GPCSPW, 0x07); /* GP Chip Select Pulse Width */ + write_mmcr_byte(SC520_GPCSOFF, 0x00); /* GP Chip Select Offset */ + write_mmcr_byte(SC520_GPRDW, 0x05); /* GP Read pulse width */ + write_mmcr_byte(SC520_GPRDOFF, 0x01); /* GP Read offset */ + write_mmcr_byte(SC520_GPWRW, 0x05); /* GP Write pulse width */ + write_mmcr_byte(SC520_GPWROFF, 0x01); /* GP Write offset */ + + write_mmcr_word(SC520_PIODATA15_0, 0x0630); /* PIO15_PIO0 Data */ + write_mmcr_word(SC520_PIODATA31_16, 0x2000); /* PIO31_PIO16 Data */ + write_mmcr_word(SC520_PIODIR31_16, 0x2000); /* GPIO Direction */ + write_mmcr_word(SC520_PIODIR15_0, 0x87b5); /* GPIO Direction */ + write_mmcr_word(SC520_PIOPFS31_16, 0x0dfe); /* GPIO pin function 31-16 reg */ + write_mmcr_word(SC520_PIOPFS15_0, 0x200a); /* GPIO pin function 15-0 reg */ + write_mmcr_byte(SC520_CSPFS, 0x00f8); /* Chip Select Pin Function Select */ + + write_mmcr_long(SC520_PAR2, 0x200713f8); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */ + write_mmcr_long(SC520_PAR3, 0x2c0712f8); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */ + write_mmcr_long(SC520_PAR4, 0x300711f8); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */ + write_mmcr_long(SC520_PAR5, 0x340710f8); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */ + write_mmcr_long(SC520_PAR6, 0xe3ffc000); /* SDRAM (0x00000000, 128MB) */ + write_mmcr_long(SC520_PAR7, 0xaa3fd000); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */ + write_mmcr_long(SC520_PAR8, 0xca3fd100); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */ + write_mmcr_long(SC520_PAR9, 0x4203d900); /* SRAM (GPCS0, 0x19000000, 1MB) */ + write_mmcr_long(SC520_PAR10, 0x4e03d910); /* SRAM (GPCS3, 0x19100000, 1MB) */ + write_mmcr_long(SC520_PAR11, 0x50018100); /* DP-RAM (GPCS4, 0x18100000, 4kB) */ + write_mmcr_long(SC520_PAR12, 0x54020000); /* CFLASH1 (0x200000000, 4kB) */ + write_mmcr_long(SC520_PAR13, 0x5c020001); /* CFLASH2 (0x200010000, 4kB) */ +/* write_mmcr_long(SC520_PAR14, 0x8bfff800); */ /* BOOTCS at 0x18000000 */ +/* write_mmcr_long(SC520_PAR15, 0x38201000); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */ + + /* Disable Watchdog */ + write_mmcr_word(0x0cb0, 0x3333); + write_mmcr_word(0x0cb0, 0xcccc); + write_mmcr_word(0x0cb0, 0x0000); + + /* Chip Select Configuration */ + write_mmcr_word(SC520_BOOTCSCTL, 0x0033); + write_mmcr_word(SC520_ROMCS1CTL, 0x0615); + write_mmcr_word(SC520_ROMCS2CTL, 0x0615); + + write_mmcr_byte(SC520_ADDDECCTL, 0x02); + write_mmcr_byte(SC520_UART1CTL, 0x07); + write_mmcr_byte(SC520_SYSARBCTL,0x06); + write_mmcr_word(SC520_SYSARBMENB, 0x0003); + + /* Crystal is 33.000MHz */ + gd->bus_clk = 33000000; + + return 0; +} + +int dram_init(void) +{ + init_sc520_dram(); + return 0; +} + +void show_boot_progress(int val) +{ + uchar led_mask; + + led_mask = 0x00; + + if (val < 0) + led_mask |= LED_ERR_BITMASK; + + led_mask |= (uchar)(val & 0x001f); + outb(led_mask, LED_LATCH_ADDRESS); +} + + +int last_stage_init(void) +{ + int minor; + int major; + + major = minor = 0; + + printf("Serck Controls eNET\n"); + + return 0; +} + +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = FLASH_CFI_8BIT; + info->chipwidth = FLASH_CFI_BY8; + info->interface = FLASH_CFI_X8; + return 1; + } else + return 0; +} diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S new file mode 100644 index 000000000..1b07d622f --- /dev/null +++ b/board/eNET/eNET_start.S @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "hardware.h" + +/* board early intialization */ +.globl early_board_init +early_board_init: + /* No 32-bit board specific initialisation */ + jmp *%ebp /* return to caller */ + +.globl show_boot_progress_asm +show_boot_progress_asm: + + movb %al, %dl /* Create Working Copy */ + andb $0x80, %dl /* Mask in only Error bit */ + shrb $0x02, %dl /* Shift Error bit to Error LED */ + andb $0x0f, %al /* Mask out 'Error' bit */ + orb %dl, %al /* Mask in ERR LED */ + movw $LED_LATCH_ADDRESS, %dx + outb %al, %dx + jmp *%ebp /* return to caller */ + +.globl cpu_halt_asm +cpu_halt_asm: + movb $0x0f, %al + movw $LED_LATCH_ADDRESS, %dx + outb %al, %dx + hlt + jmp cpu_halt_asm diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S new file mode 100644 index 000000000..48e4d83a1 --- /dev/null +++ b/board/eNET/eNET_start16.S @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * 16bit initialization code. + * This code have to map the area of the boot flash + * that is used by U-boot to its final destination. + */ + +/* #include */ + +#include "hardware.h" + +.text +.section .start16, "ax" +.code16 +.globl board_init16 +board_init16: + /* Alias MMCR to 0xdf000 */ + movw $0xfffc, %dx + movl $0x800df0cb, %eax + outl %eax, %dx + + /* Set ds to point to MMCR alias */ + movw $0xdf00, %ax + movw %ax, %ds + + /* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */ + movl $0x00c0, %edi /* SC520_PAR14 */ + movl $0x8bfff800, %eax /* TODO: Check this */ + movl %eax, (%di) + + /* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */ + movl $0x00c4, %edi /* SC520_PAR15 */ + movl $0x38201000, %eax + movl %eax, (%di) + + /* Disable SDRAM write buffer */ + movw $0x0040, %di /* SC520_DBCTL */ + xorw %ax, %ax + movb %al, (%di) + + /* Disabe MMCR alias */ + movw $0xfffc, %dx + movl $0x000000cb, %eax + outl %eax, %dx + + /* the return address is stored in bp */ + jmp *%bp + +.section .bios, "ax" +.code16 +.globl realmode_reset +realmode_reset: + /* Alias MMCR to 0xdf000 */ + movw $0xfffc, %dx + movl $0x800df0cb, %eax + outl %eax, %dx + + /* Set ds to point to MMCR alias */ + movw $0xdf00, %ax + movw %ax, %ds + + /* issue software reset thorugh MMCR */ + movl $0xd72, %edi + movb $0x01, %al + movb %al, (%di) + +1: hlt + jmp 1 diff --git a/board/eNET/hardware.h b/board/eNET/hardware.h new file mode 100644 index 000000000..42474a62f --- /dev/null +++ b/board/eNET/hardware.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef HARDWARE_H_ +#define HARDWARE_H_ + +#define LED_LATCH_ADDRESS 0x1002 +#define LED_RUN_BITMASK 0x01 +#define LED_1_BITMASK 0x02 +#define LED_2_BITMASK 0x04 +#define LED_RX_BITMASK 0x08 +#define LED_TX_BITMASK 0x10 +#define LED_ERR_BITMASK 0x20 + +#endif /* HARDWARE_H_ */ diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds new file mode 100644 index 000000000..f3d28ef94 --- /dev/null +++ b/board/eNET/u-boot.lds @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) +ENTRY(_start) + +SECTIONS +{ + . = 0x38040000; /* Location of bootcode in flash */ + .text : { *(.text); } + + . = ALIGN(4); + .rodata : { *(.rodata) *(.rodata.str1.1) *(.rodata.str1.32) } + + _i386boot_text_size = SIZEOF(.text) + SIZEOF(.rodata); + + . = 0x03FF0000; /* Ram data segment to use */ + _i386boot_romdata_dest = ABSOLUTE(.); + .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) } + _i386boot_romdata_start = LOADADDR(.data); + + . = ALIGN(4); + .got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + _i386boot_cmd_start = LOADADDR(.u_boot_cmd); + + _i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got) + SIZEOF(.u_boot_cmd); + + . = ALIGN(4); + _i386boot_bss_start = ABSOLUTE(.); + .bss (NOLOAD) : { *(.bss) } + _i386boot_bss_size = SIZEOF(.bss); + + /* 16bit realmode trampoline code */ + .realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) + SIZEOF(.u_boot_cmd)) { *(.realmode) } + + _i386boot_realmode = LOADADDR(.realmode); + _i386boot_realmode_size = SIZEOF(.realmode); + + /* 16bit BIOS emulation code (just enough to boot Linux) */ + .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) } + + _i386boot_bios = LOADADDR(.bios); + _i386boot_bios_size = SIZEOF(.bios); + + /* The load addresses below assumes that the flash + * will be mapped so that 0x387f0000 == 0xffff0000 + * at reset time + * + * The fe00 and ff00 offsets of the start32 and start16 + * segments are arbitrary, the just have to be mapped + * at reset and the code have to fit. + * The fff0 offset of reset is important, however. + */ + + . = 0xfffffe00; + .start32 : AT (0x3807fe00) { *(.start32); } + + . = 0xf800; + .start16 : AT (0x3807f800) { *(.start16); } + + . = 0xfff0; + .reset : AT (0x3807fff0) { *(.reset); } + _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) ); +} diff --git a/include/configs/eNET.h b/include/configs/eNET.h new file mode 100644 index 000000000..87d2908a3 --- /dev/null +++ b/include/configs/eNET.h @@ -0,0 +1,249 @@ +/* + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Stuff still to be dealt with - + */ +#define CONFIG_RTC_MC146818 + +/* + * High Level Configuration Options + * (easy to change) + */ +#define DEBUG_PARSER + +#define CONFIG_X86 1 /* Intel X86 CPU */ +#define CONFIG_SC520 1 /* AMD SC520 */ +#define CONFIG_SC520_SSI +#define CONFIG_SHOW_BOOT_PROGRESS 1 +#define CONFIG_LAST_STAGE_INIT 1 + +/* + * If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the + * bottom (processor) board MUST be removed! + */ +#undef CONFIG_WATCHDOG +#undef CONFIG_HW_WATCHDOG + + /*----------------------------------------------------------------------- + * Video Configuration + */ +#undef CONFIG_VIDEO /* No Video Hardware */ +#undef CONFIG_CFB_CONSOLE + +/* + * Size of malloc() pool + */ +#define CONFIG_MALLOC_SIZE (CONFIG_SYS_ENV_SIZE + 128*1024) + +#define CONFIG_BAUDRATE 9600 + +/*----------------------------------------------------------------------- + * Command line configuration. + */ +#include + +#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */ +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BOOTD /* bootd */ +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_ECHO /* echo arguments */ +#define CONFIG_CMD_ENV /* saveenv */ +#define CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#define CONFIG_CMD_FPGA /* FPGA configuration Support */ +#define CONFIG_CMD_IMI /* iminfo */ +#define CONFIG_CMD_IMLS /* List all found images */ +#define CONFIG_CMD_ITEST /* Integer (and string) test */ +#define CONFIG_CMD_LOADB /* loadb */ +#define CONFIG_CMD_LOADS /* loads */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#undef CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ +#define CONFIG_CMD_XIMG /* Load part of Multi Image */ +#undef CONFIG_CMD_IRQ /* IRQ Information */ + +#define CONFIG_BOOTDELAY 15 +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" +/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + \ + 16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ + +#define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */ + + /* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * SDRAM Configuration + */ +#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18 +#define CONFIG_NR_DRAM_BANKS 4 + +/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/ +#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY +#undef CONFIG_SYS_SDRAM_REFRESH_RATE +#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY +#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T +#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T + +/*----------------------------------------------------------------------- + * CPU Features + */ +#define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ +#define CONFIG_SYS_RESET_GENERIC /* use triple-fault to reset cpu */ +#undef CONFIG_SYS_RESET_SC520 /* use SC520 MMCR's to reset cpu */ +#define CONFIG_SYS_TIMER_SC520 /* use SC520 swtimers */ +#undef CONFIG_SYS_TIMER_GENERIC /* use the i8254 PIT timers */ +#undef CONFIG_SYS_TIMER_TSC /* use the Pentium TSC timers */ +#define CONFIG_SYS_USE_SIO_UART 0 /* prefer the uarts on the SIO to those + * in the SC520 on the CDP */ + +/*----------------------------------------------------------------------- + * Memory organization + */ +#define CONFIG_SYS_STACK_SIZE 0x8000 /* Size of bootloader stack */ +#define CONFIG_SYS_BL_START_FLASH 0x38040000 /* Address of relocated code */ +#define CONFIG_SYS_BL_START_RAM 0x03fd0000 /* Address of relocated code */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */ +#define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */ +#define CONFIG_SYS_FLASH_BASE_2 0x11000000 /* StrataFlash 2 */ + +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + + /*----------------------------------------------------------------------- + * FLASH configuration + */ +#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */ +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */ +#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_FLASH_BASE_1, \ + CONFIG_SYS_FLASH_BASE_2} +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CONFIG_SYS_FLASH_LEGACY_512Kx8 + + /*----------------------------------------------------------------------- + * Environment configuration + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ +#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE_1 + \ + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + + + /*----------------------------------------------------------------------- + * PCI configuration + */ +#undef CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* pci plug-and-play */ +#undef CONFIG_PCI_SCAN_SHOW +#undef CONFIG_SYS_FIRST_PCI_IRQ +#undef CONFIG_SYS_SECOND_PCI_IRQ +#undef CONFIG_SYS_THIRD_PCI_IRQ +#undef CONFIG_SYS_FORTH_PCI_IRQ + +/*----------------------------------------------------------------------- + * Hardware watchdog configuration + */ +#define CONFIG_SYS_WATCHDOG_PIO_BIT 0x8000 +#define CONFIG_SYS_WATCHDIG_PIO_DATA SC520_PIODATA15_0 +#define CONFIG_SYS_WATCHDIG_PIO_CLR SC520_PIOCLR15_0 +#define CONFIG_SYS_WATCHDIG_PIO_SET SC520_PIOSET15_0 + +/*----------------------------------------------------------------------- + * FPGA configuration + */ +#define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT 0x2000 +#define CONFIG_SYS_FPGA_INIT_PIO_BIT 0x4000 +#define CONFIG_SYS_FPGA_DONE_PIO_BIT 0x8000 +#define CONFIG_SYS_FPGA_PIO_DATA SC520_PIODATA31_16 +#define CONFIG_SYS_FPGA_PIO_DIRECTION SC520_PIODIR31_16 +#define CONFIG_SYS_FPGA_PIO_CLR SC520_PIOCLR31_16 +#define CONFIG_SYS_FPGA_PIO_SET SC520_PIOSET31_16 +#define CONFIG_SYS_FPGA_PROGRAM_BIT_DROP_TIME 1 /* milliseconds */ +#define CONFIG_SYS_FPGA_MAX_INIT_TIME 10 /* milliseconds */ +#define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */ +#define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */ + +#ifndef __ASSEMBLER__ +extern unsigned long ip; + +#define PRINTIP asm ("call next_line\n" \ + "next_line:\n" \ + "pop %%eax\n" \ + "movl %%eax, %0\n" \ + :"=r"(ip) \ + : /* No Input Registers */ \ + :"%eax"); \ + printf("IP: 0x%08lx (File: %s, Line: %d)\n", ip, __FILE__, __LINE__); + +#endif +#endif /* __CONFIG_H */ From a3f4c123f569474e80ea012b8db0de46afdb6443 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sat, 24 Jan 2009 01:01:49 +0100 Subject: [PATCH 170/188] Makefile: keep lists sorted. Signed-off-by: Wolfgang Denk --- Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index eeb913cb5..b99252100 100644 --- a/Makefile +++ b/Makefile @@ -2993,12 +2993,12 @@ smdk6400_config : unconfig ######################################################################### ## AMD SC520 CDP ######################################################################### -sc520_cdp_config : unconfig - @$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp - eNET_config : unconfig @$(MKCONFIG) $(@:_config=) i386 i386 eNET +sc520_cdp_config : unconfig + @$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp + sc520_spunk_config : unconfig @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk From 85ffbbd51914925a542d8528be7f072e5ab02157 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 7 Dec 2008 10:28:58 +1100 Subject: [PATCH 171/188] Renamed cpu/i386/reset.S to resetvec.S Brings i386 in line with other CPUs with a reset vector and frees up reset.c for CPU reset functions Signed-off-by: Graeme Russ --- Makefile | 2 +- board/eNET/u-boot.lds | 6 +++--- board/sc520_cdp/u-boot.lds | 6 +++--- board/sc520_spunk/u-boot.lds | 6 +++--- cpu/i386/Makefile | 2 +- cpu/i386/{reset.S => resetvec.S} | 2 +- 6 files changed, 12 insertions(+), 12 deletions(-) rename cpu/i386/{reset.S => resetvec.S} (97%) diff --git a/Makefile b/Makefile index b99252100..b859bcbd0 100644 --- a/Makefile +++ b/Makefile @@ -197,7 +197,7 @@ include $(TOPDIR)/config.mk OBJS = cpu/$(CPU)/start.o ifeq ($(CPU),i386) OBJS += cpu/$(CPU)/start16.o -OBJS += cpu/$(CPU)/reset.o +OBJS += cpu/$(CPU)/resetvec.o endif ifeq ($(CPU),ppc4xx) OBJS += cpu/$(CPU)/resetvec.o diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds index f3d28ef94..671305ac9 100644 --- a/board/eNET/u-boot.lds +++ b/board/eNET/u-boot.lds @@ -75,7 +75,7 @@ SECTIONS * The fe00 and ff00 offsets of the start32 and start16 * segments are arbitrary, the just have to be mapped * at reset and the code have to fit. - * The fff0 offset of reset is important, however. + * The fff0 offset of resetvec is important, however. */ . = 0xfffffe00; @@ -85,6 +85,6 @@ SECTIONS .start16 : AT (0x3807f800) { *(.start16); } . = 0xfff0; - .reset : AT (0x3807fff0) { *(.reset); } - _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) ); + .resetvec : AT (0x3807fff0) { *(.resetvec); } + _i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) ); } diff --git a/board/sc520_cdp/u-boot.lds b/board/sc520_cdp/u-boot.lds index 719ecbaa1..0f5011ae3 100644 --- a/board/sc520_cdp/u-boot.lds +++ b/board/sc520_cdp/u-boot.lds @@ -75,7 +75,7 @@ SECTIONS * The fe00 and ff00 offsets of the start32 and start16 * segments are arbitrary, the just have to be mapped * at reset and the code have to fit. - * The fff0 offset of reset is important, however. + * The fff0 offset of resetvec is important, however. */ @@ -86,6 +86,6 @@ SECTIONS .start16 : AT (0x387fff00) { *(.start16); } . = 0xfff0; - .reset : AT (0x387ffff0) { *(.reset); } - _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) ); + .resetvec : AT (0x387ffff0) { *(.resetvec); } + _i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) ); } diff --git a/board/sc520_spunk/u-boot.lds b/board/sc520_spunk/u-boot.lds index 4d6603cb5..d2436bce4 100644 --- a/board/sc520_spunk/u-boot.lds +++ b/board/sc520_spunk/u-boot.lds @@ -76,7 +76,7 @@ SECTIONS * The fe00 and ff00 offsets of the start32 and start16 * segments are arbitrary, the just have to be mapped * at reset and the code have to fit. - * The fff0 offset of reset is important, however. + * The fff0 offset of resetvec is important, however. */ @@ -87,6 +87,6 @@ SECTIONS .start16 : AT (0x387fff00) { *(.start16); } . = 0xfff0; - .reset : AT (0x387ffff0) { *(.reset); } - _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) ); + .resetvec : AT (0x387ffff0) { *(.resetvec); } + _i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) ); } diff --git a/cpu/i386/Makefile b/cpu/i386/Makefile index 50534b615..f20675af1 100644 --- a/cpu/i386/Makefile +++ b/cpu/i386/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o start16.o reset.o +START = start.o start16.o resetvec.o COBJS = serial.o interrupts.o cpu.o timer.o sc520.o SOBJS = sc520_asm.o diff --git a/cpu/i386/reset.S b/cpu/i386/resetvec.S similarity index 97% rename from cpu/i386/reset.S rename to cpu/i386/resetvec.S index 07a738492..d9222dd2f 100644 --- a/cpu/i386/reset.S +++ b/cpu/i386/resetvec.S @@ -26,7 +26,7 @@ .extern start16 -.section .reset, "ax" +.section .resetvec, "ax" .code16 reset_vector: cli From 407976185e0dda2c90e89027121a1071b9c77bfb Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 7 Dec 2008 10:29:00 +1100 Subject: [PATCH 172/188] Moved sc520 specific code into new cpu/i386/sc520 folder Signed-off-by: Graeme Russ Signed-off-by: Wolfgang Denk --- Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index b859bcbd0..121e096b1 100644 --- a/Makefile +++ b/Makefile @@ -2994,16 +2994,16 @@ smdk6400_config : unconfig ## AMD SC520 CDP ######################################################################### eNET_config : unconfig - @$(MKCONFIG) $(@:_config=) i386 i386 eNET + @$(MKCONFIG) $(@:_config=) i386 i386 eNET NULL sc520 sc520_cdp_config : unconfig - @$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp + @$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp NULL sc520 sc520_spunk_config : unconfig - @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk + @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk NULL sc520 sc520_spunk_rel_config : unconfig - @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk + @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk NULL sc520 #======================================================================== # MIPS From 9933d609020c297788f53f334c8465fa7a99b10c Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 7 Dec 2008 10:29:01 +1100 Subject: [PATCH 173/188] Moved definition of set_vector() to new header file This allows for future tidy ups and functionality that will require set_vector () Signed-off-by: Graeme Russ --- cpu/i386/interrupts.c | 3 ++- include/asm-i386/interrupt.h | 29 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 1 deletion(-) create mode 100644 include/asm-i386/interrupt.h diff --git a/cpu/i386/interrupts.c b/cpu/i386/interrupts.c index f6dbccac5..ba9e89df2 100644 --- a/cpu/i386/interrupts.c +++ b/cpu/i386/interrupts.c @@ -26,6 +26,7 @@ #include #include #include +#include struct idt_entry { @@ -376,7 +377,7 @@ asm ("idt_ptr:\n" ".long idt\n" /* offset */ ".word 0x18\n");/* data segment */ -static void set_vector(int intnum, void *routine) +void set_vector(int intnum, void *routine) { idt[intnum].base_high = (u16)((u32)(routine)>>16); idt[intnum].base_low = (u16)((u32)(routine)&0xffff); diff --git a/include/asm-i386/interrupt.h b/include/asm-i386/interrupt.h new file mode 100644 index 000000000..315b4001c --- /dev/null +++ b/include/asm-i386/interrupt.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_INTERRUPT_H_ +#define __ASM_INTERRUPT_H_ 1 + +void set_vector(int intnum, void *routine); + +#endif From 3f5f18d12d32ee0661bf51dfc55752c005230d6e Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 7 Dec 2008 10:29:02 +1100 Subject: [PATCH 174/188] Moved generic (triple fault) reset code Moved from interrupts.c to cpu.c and made into a weak function to allow vendor specific override Vendor specific CPU reset (like the AMD SC520 MMCR reset) can now be added to the vendor specific code without the need to remember to #undef usage of the generic method and if you forget to include your custom reset method, you will always get the default. Signed-off-by: Graeme Russ --- cpu/i386/cpu.c | 17 +++++++++++++++++ cpu/i386/interrupts.c | 16 ---------------- 2 files changed, 17 insertions(+), 16 deletions(-) diff --git a/cpu/i386/cpu.c b/cpu/i386/cpu.c index 5fd37c72a..b9af5f89d 100644 --- a/cpu/i386/cpu.c +++ b/cpu/i386/cpu.c @@ -35,6 +35,7 @@ #include #include +#include int cpu_init(void) { @@ -64,3 +65,19 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) asm("wbinvd\n"); return; } + +void __attribute__ ((regparm(0))) generate_gpf(void); + +/* segment 0x70 is an arbitrary segment which does not exist */ +asm(".globl generate_gpf\n" + "generate_gpf:\n" + "ljmp $0x70, $0x47114711\n"); + +void __reset_cpu(ulong addr) +{ + printf("Resetting using i386 Triple Fault\n"); + set_vector(13, generate_gpf); /* general protection fault handler */ + set_vector(8, generate_gpf); /* double fault handler */ + generate_gpf(); /* start the show */ +} +void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu"))); diff --git a/cpu/i386/interrupts.c b/cpu/i386/interrupts.c index ba9e89df2..badb30bb8 100644 --- a/cpu/i386/interrupts.c +++ b/cpu/i386/interrupts.c @@ -508,19 +508,3 @@ int disable_interrupts(void) return (flags&0x200); /* IE flags is bit 9 */ } - - -#ifdef CONFIG_SYS_RESET_GENERIC - -void __attribute__ ((regparm(0))) generate_gpf(void); -asm(".globl generate_gpf\n" - "generate_gpf:\n" - "ljmp $0x70, $0x47114711\n"); /* segment 0x70 is an arbitrary segment which does not - * exist */ -void reset_cpu(ulong addr) -{ - set_vector(13, generate_gpf); /* general protection fault handler */ - set_vector(8, generate_gpf); /* double fault handler */ - generate_gpf(); /* start the show */ -} -#endif From ead056bc206f6b7ee6dc98766678b64635ea20b8 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 7 Dec 2008 10:29:03 +1100 Subject: [PATCH 175/188] Added MMCR reset functionality Reset function specific to AMD SC520 microcontroller - Is more of a 'hard reset' that the triple fault. Requires CONFIG_SYS_RESET_SC520 to be defined in config I would have liked to add this to a new file (cpu/i386/sc520/reset.c) but ld requires that a object file in a library arhive MUST contain at least one function which does not override a weak function (and is called from outside the object file) in order for that object file to be extracted from the archive. This would be the only function on the new file, and hence, will never get linked in. Signed-off-by: Graeme Russ --- cpu/i386/sc520.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c index cb6bc03bc..50bd8ef5d 100644 --- a/cpu/i386/sc520.c +++ b/cpu/i386/sc520.c @@ -507,4 +507,14 @@ u8 ssi_rx_byte(void) return read_mmcr_byte(SC520_SSIRCV); } +#ifdef CONFIG_SYS_RESET_SC520 +void reset_cpu(ulong addr) +{ + printf("Resetting using SC520 MMCR\n"); + /* Write a '1' to the SYS_RST of the RESCFG MMCR */ + write_mmcr_word(SC520_RESCFG, 0x0001); + + /* NOTREACHED */ +} +#endif #endif /* CONFIG_SC520 */ From 2b5360eb2bc0b741ae5cb3c84d35ccdd17667c8a Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 7 Dec 2008 10:29:04 +1100 Subject: [PATCH 176/188] Remove #ifdef CONFIG_SC520 in source code CONFIG_SC520 is now used for conditional compile Signed-off-by: Graeme Russ --- cpu/i386/sc520.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c index 50bd8ef5d..12e8f3871 100644 --- a/cpu/i386/sc520.c +++ b/cpu/i386/sc520.c @@ -25,9 +25,6 @@ * but idependent of implementation */ #include - -#ifdef CONFIG_SC520 - #include #include #include @@ -517,4 +514,3 @@ void reset_cpu(ulong addr) /* NOTREACHED */ } #endif -#endif /* CONFIG_SC520 */ From a5989c42ae5e295f274a795c426c47819bbdbfda Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 7 Dec 2008 10:29:05 +1100 Subject: [PATCH 177/188] Removed all references to CONFIG_SYS_RESET_GENERIC Generic i386 reset - #define made redundant by weak function Signed-off-by: Graeme Russ --- include/configs/eNET.h | 1 - include/configs/sc520_cdp.h | 1 - include/configs/sc520_spunk.h | 1 - 3 files changed, 3 deletions(-) diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 87d2908a3..8f9e97245 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -142,7 +142,6 @@ * CPU Features */ #define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ -#define CONFIG_SYS_RESET_GENERIC /* use triple-fault to reset cpu */ #undef CONFIG_SYS_RESET_SC520 /* use SC520 MMCR's to reset cpu */ #define CONFIG_SYS_TIMER_SC520 /* use SC520 swtimers */ #undef CONFIG_SYS_TIMER_GENERIC /* use the i8254 PIT timers */ diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index bf8693e46..9f2357b0b 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -47,7 +47,6 @@ #define CONFIG_SYS_SDRAM_CAS_LATENCY_3T #define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ -#define CONFIG_SYS_RESET_GENERIC 1 /* use tripple-fault to reset cpu */ #undef CONFIG_SYS_RESET_SC520 /* use SC520 MMCR's to reset cpu */ #undef CONFIG_SYS_TIMER_SC520 /* use SC520 swtimers */ #define CONFIG_SYS_TIMER_GENERIC 1 /* use the i8254 PIT timers */ diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h index fbdbeddf6..50af7324a 100644 --- a/include/configs/sc520_spunk.h +++ b/include/configs/sc520_spunk.h @@ -45,7 +45,6 @@ #define CONFIG_SYS_SDRAM_CAS_LATENCY_3T #define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ -#define CONFIG_SYS_RESET_GENERIC 1 /* use tripple-fault to reset cpu */ #undef CONFIG_SYS_RESET_SC520 /* use SC520 MMCR's to reset cpu */ #undef CONFIG_SYS_TIMER_SC520 /* use SC520 swtimers */ #define CONFIG_SYS_TIMER_GENERIC 1 /* use the i8254 PIT timers */ From 626d07348e5f9f302f4ea182161a89f7362a0488 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Mon, 8 Dec 2008 20:04:51 +1100 Subject: [PATCH 178/188] Fixed off-by-one errors in lib_m68k/interrupts.c Signed-off-by: Graeme Russ --- lib_m68k/interrupts.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib_m68k/interrupts.c b/lib_m68k/interrupts.c index 2dc079bee..133494f6d 100644 --- a/lib_m68k/interrupts.c +++ b/lib_m68k/interrupts.c @@ -61,7 +61,7 @@ static __inline__ void set_sr (unsigned short sr) */ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) { - if ((vec < 0) || (vec > NR_IRQS)) { + if ((vec < 0) || (vec >= NR_IRQS)) { printf ("irq_install_handler: wrong interrupt vector %d\n", vec); return; @@ -73,7 +73,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) void irq_free_handler (int vec) { - if ((vec < 0) || (vec > NR_IRQS)) { + if ((vec < 0) || (vec >= NR_IRQS)) { return; } From 94f9279f7bbdc01bbc7cf85aedf9b545943b94c3 Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Mon, 8 Dec 2008 17:24:08 +0100 Subject: [PATCH 179/188] Added legacy flash ST Micro M29W040B --- drivers/mtd/jedec_flash.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c index 226e1e418..2d99d4d9a 100644 --- a/drivers/mtd/jedec_flash.c +++ b/drivers/mtd/jedec_flash.c @@ -215,6 +215,20 @@ static const struct amd_flash_info jedec_table[] = { ERASEINFO(0x01000,128), } }, + { + .mfr_id = STM_MANUFACT, + .dev_id = STM_ID_M29W040B, + .name = "ST Micro M29W040B", + .uaddr = { + [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000,8), + } + }, #endif #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16 { From c3284b030b1cd492b4f46c576aea01bef258599d Mon Sep 17 00:00:00 2001 From: Peter Korsgaard Date: Wed, 10 Dec 2008 16:24:16 +0100 Subject: [PATCH 180/188] common/main: support bootdelay=0 for CONFIG_AUTOBOOT_KEYED Support bootdelay=0 in abortboot for the CONFIG_AUTOBOOT_KEYED case similar to the CONFIG_ZERO_BOOTDELAY_CHECK support for the !CONFIG_AUTOBOOT_KEYED case. Do this by reversing the loop so we do at least one iteration before checking for timeout. Signed-off-by: Peter Korsgaard --- common/main.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/common/main.c b/common/main.c index a999a5d64..4c4f78065 100644 --- a/common/main.c +++ b/common/main.c @@ -158,7 +158,19 @@ static __inline__ int abortboot(int bootdelay) /* In order to keep up with incoming data, check timeout only * when catch up. */ - while (!abort && get_ticks() <= etime) { + do { + if (tstc()) { + if (presskey_len < presskey_max) { + presskey [presskey_len ++] = getc(); + } + else { + for (i = 0; i < presskey_max - 1; i ++) + presskey [i] = presskey [i + 1]; + + presskey [i] = getc(); + } + } + for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i ++) { if (delaykey[i].len > 0 && presskey_len >= delaykey[i].len && @@ -178,19 +190,8 @@ static __inline__ int abortboot(int bootdelay) abort = 1; } } + } while (!abort && get_ticks() <= etime); - if (tstc()) { - if (presskey_len < presskey_max) { - presskey [presskey_len ++] = getc(); - } - else { - for (i = 0; i < presskey_max - 1; i ++) - presskey [i] = presskey [i + 1]; - - presskey [i] = getc(); - } - } - } # if DEBUG_BOOTKEYS if (!abort) puts("key timeout\n"); From 36ede4d63e59c9277ec180b09c39b8bf46425ba2 Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Fri, 12 Dec 2008 00:45:27 +0900 Subject: [PATCH 181/188] nios: Move README.nios_CONFIG_SYS_NIOS_CPU to doc/ dir Signed-off-by: Shinya Kuribayashi --- .../README.nios_CONFIG_SYS_NIOS_CPU | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename README.nios_CONFIG_SYS_NIOS_CPU => doc/README.nios_CONFIG_SYS_NIOS_CPU (100%) diff --git a/README.nios_CONFIG_SYS_NIOS_CPU b/doc/README.nios_CONFIG_SYS_NIOS_CPU similarity index 100% rename from README.nios_CONFIG_SYS_NIOS_CPU rename to doc/README.nios_CONFIG_SYS_NIOS_CPU From 97cae3a4c68d856374ccc70fd2c5f8714cc94f7d Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 15 Dec 2008 15:40:12 +0100 Subject: [PATCH 182/188] serial: Rename driver vcth to vct to support other board variants Moved driver vcth.c to vct.c to better reflect the VCT board series. This driver is now used by the VCT platforms: vct_premium vct_platinum vct_platinumsvc Signed-off-by: Stefan Roese --- drivers/serial/Makefile | 2 +- drivers/serial/{vcth.c => vct.c} | 8 ++++++-- 2 files changed, 7 insertions(+), 3 deletions(-) rename drivers/serial/{vcth.c => vct.c} (94%) diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 17235ff17..c7a1882ef 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -38,7 +38,7 @@ COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o COBJS-$(CONFIG_USB_TTY) += usbtty.o -COBJS-$(CONFIG_VCTH_SERIAL) += vcth.o +COBJS-$(CONFIG_VCT_SERIAL) += vct.o COBJS := $(sort $(COBJS-y)) SRCS := $(COBJS:.o=.c) diff --git a/drivers/serial/vcth.c b/drivers/serial/vct.c similarity index 94% rename from drivers/serial/vcth.c rename to drivers/serial/vct.c index 2c847d08a..556c114e0 100755 --- a/drivers/serial/vcth.c +++ b/drivers/serial/vct.c @@ -21,7 +21,11 @@ #include #include +#ifdef CONFIG_VCT_PLATINUMAVC +#define UART_1_BASE 0xBDC30000 +#else #define UART_1_BASE 0xBF89C000 +#endif #define UART_RBR_OFF 0x00 /* receiver buffer reg */ #define UART_THR_OFF 0x00 /* transmit holding reg */ @@ -53,7 +57,7 @@ #define UART_7DATA_BITS 0x0002 /* 7 [bits] 1 bits 2 */ #define UART_8DATA_BITS 0x0003 /* 8 [bits] 1 bits 2 */ -static void vcth_uart_set_baud_rate(u32 address, u32 dh, u32 dl) +static void vct_uart_set_baud_rate(u32 address, u32 dh, u32 dl) { u32 val = __raw_readl(UART_1_BASE + UART_LCR_OFF); @@ -74,7 +78,7 @@ static void vcth_uart_set_baud_rate(u32 address, u32 dh, u32 dl) int serial_init(void) { __raw_writel(UART_DIS_ALL_INTER, UART_1_BASE + UART_IER_OFF); - vcth_uart_set_baud_rate(UART_1_BASE, 0, UART_115200_BDR); + vct_uart_set_baud_rate(UART_1_BASE, 0, UART_115200_BDR); __raw_writel(UART_8DATA_BITS, UART_1_BASE + UART_LCR_OFF); return 0; From b6fc6fd49a84543e1324e1620b9f301ff7c1f27f Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Tue, 16 Dec 2008 14:51:56 +0100 Subject: [PATCH 183/188] common: Iteration limit for memory test. The iteration limit is passed to mtest as a fourth parameter: [start [end [pattern [iterations]]]] If no fourth parameter is supplied, there is no iteration limit and the test will loop forever. Signed-off-by: Dirk Eibach --- common/cmd_mem.c | 45 +++++++++++++++++++++++++++++++-------------- 1 file changed, 31 insertions(+), 14 deletions(-) diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 400cfd747..c209d62d8 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -672,6 +672,8 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong val; ulong readback; int rcode = 0; + int iterations = 1; + int iteration_limit; #if defined(CONFIG_SYS_ALT_MEMTEST) vu_long len; @@ -687,7 +689,6 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) vu_long *dummy = 0; /* yes, this is address 0x0, not NULL */ #endif int j; - int iterations = 1; static const ulong bitpattern[] = { 0x00000001, /* single bit */ @@ -704,23 +705,25 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong pattern; #endif - if (argc > 1) { + if (argc > 1) start = (ulong *)simple_strtoul(argv[1], NULL, 16); - } else { + else start = (ulong *)CONFIG_SYS_MEMTEST_START; - } - if (argc > 2) { + if (argc > 2) end = (ulong *)simple_strtoul(argv[2], NULL, 16); - } else { + else end = (ulong *)(CONFIG_SYS_MEMTEST_END); - } - if (argc > 3) { + if (argc > 3) pattern = (ulong)simple_strtoul(argv[3], NULL, 16); - } else { + else pattern = 0; - } + + if (argc > 4) + iteration_limit = (ulong)simple_strtoul(argv[4], NULL, 16); + else + iteration_limit = 0; #if defined(CONFIG_SYS_ALT_MEMTEST) printf ("Testing %08x ... %08x:\n", (uint)start, (uint)end); @@ -733,8 +736,15 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } + + if (iteration_limit && iterations > iteration_limit) { + printf("Tested %d iteration(s) without errors.\n", + iterations-1); + return 0; + } + printf("Iteration: %6d\r", iterations); - PRINTF("Iteration: %6d\n", iterations); + PRINTF("\n"); iterations++; /* @@ -926,6 +936,13 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } + if (iteration_limit && iterations > iteration_limit) { + printf("Tested %d iteration(s) without errors.\n", + iterations-1); + return 0; + } + ++iterations; + printf ("\rPattern %08lX Writing..." "%12s" "\b\b\b\b\b\b\b\b\b\b", @@ -1276,9 +1293,9 @@ U_BOOT_CMD( #endif /* CONFIG_LOOPW */ U_BOOT_CMD( - mtest, 4, 1, do_mem_mtest, - "mtest - simple RAM test\n", - "[start [end [pattern]]]\n" + mtest, 5, 1, do_mem_mtest, + "mtest - simple RAM test\n", + "[start [end [pattern [iterations]]]]\n" " - simple RAM read/write test\n" ); From a7c9310457e85b4598abe5b304108edf11332e2f Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Wed, 17 Dec 2008 16:36:22 -0600 Subject: [PATCH 184/188] Add support for Maxim's DS4510 I2C device Initial support for the DS4510, a CPU supervisor with integrated EEPROM, SRAM, and 4 programmable non-volatile GPIO pins. The CONFIG_DS4510 define enables support for the device while the CONFIG_CMD_DS4510 define enables the ds4510 command. The additional CONFIG_DS4510_INFO, CONFIG_DS4510_MEM, and CONFIG_DS4510_RST defines add additional sub-commands to the ds4510 command when defined. Signed-off-by: Peter Tyser --- README | 4 + drivers/misc/Makefile | 1 + drivers/misc/ds4510.c | 424 ++++++++++++++++++++++++++++++++++++++++++ include/ds4510.h | 75 ++++++++ 4 files changed, 504 insertions(+) create mode 100644 drivers/misc/ds4510.c create mode 100644 include/ds4510.h diff --git a/README b/README index 132650ee5..ad792d394 100644 --- a/README +++ b/README @@ -592,6 +592,10 @@ The following options need to be configured: CONFIG_CMD_DHCP * DHCP support CONFIG_CMD_DIAG * Diagnostics CONFIG_CMD_DOC * Disk-On-Chip Support + CONFIG_CMD_DS4510 * ds4510 I2C gpio commands + CONFIG_CMD_DS4510_INFO * ds4510 I2C info command + CONFIG_CMD_DS4510_MEM * ds4510 I2C eeprom/sram commansd + CONFIG_CMD_DS4510_RST * ds4510 I2C rst command CONFIG_CMD_DTT * Digital Therm and Thermostat CONFIG_CMD_ECHO echo arguments CONFIG_CMD_EEPROM * EEPROM read/write support diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 01e0f393d..ea2bf87ec 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libmisc.a COBJS-$(CONFIG_ALI152X) += ali512x.o +COBJS-$(CONFIG_DS4510) += ds4510.o COBJS-$(CONFIG_FSL_LAW) += fsl_law.o COBJS-$(CONFIG_NS87308) += ns87308.o COBJS-$(CONFIG_STATUS_LED) += status_led.o diff --git a/drivers/misc/ds4510.c b/drivers/misc/ds4510.c new file mode 100644 index 000000000..4cd2fc224 --- /dev/null +++ b/drivers/misc/ds4510.c @@ -0,0 +1,424 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Driver for DS4510, a CPU supervisor with integrated EEPROM, SRAM, + * and 4 programmable non-volatile GPIO pins. + */ + +#include +#include +#include +#include + +/* Default to an address that hopefully won't corrupt other i2c devices */ +#ifndef CONFIG_SYS_I2C_DS4510_ADDR +#define CONFIG_SYS_I2C_DS4510_ADDR (~0) +#endif + +enum { + DS4510_CMD_INFO, + DS4510_CMD_DEVICE, + DS4510_CMD_NV, + DS4510_CMD_RSTDELAY, + DS4510_CMD_OUTPUT, + DS4510_CMD_INPUT, + DS4510_CMD_PULLUP, + DS4510_CMD_EEPROM, + DS4510_CMD_SEEPROM, + DS4510_CMD_SRAM, +}; + +/* + * Write to DS4510, taking page boundaries into account + */ +int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count) +{ + int wrlen; + int i = 0; + + do { + wrlen = DS4510_EEPROM_PAGE_SIZE - + DS4510_EEPROM_PAGE_OFFSET(offset); + if (count < wrlen) + wrlen = count; + if (i2c_write(chip, offset, 1, &buf[i], wrlen)) + return -1; + + /* + * This delay isn't needed for SRAM writes but shouldn't delay + * things too much, so do it unconditionally for simplicity + */ + udelay(DS4510_EEPROM_PAGE_WRITE_DELAY_MS * 1000); + count -= wrlen; + offset += wrlen; + i += wrlen; + } while (count > 0); + + return 0; +} + +/* + * General read from DS4510 + */ +int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count) +{ + return i2c_read(chip, offset, 1, buf, count); +} + +/* + * Write SEE bit in config register. + * nv = 0 - Writes to SEEPROM registers behave like EEPROM + * nv = 1 - Writes to SEEPROM registers behave like SRAM + */ +int ds4510_see_write(uint8_t chip, uint8_t nv) +{ + uint8_t data; + + if (i2c_read(chip, DS4510_CFG, 1, &data, 1)) + return -1; + + if (nv) /* Treat SEEPROM bits as EEPROM */ + data &= ~DS4510_CFG_SEE; + else /* Treat SEEPROM bits as SRAM */ + data |= DS4510_CFG_SEE; + + return ds4510_mem_write(chip, DS4510_CFG, &data, 1); +} + +/* + * Write de-assertion of reset signal delay + */ +int ds4510_rstdelay_write(uint8_t chip, uint8_t delay) +{ + uint8_t data; + + if (i2c_read(chip, DS4510_RSTDELAY, 1, &data, 1)) + return -1; + + data &= ~DS4510_RSTDELAY_MASK; + data |= delay & DS4510_RSTDELAY_MASK; + + return ds4510_mem_write(chip, DS4510_RSTDELAY, &data, 1); +} + +/* + * Write pullup characteristics of IO pins + */ +int ds4510_pullup_write(uint8_t chip, uint8_t val) +{ + val &= DS4510_IO_MASK; + + return ds4510_mem_write(chip, DS4510_PULLUP, (uint8_t *)&val, 1); +} + +/* + * Read pullup characteristics of IO pins + */ +int ds4510_pullup_read(uint8_t chip) +{ + uint8_t val; + + if (i2c_read(chip, DS4510_PULLUP, 1, &val, 1)) + return -1; + + return val & DS4510_IO_MASK; +} + +/* + * Write drive level of IO pins + */ +int ds4510_gpio_write(uint8_t chip, uint8_t val) +{ + uint8_t data; + int i; + + for (i = 0; i < DS4510_NUM_IO; i++) { + if (i2c_read(chip, DS4510_IO0 - i, 1, &data, 1)) + return -1; + + if (val & (0x1 << i)) + data |= 0x1; + else + data &= ~0x1; + + if (ds4510_mem_write(chip, DS4510_IO0 - i, &data, 1)) + return -1; + } + + return 0; +} + +/* + * Read drive level of IO pins + */ +int ds4510_gpio_read(uint8_t chip) +{ + uint8_t data; + int val = 0; + int i; + + for (i = 0; i < DS4510_NUM_IO; i++) { + if (i2c_read(chip, DS4510_IO0 - i, 1, &data, 1)) + return -1; + + if (data & 1) + val |= (1 << i); + } + + return val; +} + +/* + * Read physical level of IO pins + */ +int ds4510_gpio_read_val(uint8_t chip) +{ + uint8_t val; + + if (i2c_read(chip, DS4510_IO_STATUS, 1, &val, 1)) + return -1; + + return val & DS4510_IO_MASK; +} + +#ifdef CONFIG_CMD_DS4510 +#ifdef CONFIG_CMD_DS4510_INFO +/* + * Display DS4510 information + */ +static int ds4510_info(uint8_t chip) +{ + int i; + int tmp; + uint8_t data; + + printf("DS4510 @ 0x%x:\n\n", chip); + + if (i2c_read(chip, DS4510_RSTDELAY, 1, &data, 1)) + return -1; + printf("rstdelay = 0x%x\n\n", data & DS4510_RSTDELAY_MASK); + + if (i2c_read(chip, DS4510_CFG, 1, &data, 1)) + return -1; + printf("config = 0x%x\n", data); + printf(" /ready = %d\n", data & DS4510_CFG_READY ? 1 : 0); + printf(" trip pt = %d\n", data & DS4510_CFG_TRIP_POINT ? 1 : 0); + printf(" rst sts = %d\n", data & DS4510_CFG_RESET ? 1 : 0); + printf(" /see = %d\n", data & DS4510_CFG_SEE ? 1 : 0); + printf(" swrst = %d\n\n", data & DS4510_CFG_SWRST ? 1 : 0); + + printf("gpio pins: 3210\n"); + printf("---------------\n"); + printf("pullup "); + + tmp = ds4510_pullup_read(chip); + if (tmp == -1) + return tmp; + for (i = DS4510_NUM_IO - 1; i >= 0; i--) + printf("%d", (tmp & (1 << i)) ? 1 : 0); + printf("\n"); + + printf("driven "); + tmp = ds4510_gpio_read(chip); + if (tmp == -1) + return -1; + for (i = DS4510_NUM_IO - 1; i >= 0; i--) + printf("%d", (tmp & (1 << i)) ? 1 : 0); + printf("\n"); + + printf("read "); + tmp = ds4510_gpio_read_val(chip); + if (tmp == -1) + return -1; + for (i = DS4510_NUM_IO - 1; i >= 0; i--) + printf("%d", (tmp & (1 << i)) ? 1 : 0); + printf("\n"); + + return 0; +} +#endif /* CONFIG_CMD_DS4510_INFO */ + +cmd_tbl_t cmd_ds4510[] = { + U_BOOT_CMD_MKENT(device, 3, 0, (void *)DS4510_CMD_DEVICE, "", ""), + U_BOOT_CMD_MKENT(nv, 3, 0, (void *)DS4510_CMD_NV, "", ""), + U_BOOT_CMD_MKENT(output, 4, 0, (void *)DS4510_CMD_OUTPUT, "", ""), + U_BOOT_CMD_MKENT(input, 3, 0, (void *)DS4510_CMD_INPUT, "", ""), + U_BOOT_CMD_MKENT(pullup, 4, 0, (void *)DS4510_CMD_PULLUP, "", ""), +#ifdef CONFIG_CMD_DS4510_INFO + U_BOOT_CMD_MKENT(info, 2, 0, (void *)DS4510_CMD_INFO, "", ""), +#endif +#ifdef CONFIG_CMD_DS4510_RST + U_BOOT_CMD_MKENT(rstdelay, 3, 0, (void *)DS4510_CMD_RSTDELAY, "", ""), +#endif +#ifdef CONFIG_CMD_DS4510_MEM + U_BOOT_CMD_MKENT(eeprom, 6, 0, (void *)DS4510_CMD_EEPROM, "", ""), + U_BOOT_CMD_MKENT(seeprom, 6, 0, (void *)DS4510_CMD_SEEPROM, "", ""), + U_BOOT_CMD_MKENT(sram, 6, 0, (void *)DS4510_CMD_SRAM, "", ""), +#endif +}; + +int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + static uint8_t chip = CONFIG_SYS_I2C_DS4510_ADDR; + cmd_tbl_t *c; + ulong ul_arg2 = 0; + ulong ul_arg3 = 0; + int tmp; +#ifdef CONFIG_CMD_DS4510_MEM + ulong addr; + ulong off; + ulong cnt; + int end; + int (*rw_func)(uint8_t, int, uint8_t *, int); +#endif + + c = find_cmd_tbl(argv[1], cmd_ds4510, ARRAY_SIZE(cmd_ds4510)); + + /* All commands but "device" require 'maxargs' arguments */ + if (!c || !((argc == (c->maxargs)) || + (((int)c->cmd == DS4510_CMD_DEVICE) && + (argc == (c->maxargs - 1))))) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* arg2 used as chip addr and pin number */ + if (argc > 2) + ul_arg2 = simple_strtoul(argv[2], NULL, 16); + + /* arg3 used as output/pullup value */ + if (argc > 3) + ul_arg3 = simple_strtoul(argv[3], NULL, 16); + + switch ((int)c->cmd) { + case DS4510_CMD_DEVICE: + if (argc == 3) + chip = ul_arg2; + printf("Current device address: 0x%x\n", chip); + return 0; + case DS4510_CMD_NV: + return ds4510_see_write(chip, ul_arg2); + case DS4510_CMD_OUTPUT: + tmp = ds4510_gpio_read(chip); + if (tmp == -1) + return -1; + if (ul_arg3) + tmp |= (1 << ul_arg2); + else + tmp &= ~(1 << ul_arg2); + return ds4510_gpio_write(chip, tmp); + case DS4510_CMD_INPUT: + tmp = ds4510_gpio_read_val(chip); + if (tmp == -1) + return -1; + return (tmp & (1 << ul_arg2)) != 0; + case DS4510_CMD_PULLUP: + tmp = ds4510_pullup_read(chip); + if (tmp == -1) + return -1; + if (ul_arg3) + tmp |= (1 << ul_arg2); + else + tmp &= ~(1 << ul_arg2); + return ds4510_pullup_write(chip, tmp); +#ifdef CONFIG_CMD_DS4510_INFO + case DS4510_CMD_INFO: + return ds4510_info(chip); +#endif +#ifdef CONFIG_CMD_DS4510_RST + case DS4510_CMD_RSTDELAY: + return ds4510_rstdelay_write(chip, ul_arg2); +#endif +#ifdef CONFIG_CMD_DS4510_MEM + case DS4510_CMD_EEPROM: + end = DS4510_EEPROM + DS4510_EEPROM_SIZE; + off = DS4510_EEPROM; + break; + case DS4510_CMD_SEEPROM: + end = DS4510_SEEPROM + DS4510_SEEPROM_SIZE; + off = DS4510_SEEPROM; + break; + case DS4510_CMD_SRAM: + end = DS4510_SRAM + DS4510_SRAM_SIZE; + off = DS4510_SRAM; + break; +#endif + default: + /* We should never get here... */ + return 1; + } + +#ifdef CONFIG_CMD_DS4510_MEM + /* Only eeprom, seeprom, and sram commands should make it here */ + if (strcmp(argv[2], "read") == 0) { + rw_func = ds4510_mem_read; + } else if (strcmp(argv[2], "write") == 0) { + rw_func = ds4510_mem_write; + } else { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + addr = simple_strtoul(argv[3], NULL, 16); + off += simple_strtoul(argv[4], NULL, 16); + cnt = simple_strtoul(argv[5], NULL, 16); + + if ((off + cnt) > end) { + printf("ERROR: invalid len\n"); + return -1; + } + + return rw_func(chip, off, (uint8_t *)addr, cnt); +#endif +} + +U_BOOT_CMD( + ds4510, 6, 1, do_ds4510, + "ds4510 - ds4510 eeprom/seeprom/sram/gpio access\n", + "device [dev]\n" + " - show or set current device address\n" +#ifdef CONFIG_CMD_DS4510_INFO + "ds4510 info\n" + " - display ds4510 info\n" +#endif + "ds4510 output pin 0|1\n" + " - set pin low or high-Z\n" + "ds4510 input pin\n" + " - read value of pin\n" + "ds4510 pullup pin 0|1\n" + " - disable/enable pullup on specified pin\n" + "ds4510 nv 0|1\n" + " - make gpio and seeprom writes volatile/non-volatile\n" +#ifdef CONFIG_CMD_DS4510_RST + "ds4510 rstdelay 0-3\n" + " - set reset output delay\n" +#endif +#ifdef CONFIG_CMD_DS4510_MEM + "ds4510 eeprom read addr off cnt\n" + "ds4510 eeprom write addr off cnt\n" + " - read/write 'cnt' bytes at EEPROM offset 'off'\n" + "ds4510 seeprom read addr off cnt\n" + "ds4510 seeprom write addr off cnt\n" + " - read/write 'cnt' bytes at SRAM-shadowed EEPROM offset 'off'\n" + "ds4510 sram read addr off cnt\n" + "ds4510 sram write addr off cnt\n" + " - read/write 'cnt' bytes at SRAM offset 'off'\n" +#endif +); +#endif /* CONFIG_CMD_DS4510 */ diff --git a/include/ds4510.h b/include/ds4510.h new file mode 100644 index 000000000..40480afc9 --- /dev/null +++ b/include/ds4510.h @@ -0,0 +1,75 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __DS4510_H_ +#define __DS4510_H_ + +/* General defines */ +#define DS4510_NUM_IO 0x04 +#define DS4510_IO_MASK ((1 << DS4510_NUM_IO) - 1) +#define DS4510_EEPROM_PAGE_WRITE_DELAY_MS 20 + +/* EEPROM from 0x00 - 0x39 */ +#define DS4510_EEPROM 0x00 +#define DS4510_EEPROM_SIZE 0x40 +#define DS4510_EEPROM_PAGE_SIZE 0x08 +#define DS4510_EEPROM_PAGE_OFFSET(x) ((x) & (DS4510_EEPROM_PAGE_SIZE - 1)) + +/* SEEPROM from 0xf0 - 0xf7 */ +#define DS4510_SEEPROM 0xf0 +#define DS4510_SEEPROM_SIZE 0x08 + +/* Registers overlapping SEEPROM from 0xf0 - 0xf7 */ +#define DS4510_PULLUP 0xF0 +#define DS4510_PULLUP_DIS 0x00 +#define DS4510_PULLUP_EN 0x01 +#define DS4510_RSTDELAY 0xF1 +#define DS4510_RSTDELAY_MASK 0x03 +#define DS4510_RSTDELAY_125 0x00 +#define DS4510_RSTDELAY_250 0x01 +#define DS4510_RSTDELAY_500 0x02 +#define DS4510_RSTDELAY_1000 0x03 +#define DS4510_IO3 0xF4 +#define DS4510_IO2 0xF5 +#define DS4510_IO1 0xF6 +#define DS4510_IO0 0xF7 + +/* Status configuration registers from 0xf8 - 0xf9*/ +#define DS4510_IO_STATUS 0xF8 +#define DS4510_CFG 0xF9 +#define DS4510_CFG_READY 0x80 +#define DS4510_CFG_TRIP_POINT 0x40 +#define DS4510_CFG_RESET 0x20 +#define DS4510_CFG_SEE 0x10 +#define DS4510_CFG_SWRST 0x08 + +/* SRAM from 0xfa - 0xff */ +#define DS4510_SRAM 0xfa +#define DS4510_SRAM_SIZE 0x06 + +int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count); +int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count); +int ds4510_see_write(uint8_t chip, uint8_t nv); +int ds4510_rstdelay_write(uint8_t chip, uint8_t delay); +int ds4510_pullup_write(uint8_t chip, uint8_t val); +int ds4510_pullup_read(uint8_t chip); +int ds4510_gpio_write(uint8_t chip, uint8_t val); +int ds4510_gpio_read(uint8_t chip); +int ds4510_gpio_read_val(uint8_t chip); + +#endif /* __DS4510_H_ */ From ce82ff05388b5ddafdf6082ef0776cce72c40b1c Mon Sep 17 00:00:00 2001 From: Yuri Tikhonov Date: Sat, 20 Dec 2008 14:54:21 +0300 Subject: [PATCH 185/188] FPU POST: fix warnings when building with 2.18 binutils When compile u-boot with the 2.18 binutils the following warning messages for each object file in post/lib_ppc/fpu/ is produced at the linking stage: post/libpost.a(acc1.o) uses hard float, u-boot uses soft-float ... This is because of the fact that, in general, the soft-float and hard-float ABIs are incompatible; the 2.18 binutils do checking of the Tag_GNU_Power_ABI_FP attribute of the files to be linked, and produce the worning like above if these are not compatible. The incompatibility of ABIs is concerned only the float values: e.g. the soft-float ABI assumes the float argument passing in the pair of rX registers, and the hard-float ABI assumes passing of the float argument in the fX register. When we don't pass the float arguments between the functions compiled with different floatness, then such an application will work correctly. This is the case for the FPU POST: u-boot (compiled with soft-float) doesn't pass to (and doesn't get from) the FPU POST functions any floats; there are no functions exported from the post/lib_ppc/fpu/ objects which would work with float parameters/returns too. So, we can reassure the linker not to worry about the difference in ABI attributes of linking files just by setting the 'soft-float' attribute for the objects in post/lib_ppc/fpu. And this patch does this. Also, to avoid passing both soft- and hard-float options in CFLAGS when compiling the files from post/lib_ppc/fpu (which is OK, but looks rather dirty) this patch removes the soft-float string from CFLAGS in post/lib_ppc/fpu/Makefile. Signed-off-by: Yuri Tikhonov --- include/post.h | 13 +++++++++++++ post/lib_ppc/fpu/20001122-1.c | 2 ++ post/lib_ppc/fpu/20010114-2.c | 2 ++ post/lib_ppc/fpu/20010226-1.c | 2 ++ post/lib_ppc/fpu/980619-1.c | 2 ++ post/lib_ppc/fpu/Makefile | 1 + post/lib_ppc/fpu/acc1.c | 2 ++ post/lib_ppc/fpu/compare-fp-1.c | 2 ++ post/lib_ppc/fpu/fpu.c | 2 ++ post/lib_ppc/fpu/mul-subnormal-single-1.c | 2 ++ 10 files changed, 30 insertions(+) diff --git a/include/post.h b/include/post.h index 97583b7e9..fe96312cb 100644 --- a/include/post.h +++ b/include/post.h @@ -80,6 +80,19 @@ extern struct post_test post_list[]; extern unsigned int post_list_size; extern int post_hotkeys_pressed(void); +/* + * If GCC is configured to use a version of GAS that supports + * the .gnu_attribute directive, it will use that directive to + * record certain properties of the output code. + * This feature is new to GCC 4.3.0. + * .gnu_attribute is new to GAS 2.18. + */ +#if (__GNUC__ >= 4 && __GNUC_MINOR__ >= 3) +/* Tag_GNU_Power_ABI_FP/soft-float */ +#define GNU_FPOST_ATTR asm(".gnu_attribute 4, 2"); +#else +#define GNU_FPOST_ATTR +#endif /* __GNUC__ */ #endif /* __ASSEMBLY__ */ #define CONFIG_SYS_POST_RTC 0x00000001 diff --git a/post/lib_ppc/fpu/20001122-1.c b/post/lib_ppc/fpu/20001122-1.c index a8537fa6a..bef80c5f7 100644 --- a/post/lib_ppc/fpu/20001122-1.c +++ b/post/lib_ppc/fpu/20001122-1.c @@ -30,6 +30,8 @@ #if CONFIG_POST & CONFIG_SYS_POST_FPU +GNU_FPOST_ATTR + int fpu_post_test_math1 (void) { volatile double a, *p; diff --git a/post/lib_ppc/fpu/20010114-2.c b/post/lib_ppc/fpu/20010114-2.c index 91e3631d0..ee564e8d6 100644 --- a/post/lib_ppc/fpu/20010114-2.c +++ b/post/lib_ppc/fpu/20010114-2.c @@ -30,6 +30,8 @@ #if CONFIG_POST & CONFIG_SYS_POST_FPU +GNU_FPOST_ATTR + static float rintf (float x) { volatile float TWO23 = 8388608.0; diff --git a/post/lib_ppc/fpu/20010226-1.c b/post/lib_ppc/fpu/20010226-1.c index b00386b18..099ca4a64 100644 --- a/post/lib_ppc/fpu/20010226-1.c +++ b/post/lib_ppc/fpu/20010226-1.c @@ -30,6 +30,8 @@ #if CONFIG_POST & CONFIG_SYS_POST_FPU +GNU_FPOST_ATTR + int fpu_post_test_math3 (void) { volatile long double dfrom = 1.1; diff --git a/post/lib_ppc/fpu/980619-1.c b/post/lib_ppc/fpu/980619-1.c index ceb2b76bf..46a31aec4 100644 --- a/post/lib_ppc/fpu/980619-1.c +++ b/post/lib_ppc/fpu/980619-1.c @@ -30,6 +30,8 @@ #if CONFIG_POST & CONFIG_SYS_POST_FPU +GNU_FPOST_ATTR + int fpu_post_test_math4 (void) { volatile float reale = 1.0f; diff --git a/post/lib_ppc/fpu/Makefile b/post/lib_ppc/fpu/Makefile index db435931d..a6815398e 100644 --- a/post/lib_ppc/fpu/Makefile +++ b/post/lib_ppc/fpu/Makefile @@ -29,4 +29,5 @@ COBJS-$(CONFIG_HAS_POST) += acc1.o compare-fp-1.o mul-subnormal-single-1.o include $(TOPDIR)/post/rules.mk +CFLAGS := $(shell echo $(CFLAGS) | sed s/-msoft-float//) CFLAGS += -mhard-float -fkeep-inline-functions diff --git a/post/lib_ppc/fpu/acc1.c b/post/lib_ppc/fpu/acc1.c index 8a6519383..9fca9b378 100644 --- a/post/lib_ppc/fpu/acc1.c +++ b/post/lib_ppc/fpu/acc1.c @@ -30,6 +30,8 @@ #if CONFIG_POST & CONFIG_SYS_POST_FPU +GNU_FPOST_ATTR + static double func (const double *array) { double d = *array; diff --git a/post/lib_ppc/fpu/compare-fp-1.c b/post/lib_ppc/fpu/compare-fp-1.c index ab476579e..f836b29c0 100644 --- a/post/lib_ppc/fpu/compare-fp-1.c +++ b/post/lib_ppc/fpu/compare-fp-1.c @@ -32,6 +32,8 @@ #if CONFIG_POST & CONFIG_SYS_POST_FPU +GNU_FPOST_ATTR + static int failed; #define TEST(c) if ((c) != ok) failed++ diff --git a/post/lib_ppc/fpu/fpu.c b/post/lib_ppc/fpu/fpu.c index 846b76d87..3f3adea19 100644 --- a/post/lib_ppc/fpu/fpu.c +++ b/post/lib_ppc/fpu/fpu.c @@ -40,6 +40,8 @@ #include +GNU_FPOST_ATTR + extern int fpu_status (void); extern void fpu_enable (void); extern void fpu_disable (void); diff --git a/post/lib_ppc/fpu/mul-subnormal-single-1.c b/post/lib_ppc/fpu/mul-subnormal-single-1.c index 9c514e116..1f3732d92 100644 --- a/post/lib_ppc/fpu/mul-subnormal-single-1.c +++ b/post/lib_ppc/fpu/mul-subnormal-single-1.c @@ -32,6 +32,8 @@ #if CONFIG_POST & CONFIG_SYS_POST_FPU +GNU_FPOST_ATTR + union uf { unsigned int u; From 68f8718df2ed4c2f43031407ccf6cfa81125dddc Mon Sep 17 00:00:00 2001 From: Brad Bozarth Date: Thu, 1 Jan 2009 22:45:47 -0500 Subject: [PATCH 186/188] spi flash: fix crash due to spi flash miscommunication Higher spi flash layers expect to be given back a pointer that was malloced so that it can free the result, but the lower layers return a pointer that is in the middle of the malloced memory. Reorder the members of the lower spi structures so that things work out. Signed-off-by: Brad Bozarth Signed-off-by: Mike Frysinger Acked-by: Haavard Skinnemoen --- drivers/mtd/spi/atmel.c | 3 ++- drivers/mtd/spi/stmicro.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/atmel.c b/drivers/mtd/spi/atmel.c index 10fcf0cdd..a5f51caf4 100644 --- a/drivers/mtd/spi/atmel.c +++ b/drivers/mtd/spi/atmel.c @@ -39,9 +39,10 @@ struct atmel_spi_flash_params { const char *name; }; +/* spi_flash needs to be first so upper layers can free() it */ struct atmel_spi_flash { - const struct atmel_spi_flash_params *params; struct spi_flash flash; + const struct atmel_spi_flash_params *params; }; static inline struct atmel_spi_flash * diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c index 86324e4e1..e7dda91a4 100644 --- a/drivers/mtd/spi/stmicro.c +++ b/drivers/mtd/spi/stmicro.c @@ -64,9 +64,10 @@ struct stmicro_spi_flash_params { const char *name; }; +/* spi_flash needs to be first so upper layers can free() it */ struct stmicro_spi_flash { - const struct stmicro_spi_flash_params *params; struct spi_flash flash; + const struct stmicro_spi_flash_params *params; }; static inline struct stmicro_spi_flash *to_stmicro_spi_flash(struct spi_flash From 7e4b9b4f6f43838fad3ad72c029a3d7fc7c7d48c Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Fri, 2 Jan 2009 20:47:45 -0500 Subject: [PATCH 187/188] fat: fix unaligned errors A couple of buffers in the fat code are declared as an array of bytes. But it is then cast up to a structure with 16bit and 32bit members. Since GCC assumes structure alignment here, we have to force the buffers to be aligned according to the structure usage. Signed-off-by: Bryan Wu Signed-off-by: Mike Frysinger --- fs/fat/fat.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index a9dde7def..28c7805d0 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -434,7 +434,8 @@ slot2str(dir_slot *slotptr, char *l_name, int *idx) * into 'retdent' * Return 0 on success, -1 otherwise. */ -__u8 get_vfatname_block[MAX_CLUSTSIZE]; +__attribute__ ((__aligned__(__alignof__(dir_entry)))) +__u8 get_vfatname_block[MAX_CLUSTSIZE]; static int get_vfatname(fsdata *mydata, int curclust, __u8 *cluster, dir_entry *retdent, char *l_name) @@ -520,6 +521,7 @@ mkcksum(const char *str) * Get the directory entry associated with 'filename' from the directory * starting at 'startsect' */ +__attribute__ ((__aligned__(__alignof__(dir_entry)))) __u8 get_dentfromdir_block[MAX_CLUSTSIZE]; static dir_entry *get_dentfromdir (fsdata * mydata, int startsect, char *filename, dir_entry * retdent, @@ -725,8 +727,8 @@ read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) return -1; } - -__u8 do_fat_read_block[MAX_CLUSTSIZE]; /* Block buffer */ +__attribute__ ((__aligned__(__alignof__(dir_entry)))) +__u8 do_fat_read_block[MAX_CLUSTSIZE]; long do_fat_read (const char *filename, void *buffer, unsigned long maxsize, int dols) From 24113a44ed5cd3257a0237c3961e121812fca6db Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 30 Dec 2008 03:15:38 -0500 Subject: [PATCH 188/188] easylogo: add optional gzip support Some images can be quite large, so add an option to compress the image data with gzip in the U-Boot image. Then at runtime, the board can decompress it with the normal zlib functions. Signed-off-by: Mike Frysinger --- tools/easylogo/easylogo.c | 98 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 92 insertions(+), 6 deletions(-) diff --git a/tools/easylogo/easylogo.c b/tools/easylogo/easylogo.c index 00a1e4ed1..41e583852 100644 --- a/tools/easylogo/easylogo.c +++ b/tools/easylogo/easylogo.c @@ -3,15 +3,19 @@ ** ============================== ** (C) 2000 by Paolo Scaffardi (arsenio@tin.it) ** AIRVENT SAM s.p.a - RIMINI(ITALY) +** (C) 2007-2008 Mike Frysinger ** ** This is still under construction! */ +#include #include #include #include #include #include +#include +#include #pragma pack(1) @@ -49,6 +53,17 @@ typedef struct { int width, height, pixels, bpp, pixel_size, size, palette_size, yuyv; } image_t; +void *xmalloc (size_t size) +{ + void *ret = malloc (size); + if (!ret) { + fprintf (stderr, "\nerror: malloc(%zu) failed: %s", + size, strerror(errno)); + exit (1); + } + return ret; +} + void StringUpperCase (char *str) { int count = strlen (str); @@ -171,7 +186,7 @@ int image_load_tga (image_t * image, char *filename) image->pixel_size = ((image->bpp - 1) / 8) + 1; image->pixels = image->width * image->height; image->size = image->pixels * image->pixel_size; - image->data = malloc (image->size); + image->data = xmalloc (image->size); if (image->bpp != 24) { printf ("Bpp not supported: %d!\n", image->bpp); @@ -192,7 +207,7 @@ int image_load_tga (image_t * image, char *filename) /* Swapping image */ if (!(header.ImageDescriptorByte & 0x20)) { - unsigned char *temp = malloc (image->size); + unsigned char *temp = xmalloc (image->size); int linesize = image->pixel_size * image->width; void *dest = image->data, *source = temp + image->size - linesize; @@ -239,7 +254,7 @@ int image_rgb_to_yuyv (image_t * rgb_image, image_t * yuyv_image) yuyv_image->pixels = yuyv_image->width * yuyv_image->height; yuyv_image->size = yuyv_image->pixels * yuyv_image->pixel_size; dest = (unsigned short *) (yuyv_image->data = - malloc (yuyv_image->size)); + xmalloc (yuyv_image->size)); yuyv_image->palette = 0; yuyv_image->palette_size = 0; @@ -261,6 +276,8 @@ int image_rgb_to_yuyv (image_t * rgb_image, image_t * yuyv_image) return 0; } +int use_gzip = 0; + int image_save_header (image_t * image, char *filename, char *varname) { FILE *file = fopen (filename, "w"); @@ -283,6 +300,65 @@ int image_save_header (image_t * image, char *filename, char *varname) fprintf (file, " *\t\t'x'\t\tis the horizontal position\n"); fprintf (file, " *\t\t'y'\t\tis the vertical position\n */\n\n"); + /* gzip compress */ + if (use_gzip & 0x1) { + const char *errstr = NULL; + unsigned char *compressed; + struct stat st; + FILE *gz; + char *gzfilename = xmalloc(strlen (filename) + 20); + char *gzcmd = xmalloc(strlen (filename) + 20); + + sprintf (gzfilename, "%s.gz", filename); + sprintf (gzcmd, "gzip > %s", gzfilename); + gz = popen (gzcmd, "w"); + if (!gz) { + errstr = "\nerror: popen() failed"; + goto done; + } + if (fwrite (image->data, image->size, 1, gz) != 1) { + errstr = "\nerror: writing data to gzip failed"; + goto done; + } + if (pclose (gz)) { + errstr = "\nerror: gzip process failed"; + goto done; + } + + gz = fopen (gzfilename, "r"); + if (!gz) { + errstr = "\nerror: open() on gzip data failed"; + goto done; + } + if (stat (gzfilename, &st)) { + errstr = "\nerror: stat() on gzip file failed"; + goto done; + } + compressed = xmalloc (st.st_size); + if (fread (compressed, st.st_size, 1, gz) != 1) { + errstr = "\nerror: reading gzip data failed"; + goto done; + } + fclose (gz); + + unlink (gzfilename); + + dataptr = compressed; + count = st.st_size; + fprintf (file, "#define EASYLOGO_ENABLE_GZIP %i\n\n", count); + if (use_gzip & 0x2) + fprintf (file, "static unsigned char EASYLOGO_DECOMP_BUFFER[%i];\n\n", image->size); + + done: + free (gzfilename); + free (gzcmd); + + if (errstr) { + perror (errstr); + return -1; + } + } + /* Headers */ fprintf (file, "#include \n\n"); /* Macros */ @@ -300,8 +376,8 @@ int image_save_header (image_t * image, char *filename, char *varname) fprintf (file, "#define DEF_%s_SIZE\t\t%d\n\n", def_name, image->size); /* Declaration */ - fprintf (file, "unsigned char DEF_%s_DATA[DEF_%s_SIZE] = {\n", - def_name, def_name); + fprintf (file, "unsigned char DEF_%s_DATA[] = {\n", + def_name); /* Data */ while (count) @@ -359,6 +435,8 @@ static void usage (int exit_status) "\n" "Options:\n" " -r Output RGB instead of YUYV\n" + " -g Compress with gzip\n" + " -b Preallocate space in bss for decompressing image\n" " -h Help output\n" "\n" "Where: 'inputfile' is the TGA image to load\n" @@ -377,7 +455,7 @@ int main (int argc, char *argv[]) image_t rgb_logo, yuyv_logo; - while ((c = getopt(argc, argv, "hr")) > 0) { + while ((c = getopt(argc, argv, "hrgb")) > 0) { switch (c) { case 'h': usage (0); @@ -386,6 +464,14 @@ int main (int argc, char *argv[]) use_rgb = true; puts ("Using 24-bit RGB Output Fromat"); break; + case 'g': + use_gzip |= 0x1; + puts ("Compressing with gzip"); + break; + case 'b': + use_gzip |= 0x2; + puts ("Preallocating bss space for decompressing image"); + break; default: usage (1); break;