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[PATCH] Update ALPR board files

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This update brings the ALPR board support to the newest version.
It also fixes a problem with the NAND driver.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-01-06 15:56:13 +01:00
parent cd1d937f90
commit f16c1da957
3 changed files with 29 additions and 21 deletions
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27
board/prodrive/alpr/alpr.c
View File

@ -77,8 +77,12 @@ int board_early_init_f (void)
mtdcr (uicb0tr, 0x00000000); /* */ mtdcr (uicb0tr, 0x00000000); /* */
mtdcr (uicb0vr, 0x00000001); /* */ mtdcr (uicb0vr, 0x00000001); /* */
/* Setup shutdown/SSD empty interrupt as inputs */
out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
/* Setup GPIO/IRQ multiplexing */ /* Setup GPIO/IRQ multiplexing */
mtsdr(sdr_pfc0, 0x01a03e00); mtsdr(sdr_pfc0, 0x01a33e00);
return 0; return 0;
} }
@ -105,26 +109,11 @@ int last_stage_init(void)
static int board_rev(void) static int board_rev(void)
{ {
int rev;
u32 pfc0;
/* Setup GPIO14 & 15 as GPIO */
mfsdr(sdr_pfc0, pfc0);
pfc0 |= CFG_GPIO_REV0 | CFG_GPIO_REV1;
mtsdr(sdr_pfc0, pfc0);
/* Setup as input */ /* Setup as input */
out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0)); out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0)); out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
rev = (in32(GPIO0_IR) >> 16) & 0x3; return (in32(GPIO0_IR) >> 16) & 0x3;
/* Setup GPIO14 & 15 as non GPIO again */
mfsdr(sdr_pfc0, pfc0);
pfc0 &= ~(CFG_GPIO_REV0 | CFG_GPIO_REV1);
mtsdr(sdr_pfc0, pfc0);
return rev;
} }
int checkboard (void) int checkboard (void)

4
board/prodrive/alpr/nand.c
View File

@ -154,7 +154,7 @@ static int alpr_nand_dev_ready(struct mtd_info *mtd)
return 1; return 1;
} }
void board_nand_init(struct nand_chip *nand) int board_nand_init(struct nand_chip *nand)
{ {
alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE; alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE;
@ -169,5 +169,7 @@ void board_nand_init(struct nand_chip *nand)
nand->read_buf = alpr_nand_read_buf; nand->read_buf = alpr_nand_read_buf;
nand->verify_buf = alpr_nand_verify_buf; nand->verify_buf = alpr_nand_verify_buf;
nand->dev_ready = alpr_nand_dev_ready; nand->dev_ready = alpr_nand_dev_ready;
return 0;
} }
#endif #endif

19
include/configs/alpr.h
View File

@ -166,8 +166,23 @@
"cp.b 100000 fffc0000 40000;" \ "cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \ "setenv filesize;saveenv\0" \
"upd=run load;run update\0" \ "upd=run load;run update\0" \
"ethprime=ppc_4xx_eth3\0" \
"ethact=ppc_4xx_eth3\0" \
"autoload=no\0" \
"ipconfig=dhcp;setenv serverip 11.0.0.152\0" \
"actkernel=kernel2\0" \
"load_fpga=fpga load 0 ffe00000 10dd9a\0" \
"mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \
"rootfstype=jffs2 init=/sbin/init\0" \
"kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
";bootm 200000\0" \
"kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \
"addtty;bootm 200000\0" \
"kernel1=run ipconfig load_fpga kernel1_mtd\0" \
"kernel2=run ipconfig load_fpga kernel2_mtd\0" \
"" ""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_BOOTCOMMAND "run kernel2"
#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ #define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
@ -291,6 +306,8 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Definitions for GPIO setup * Definitions for GPIO setup
*-----------------------------------------------------------------------*/ *-----------------------------------------------------------------------*/
#define CFG_GPIO_SHUTDOWN (0x80000000 >> 6)
#define CFG_GPIO_SSD_EMPTY (0x80000000 >> 9)
#define CFG_GPIO_EREADY (0x80000000 >> 26) #define CFG_GPIO_EREADY (0x80000000 >> 26)
#define CFG_GPIO_REV0 (0x80000000 >> 14) #define CFG_GPIO_REV0 (0x80000000 >> 14)
#define CFG_GPIO_REV1 (0x80000000 >> 15) #define CFG_GPIO_REV1 (0x80000000 >> 15)