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Prepare for release 1.2.0
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Wolfgang Denk
Wolfgang Denk
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f07ae7a9da
commit
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121
CHANGELOG
121
CHANGELOG
@ -1,3 +1,124 @@
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commit f07ae7a9daef27a3d0213a4f3fe39d5342173c02
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Author: Stefan Roese <sr@denx.de>
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Date: Sat Jan 6 15:58:09 2007 +0100
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[PATCH] 44x: Fix problem with DDR controller setup (refresh rate)
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This patch fixes a problem with an incorrect setup for the refresh
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timer of the 44x DDR controller in the file cpu/ppc4xx/sdram.c
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Signed-off-by: Stefan Roese <sr@denx.de>
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commit f16c1da9577f06c5fc08651a4065537407de4635
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Author: Stefan Roese <sr@denx.de>
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Date: Sat Jan 6 15:56:13 2007 +0100
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[PATCH] Update ALPR board files
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This update brings the ALPR board support to the newest version.
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It also fixes a problem with the NAND driver.
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Signed-off-by: Stefan Roese <sr@denx.de>
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commit cd1d937f90250a32988c37b2b4af8364d25de8ed
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Author: Stefan Roese <sr@denx.de>
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Date: Fri Jan 5 11:46:05 2007 +0100
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[PATCH] nand: Fix problem with oobsize calculation
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Here the description from Brian Brelsford <Brian_Brelsford@dell.com>:
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The Hynix part returns a 0x1d in the 4th ID byte. The Samsung part
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returns a 0x15. In the code fragment below bits [1:0] determine the
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page size, it is ANDed via "(extid & 0x3)" then shifted out. The
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next field is also ANDed with 0x3. However this is a one bit field
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as defined in the Hynix and Samsung parts in the 4th ID byte that
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determins the oobsize, not a two bit field. It works on Samsung as
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bits[3:2] are 01. However for the Hynix there is a 11 in these two
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bits, so the oob size gets messed up.
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I checked the correct linux code and the suggested fix from Brian is
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also available in the linux nand mtd driver.
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Signed-off-by: Stefan Roese <sr@denx.de>
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commit a78bc443ae5a4a8ba87590587d5e35bf5a787b2e
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Author: Stefan Roese <sr@denx.de>
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Date: Fri Jan 5 10:40:36 2007 +0100
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[PATCH] Clear PLB4A0_ACR[WRP] on Sequoia (440EPx)
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This fix will make the MAL burst disabling patch for the Linux
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EMAC driver obsolete.
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Signed-off-by: Stefan Roese <sr@denx.de>
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commit 023889838282b6237b401664f22dd22dfba2c066
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Author: Stefan Roese <sr@denx.de>
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Date: Fri Jan 5 10:38:05 2007 +0100
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[PATCH] Add DDR2 optimization code for Sequoia (440EPx) board
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This code will optimize the DDR2 controller setup on a board specific
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basis.
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Note: This code doesn't work right now on the NAND booting image for the
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Sequoia board, since it doesn't fit into the 4kBytes for the SPL image.
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Signed-off-by: Stefan Roese <sr@denx.de>
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commit cce4acbb68398634b8d011ed7bb0d12269c84230
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Author: Bartlomiej Sieka <tur@semihalf.com>
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Date: Thu Dec 28 19:08:21 2006 +0100
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Few V38B changes:
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- fix a typo in V38B config file
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- move watchdog initialisation earlier in the boot process
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- add "wdt=off" to default kernel command line (disables kernel watchdog)
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commit 92eb729bad876725aeea908d2addba0800620840
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Author: Wolfgang Denk <wd@pollux.denx.de>
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Date: Wed Dec 27 01:26:13 2006 +0100
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Fix bug in adaption of Stefano Babic's CFI driver patch.
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commit 9c0f42ecfe25f7ffce8ec7a815f03864d723ffe3
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Author: Wolfgang Denk <wd@pollux.denx.de>
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Date: Sun Dec 24 01:42:57 2006 +0100
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Minor code cleanup.
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commit d784fdb05900ada3686d5778783e1fb328e9fb66
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Author: Stefano Babic <sbabic@denx.de>
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Date: Tue Dec 12 00:22:42 2006 +0100
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Fix cfi failure with Spansion Flash (Spansion Flash Devices have a different offset to go into CFI mode)
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commit 1b3c360c235dc684ec06c2d5f183f0a282ce45e2
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Author: Stefan Roese <sr@denx.de>
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Date: Fri Dec 22 14:29:40 2006 +0100
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[PATCH] Fix sequoia flash autodetection (finally correct)
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Now 32MByte and 64MByte FLASH is know to work and other
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configurations should work too.
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Signed-off-by: Stefan Roese <sr@denx.de>
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commit 82e5236a8b719543643fd26d5827938ab2b94818
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Author: Wolfgang Denk <wd@pollux.denx.de>
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Date: Fri Dec 22 10:30:26 2006 +0100
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Minor code cleanup; update CHANGELOG.
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commit fa23044564091f05d9695beb7b5b9a931e7f41a4
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Author: Heiko Schocher <hs@pollux.denx.de>
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Date: Thu Dec 21 17:17:02 2006 +0100
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Added support for the TQM8272 board from TQ
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Signed-off-by: Heiko Schocher <hs@denx.de>
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commit c84bad0ef60e7055ab0bd49b93069509cecc382a
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Author: Bartlomiej Sieka <tur@semihalf.com>
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Date: Wed Dec 20 00:29:43 2006 +0100
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