cosmetic changes to bcm570x driver

This is a cosmetic only changes submission.
It affects files relevant to bcm570x driver.
the commands used to generate this change was

cd drivers
Lindent -pcs -l80  bcm570x.c   bcm570x_lm.h   bcm570x_mm.h  tigon3.c  tigon3.h

The BMW target (the only one using this chip so far) builds cleanly, the
`before and after' generated object files for drivers/bcm570x.c and
drivers/tigon3.o are identical as reported by objdump -d

Signed-off-by: Vadim Bendebury <vbendeb@google.com>
Signed-off-by: Ben Warren <bwarren@qstreams.com>

drivers/bcm570x_lm.h

@@ -19,7 +19,6 @@
 #include "bcm570x_queue.h"
 #include "bcm570x_bits.h"
 
-
 /******************************************************************************/
 /* Basic types. */
 /******************************************************************************/
@@ -58,7 +57,6 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
 	}                                                   \
     }
 
-
 #ifndef NULL
 #define NULL                ((void *) 0)
 #endif				/* NULL */
@@ -67,7 +65,6 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
 #define OFFSETOF(_s, _m)    (MM_UINT_PTR(&(((_s *) 0)->_m)))
 #endif				/* OFFSETOF */
 
-
 /******************************************************************************/
 /* Simple macros. */
 /******************************************************************************/
@@ -100,7 +97,6 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
     ((unsigned char *) (_Dst))[4] = ((unsigned char *) (_Src))[4];          \
     ((unsigned char *) (_Dst))[5] = ((unsigned char *) (_Src))[5];
 
-
 /******************************************************************************/
 /* Constants. */
 /******************************************************************************/
@@ -119,7 +115,6 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
 #define LM_MC_ENTRY_SIZE                (ETHERNET_ADDRESS_SIZE+1)
 #define LM_MC_INSTANCE_COUNT_INDEX      (LM_MC_ENTRY_SIZE-1)
 
-
 /* Receive filter masks. */
 #define LM_ACCEPT_UNICAST               0x0001
 #define LM_ACCEPT_MULTICAST             0x0002
@@ -129,7 +124,6 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
 
 #define LM_PROMISCUOUS_MODE             0x10000
 
-
 /******************************************************************************/
 /* PCI registers. */
 /******************************************************************************/
@@ -191,7 +185,6 @@ typedef struct {
 	LM_FRAG FragListBuffer[_MAX_FRAG_COUNT-1];                           \
     } _FRAG_LIST_TYPE_NAME, *P##_FRAG_LIST_TYPE_NAME
 
-
 /******************************************************************************/
 /* Status codes. */
 /******************************************************************************/
@@ -217,7 +210,6 @@ typedef struct {
 
 typedef LM_UINT LM_STATUS, *PLM_STATUS;
 
-
 /******************************************************************************/
 /* Requested media type. */
 /******************************************************************************/
@@ -240,7 +232,6 @@ typedef LM_UINT LM_STATUS, *PLM_STATUS;
 
 typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE;
 
-
 /******************************************************************************/
 /* Media type. */
 /******************************************************************************/
@@ -254,7 +245,6 @@ typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE;
 
 typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE;
 
-
 /******************************************************************************/
 /* Line speed. */
 /******************************************************************************/
@@ -266,7 +256,6 @@ typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE;
 
 typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED;
 
-
 /******************************************************************************/
 /* Duplex mode. */
 /******************************************************************************/
@@ -277,7 +266,6 @@ typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED;
 
 typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE;
 
-
 /******************************************************************************/
 /* Power state. */
 /******************************************************************************/
@@ -289,7 +277,6 @@ typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE;
 
 typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE;
 
-
 /******************************************************************************/
 /* Task offloading. */
 /******************************************************************************/
@@ -305,7 +292,6 @@ typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE;
 
 typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD;
 
-
 /******************************************************************************/
 /* Flow control. */
 /******************************************************************************/
@@ -324,7 +310,6 @@ typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD;
 
 typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL;
 
-
 /******************************************************************************/
 /* Wake up mode. */
 /******************************************************************************/
@@ -336,7 +321,6 @@ typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL;
 
 typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE;
 
-
 /******************************************************************************/
 /* Counters. */
 /******************************************************************************/
@@ -362,7 +346,6 @@ typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE;
 
 typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE;
 
-
 /******************************************************************************/
 /* Forward definition. */
 /******************************************************************************/
@@ -370,7 +353,6 @@ typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE;
 typedef struct _LM_DEVICE_BLOCK *PLM_DEVICE_BLOCK;
 typedef struct _LM_PACKET *PLM_PACKET;
 
-
 /******************************************************************************/
 /* Function prototypes. */
 /******************************************************************************/
@@ -399,7 +381,8 @@ LM_STATUS LM_NwufAdd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
 		      LM_UINT8 * pByteMask, LM_UINT8 * pPattern);
 LM_STATUS LM_NwufRemove (PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
 			 LM_UINT8 * pByteMask, LM_UINT8 * pPattern);
-LM_STATUS LM_SetPowerState(PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel);
+LM_STATUS LM_SetPowerState (PLM_DEVICE_BLOCK pDevice,
+			    LM_POWER_STATE PowerLevel);
 
 LM_VOID LM_ReadPhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg,
 		    PLM_UINT32 pData32);
@@ -410,7 +393,6 @@ LM_STATUS LM_ControlLoopBack(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Control);
 LM_STATUS LM_SetupPhy (PLM_DEVICE_BLOCK pDevice);
 int LM_BlinkLED (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDuration);
 
-
 /******************************************************************************/
 /* These are the OS specific functions called by LMAC. */
 /******************************************************************************/
@@ -431,8 +413,10 @@ LM_STATUS MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
 LM_STATUS MM_CompleteTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
 LM_STATUS MM_AllocateMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
 			     PLM_VOID * pMemoryBlockVirt);
-LM_STATUS MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
+LM_STATUS MM_AllocateSharedMemory (PLM_DEVICE_BLOCK pDevice,
-    PLM_VOID *pMemoryBlockVirt, PLM_PHYSICAL_ADDRESS pMemoryBlockPhy,
+				   LM_UINT32 BlockSize,
+				   PLM_VOID * pMemoryBlockVirt,
+				   PLM_PHYSICAL_ADDRESS pMemoryBlockPhy,
 				   LM_BOOL Cached);
 LM_STATUS MM_GetConfig (PLM_DEVICE_BLOCK pDevice);
 LM_STATUS MM_IndicateStatus (PLM_DEVICE_BLOCK pDevice, LM_STATUS Status);
@@ -447,5 +431,4 @@ LM_STATUS LM_SetLinkSpeed(PLM_DEVICE_BLOCK pDevice,
 LM_STATUS LM_Load5703DmaWFirmware (PLM_DEVICE_BLOCK pDevice);
 #endif
 
-
 #endif				/* LM_H */

drivers/bcm570x_mm.h

@@ -109,7 +109,6 @@ typedef struct _UM_DEVICE_BLOCK {
 	unsigned int rx_misc_errors;	/* new -- unsupported */
 } UM_DEVICE_BLOCK, *PUM_DEVICE_BLOCK;
 
-
 /* Physical/PCI DMA address */
 typedef union {
 	dma_addr_t dma_map;
@@ -146,7 +145,6 @@ extern void MM_MapRxDma ( PLM_DEVICE_BLOCK pDevice,
 			 struct _LM_PACKET *pPacket,
 			 T3_64BIT_HOST_ADDR * paddr);
 
-
 /* BSP needs to provide sysUsecDelay and sysSerialPrintString */
 extern void sysSerialPrintString (char *s);
 #define MM_Wait(usec) udelay(usec)

drivers/tigon3.h

@@ -21,7 +21,6 @@
 #include "bcm570x_autoneg.h"
 #endif
 
-
 /* io defines */
 #if !defined(BIG_ENDIAN_HOST)
 #define readl(addr) \
@@ -38,24 +37,27 @@
 #define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
 #else
 extern int sprintf (char *buf, const char *f, ...);
-static __inline unsigned int readl(void* addr){
+static __inline unsigned int readl (void *addr)
+{
 	char buf[128];
 	unsigned int tmp = (*(volatile unsigned int *)(addr));
-    sprintf(buf,"%s:%s: read 0x%x from 0x%x\n",__FILE__,__LINE__,tmp,addr,0,0);
+	sprintf (buf, "%s:%s: read 0x%x from 0x%x\n", __FILE__, __LINE__, tmp,
+		 addr, 0, 0);
 	sysSerialPrintString (buf);
 	return tmp;
 }
-static __inline void writel(unsigned int b, unsigned int addr){
+static __inline void writel (unsigned int b, unsigned int addr)
+{
 	char buf[128];
 	((*(volatile unsigned int *)(addr)) = (b));
-    sprintf(buf,"%s:%s: write 0x%x to 0x%x\n",__FILE__,__LINE__,b,addr,0,0);
+	sprintf (buf, "%s:%s: write 0x%x to 0x%x\n", __FILE__, __LINE__, b,
+		 addr, 0, 0);
 	sysSerialPrintString (buf);
 }
 #endif
 #endif				/* PPC603 */
 #endif
 
-
 /******************************************************************************/
 /* Constants. */
 /******************************************************************************/
@@ -198,7 +200,6 @@ static __inline void writel(unsigned int b, unsigned int addr){
 #endif				/* T3_RCV_RETURN_RCB_ENTRY_COUNT */
 #define T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK  (T3_RCV_RETURN_RCB_ENTRY_COUNT-1)
 
-
 /* Default coalescing parameters. */
 #define DEFAULT_RX_COALESCING_TICKS         100
 #define MAX_RX_COALESCING_TICKS             500
@@ -227,7 +228,6 @@ static __inline void writel(unsigned int b, unsigned int addr){
 #define DEFAULT_STATS_COALESCING_TICKS      1000000
 #define MAX_STATS_COALESCING_TICKS          3600000000U
 
-
 /* Receive BD Replenish thresholds. */
 #define DEFAULT_RCV_STD_BD_REPLENISH_THRESHOLD      4
 #define DEFAULT_RCV_JUMBO_BD_REPLENISH_THRESHOLD    4
@@ -240,12 +240,10 @@ static __inline void writel(unsigned int b, unsigned int addr){
 /* Maximum physical fragment size. */
 #define MAX_FRAGMENT_SIZE                   (64 * 1024)
 
-
 /* Standard view. */
 #define T3_STD_VIEW_SIZE                    (64 * 1024)
 #define T3_FLAT_VIEW_SIZE                   (32 * 1024 * 1024)
 
-
 /* Buffer descriptor base address on the NIC's memory. */
 
 #define T3_NIC_SND_BUFFER_DESC_ADDR         0x4000
@@ -265,14 +263,12 @@ static __inline void writel(unsigned int b, unsigned int addr){
 #define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE   (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \
 					    sizeof(T3_EXT_RCV_BD) / 4)
 
-
 /* MBUF pool. */
 #define T3_NIC_MBUF_POOL_ADDR               0x8000
 /* #define T3_NIC_MBUF_POOL_SIZE               0x18000 */
 #define T3_NIC_MBUF_POOL_SIZE96             0x18000
 #define T3_NIC_MBUF_POOL_SIZE64             0x10000
 
-
 #define T3_NIC_MBUF_POOL_ADDR_EXT_MEM       0x20000
 
 /* DMA descriptor pool */
@@ -301,15 +297,13 @@ static __inline void writel(unsigned int b, unsigned int addr){
 #define T3_TX_CPU_SPAD_ADDR  0x34000
 #define T3_TX_CPU_SPAD_SIZE  0x4000
 
-typedef struct T3_DIR_ENTRY
+typedef struct T3_DIR_ENTRY {
-{
 	PLM_UINT8 Buffer;
 	LM_UINT32 Offset;
 	LM_UINT32 Length;
 } T3_DIR_ENTRY, *PT3_DIR_ENTRY;
 
-typedef struct T3_FWIMG_INFO
+typedef struct T3_FWIMG_INFO {
-{
 	LM_UINT32 StartAddress;
 	T3_DIR_ENTRY Text;
 	T3_DIR_ENTRY ROnlyData;
@@ -318,7 +312,6 @@ typedef struct T3_FWIMG_INFO
 	T3_DIR_ENTRY Bss;
 } T3_FWIMG_INFO, *PT3_FWIMG_INFO;
 
-
 /******************************************************************************/
 /* Tigon3 PCI Registers. */
 /******************************************************************************/
@@ -362,7 +355,6 @@ typedef struct T3_FWIMG_INFO
 #define T3_ASIC_REV_5703                    0x01
 #define T3_ASIC_REV_5704                    0x02
 
-
 /* Chip id and revision. */
 #define T3_CHIP_REV(_ChipRevId)             ((_ChipRevId) >> 8)
 #define T3_CHIP_REV_5700_AX                 0x70
@@ -386,7 +378,6 @@ typedef struct T3_FWIMG_INFO
 #define T3_PCI_POWER_DOWN_PCI_PLL133        BIT_15
 #define T3_PCI_44MHZ_CORE_CLOCK             BIT_18
 
-
 #define T3_PCI_REG_ADDR_REG                 0x78
 #define T3_PCI_REG_DATA_REG                 0x80
 
@@ -409,7 +400,6 @@ typedef struct T3_FWIMG_INFO
 #define T3_PM_PME_ENABLE                    BIT_8
 #define T3_PM_PME_ASSERTED                  BIT_15
 
-
 /* PCI state register. */
 #define T3_PCI_STATE_REG                    0x70
 
@@ -419,7 +409,6 @@ typedef struct T3_FWIMG_INFO
 #define T3_PCI_STATE_BUS_SPEED_HIGH         BIT_3
 #define T3_PCI_STATE_32BIT_PCI_BUS          BIT_4
 
-
 /* Broadcom subsystem/subvendor IDs. */
 #define T3_SVID_BROADCOM                            0x14e4
 
@@ -449,7 +438,6 @@ typedef struct T3_FWIMG_INFO
 #define T3_SSID_3COM_3C996SX                        0x1004
 #define T3_SSID_3COM_3C997SX                        0x1005
 
-
 /* Dell subsystem/subvendor IDs. */
 
 #define T3_SVID_DELL                                0x1028
@@ -469,7 +457,6 @@ typedef struct T3_FWIMG_INFO
 #define T3_SSID_COMPAQ_NC7780                       0x0085
 #define T3_SSID_COMPAQ_NC7780_2                     0x0099
 
-
 /******************************************************************************/
 /* MII registers. */
 /******************************************************************************/
@@ -490,14 +477,12 @@ typedef struct T3_FWIMG_INFO
 #define PHY_CTRL_LOOPBACK_MODE                      BIT_14
 #define PHY_CTRL_PHY_RESET                          BIT_15
 
-
 /* Status register. */
 #define PHY_STATUS_REG                              0x01
 
 #define PHY_STATUS_LINK_PASS                        BIT_2
 #define PHY_STATUS_AUTO_NEG_COMPLETE                BIT_5
 
-
 /* Phy Id registers. */
 #define PHY_ID1_REG                                 0x02
 #define PHY_ID1_OUI_MASK                            0xffff
@@ -507,7 +492,6 @@ typedef struct T3_FWIMG_INFO
 #define PHY_ID2_MODEL_MASK                          0x03f0
 #define PHY_ID2_OUI_MASK                            0xfc00
 
-
 /* Auto-negotiation advertisement register. */
 #define PHY_AN_AD_REG                               0x04
 
@@ -519,18 +503,15 @@ typedef struct T3_FWIMG_INFO
 #define PHY_AN_AD_100BASETX_FULL                    BIT_8
 #define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD            0x01
 
-
 /* Auto-negotiation Link Partner Ability register. */
 #define PHY_LINK_PARTNER_ABILITY_REG                0x05
 
 #define PHY_LINK_PARTNER_ASYM_PAUSE                 BIT_11
 #define PHY_LINK_PARTNER_PAUSE_CAPABLE              BIT_10
 
-
 /* Auto-negotiation expansion register. */
 #define PHY_AN_EXPANSION_REG                        0x06
 
-
 /******************************************************************************/
 /* BCM5400 and BCM5401 phy info. */
 /******************************************************************************/
@@ -557,7 +538,6 @@ typedef struct T3_FWIMG_INFO
 #define PHY_ID_MASK                                 (PHY_ID_OUI_MASK |      \
 						    PHY_ID_MODEL_MASK)
 
-
 #define UNKNOWN_PHY_ID(x)   ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \
 			    (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \
 			    (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \
@@ -566,7 +546,6 @@ typedef struct T3_FWIMG_INFO
 			    (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \
 			    (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID))
 
-
 /* 1000Base-T control register. */
 #define BCM540X_1000BASET_CTRL_REG                  0x09
 
@@ -575,7 +554,6 @@ typedef struct T3_FWIMG_INFO
 #define BCM540X_CONFIG_AS_MASTER                    BIT_11
 #define BCM540X_ENABLE_CONFIG_AS_MASTER             BIT_12
 
-
 /* Extended control register. */
 #define BCM540X_EXT_CTRL_REG                        0x10
 
@@ -587,11 +565,9 @@ typedef struct T3_FWIMG_INFO
 
 #define BCM540X_EXT_STATUS_LINK_PASS                BIT_8
 
-
 /* DSP Coefficient Read/Write Port. */
 #define BCM540X_DSP_RW_PORT                         0x15
 
-
 /* DSP Coeficient Address Register. */
 #define BCM540X_DSP_ADDRESS_REG                     0x17
 
@@ -631,7 +607,6 @@ typedef struct T3_FWIMG_INFO
 
 #define BCM540X_CONTROL_ALL_CHANNELS                BIT_15
 
-
 /* Auxilliary Control Register (Shadow Register) */
 #define BCM5401_AUX_CTRL                            0x18
 
@@ -644,7 +619,6 @@ typedef struct T3_FWIMG_INFO
 #define BCM5401_SHADOW_SEL_MISC_TEST2               0x05
 #define BCM5401_SHADOW_SEL_IP_PHONE_SEED            0x06
 
-
 /* Shadow register selector == '000' */
 #define BCM5401_SHDW_NORMAL_DIAG_MODE               BIT_3
 #define BCM5401_SHDW_NORMAL_DISABLE_MBP             BIT_4
@@ -664,7 +638,6 @@ typedef struct T3_FWIMG_INFO
 #define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH       BIT_14
 #define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK       BIT_15
 
-
 /* Auxilliary status summary. */
 #define BCM540X_AUX_STATUS_REG                      0x19
 
@@ -678,7 +651,6 @@ typedef struct T3_FWIMG_INFO
 #define BCM540X_AUX_100BASET_HD                     (BIT_9 | BIT_10)
 #define BCM540X_AUX_100BASET_FD                     (BIT_8 | BIT_9 | BIT_10)
 
-
 /* Interrupt status. */
 #define BCM540X_INT_STATUS_REG                      0x1a
 
@@ -687,11 +659,9 @@ typedef struct T3_FWIMG_INFO
 #define BCM540X_INT_DUPLEX_CHANGE                   BIT_3
 #define BCM540X_INT_AUTO_NEG_PAGE_RX                BIT_10
 
-
 /* Interrupt mask register. */
 #define BCM540X_INT_MASK_REG                        0x1b
 
-
 /******************************************************************************/
 /* Register definitions. */
 /******************************************************************************/
@@ -711,8 +681,7 @@ typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR;
 #define T3_NUM_OF_DMA_DESC    256
 #define T3_NUM_OF_MBUF        768
 
-typedef struct
+typedef struct {
-{
 	T3_64BIT_REGISTER host_addr;
 	T3_32BIT_REGISTER nic_mbuf;
 	T3_16BIT_REGISTER len;
@@ -723,7 +692,6 @@ typedef struct
 	T3_32BIT_REGISTER opaque3;
 } T3_DMA_DESC, *PT3_DMA_DESC;
 
-
 /******************************************************************************/
 /* Ring control block. */
 /******************************************************************************/
@@ -751,7 +719,6 @@ typedef struct {
 #define T3_RCB_FLAG_USE_EXT_RECV_BD                     BIT_0
 #define T3_RCB_FLAG_RING_DISABLED                       BIT_1
 
-
 /******************************************************************************/
 /* Status block. */
 /******************************************************************************/
@@ -795,7 +762,6 @@ typedef struct {
 #endif
 } T3_STATUS_BLOCK, *PT3_STATUS_BLOCK;
 
-
 /******************************************************************************/
 /* Receive buffer descriptors. */
 /******************************************************************************/
@@ -833,7 +799,6 @@ typedef struct {
 	volatile LM_UINT32 Opaque;
 } T3_RCV_BD, *PT3_RCV_BD;
 
-
 typedef struct {
 	T3_64BIT_HOST_ADDR HostAddr[3];
 
@@ -854,7 +819,6 @@ typedef struct {
 	T3_RCV_BD StdRcvBd;
 } T3_EXT_RCV_BD, *PT3_EXT_RCV_BD;
 
-
 /* Error flags. */
 #define RCV_BD_ERR_BAD_CRC                          0x0001
 #define RCV_BD_ERR_COLL_DETECT                      0x0002
@@ -866,7 +830,6 @@ typedef struct {
 #define RCV_BD_ERR_TRUNC_NO_RESOURCES               0x0080
 #define RCV_BD_ERR_GIANT_FRAME_RCVD                 0x0100
 
-
 /* Buffer descriptor flags. */
 #define RCV_BD_FLAG_END                             0x0004
 #define RCV_BD_FLAG_JUMBO_RING                      0x0020
@@ -877,7 +840,6 @@ typedef struct {
 #define RCV_BD_FLAG_TCP_UDP_CHKSUM_FIELD            0x2000
 #define RCV_BD_FLAG_TCP_PACKET                      0x4000
 
-
 /******************************************************************************/
 /* Send buffer descriptor. */
 /******************************************************************************/
@@ -914,7 +876,6 @@ typedef struct {
 	} u2;
 } T3_SND_BD, *PT3_SND_BD;
 
-
 /* Send buffer descriptor flags. */
 #define SND_BD_FLAG_TCP_UDP_CKSUM                   0x0001
 #define SND_BD_FLAG_IP_CKSUM                        0x0002
@@ -942,8 +903,7 @@ typedef struct T3_MBUF_FRAME_DESC {
 		LM_UINT32 word;
 	} u1;
 	union {
-    struct
+		struct {
-    {
 			LM_UINT16 ip_hdr_start;
 			LM_UINT16 tcp_udp_hdr_start;
 		} s2;
@@ -1010,8 +970,7 @@ typedef struct T3_MBUF_FRAME_DESC {
 		LM_UINT32 word;
 	} u1;
 	union {
-    struct
+		struct {
-    {
 			LM_UINT16 tcp_udp_hdr_start;
 			LM_UINT16 ip_hdr_start;
 		} s2;
@@ -1086,11 +1045,9 @@ typedef struct T3_MBUF_HDR {
 	LM_UINT32 next_frame_ptr;
 } T3_MBUF_HDR, *PT3_MBUF_HDR;
 
-typedef struct T3_MBUF
+typedef struct T3_MBUF {
-{
 	T3_MBUF_HDR hdr;
-  union
+	union {
-  {
 		struct {
 			T3_MBUF_FRAME_DESC frame_hdr;
 			LM_UINT32 data[20];
@@ -1105,7 +1062,6 @@ typedef struct T3_MBUF
 #define T3_MBUF_BASE   (T3_NIC_MBUF_POOL_ADDR >> 7)
 #define T3_MBUF_END    ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7)
 
-
 /******************************************************************************/
 /* Statistics block. */
 /******************************************************************************/
@@ -1209,7 +1165,6 @@ typedef struct {
 	LM_UINT8 Reserved4[0xb00 - 0x9c0];
 } T3_STATS_BLOCK, *PT3_STATS_BLOCK;
 
-
 /******************************************************************************/
 /* PCI configuration registers. */
 /******************************************************************************/
@@ -1274,7 +1229,6 @@ typedef struct {
 #define VPD_FLAG_RW_MASK    (1 << 15)
 #define VPD_FLAG_READ       0
 
-
 	T3_32BIT_REGISTER VpdData;
 
 	T3_8BIT_REGISTER MsiCapabilityId;
@@ -1285,7 +1239,6 @@ typedef struct {
 #define MSI_CTRL_MSG_CAP(x)    (x << 1)
 #define MSI_CTRL_ENABLE        (1 << 0)
 
-
 	T3_32BIT_REGISTER MsiAddrLow;
 	T3_32BIT_REGISTER MsiAddrHigh;
 
@@ -1316,7 +1269,6 @@ typedef struct {
 #define DMA_CTRL_WRITE_BOUNDARY_1024            (BIT_13 | BIT_12 | BIT_11)
 #define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE          BIT_14
 
-
 	T3_32BIT_REGISTER PciState;
 #define T3_PCI_STATE_FORCE_PCI_RESET                    BIT_0
 #define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE               BIT_1
@@ -1610,7 +1562,6 @@ typedef struct {
 	LM_UINT8 Reserved5[784];
 } T3_MAC_CONTROL, *PT3_MAC_CONTROL;
 
-
 /******************************************************************************/
 /* Send data initiator control registers. */
 /******************************************************************************/
@@ -1651,7 +1602,6 @@ typedef struct {
 	LM_UINT8 Unused[800];
 } T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR;
 
-
 /******************************************************************************/
 /* Send data completion control registers. */
 /******************************************************************************/
@@ -1665,7 +1615,6 @@ typedef struct {
 	LM_UINT8 Unused[1020];
 } T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION;
 
-
 /******************************************************************************/
 /* Send BD Ring Selector Control Registers. */
 /******************************************************************************/
@@ -1691,7 +1640,6 @@ typedef struct {
 	LM_UINT8 Unused2[896];
 } T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR;
 
-
 /******************************************************************************/
 /* Send BD initiator control registers. */
 /******************************************************************************/
@@ -1712,7 +1660,6 @@ typedef struct {
 	LM_UINT8 Unused2[952];
 } T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR;
 
-
 /******************************************************************************/
 /* Send BD Completion Control. */
 /******************************************************************************/
@@ -1727,7 +1674,6 @@ typedef struct {
 	LM_UINT8 Unused2[1020];
 } T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION;
 
-
 /******************************************************************************/
 /* Receive list placement control registers. */
 /******************************************************************************/
@@ -1797,7 +1743,6 @@ typedef struct {
 	LM_UINT8 Unused2[420];
 } T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT;
 
-
 /******************************************************************************/
 /* Receive Data and Receive BD Initiator Control. */
 /******************************************************************************/
@@ -1847,7 +1792,6 @@ typedef struct {
 	LM_UINT8 Unused3[828];
 } T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR;
 
-
 /******************************************************************************/
 /* Receive Data Completion Control Registes. */
 /******************************************************************************/
@@ -1862,7 +1806,6 @@ typedef struct {
 	LM_UINT8 Unused[1020];
 } T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION;
 
-
 /******************************************************************************/
 /* Receive BD Initiator Control. */
 /******************************************************************************/
@@ -1888,7 +1831,6 @@ typedef struct {
 	LM_UINT8 Unused[992];
 } T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR;
 
-
 /******************************************************************************/
 /* Receive BD Completion Control Registers. */
 /******************************************************************************/
@@ -1910,7 +1852,6 @@ typedef struct {
 	LM_UINT8 Unused[1004];
 } T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION;
 
-
 /******************************************************************************/
 /* Receive list selector control register. */
 /******************************************************************************/
@@ -1928,7 +1869,6 @@ typedef struct {
 	LM_UINT8 Unused[1016];
 } T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR;
 
-
 /******************************************************************************/
 /* Mbuf cluster free registers. */
 /******************************************************************************/
@@ -1944,7 +1884,6 @@ typedef struct {
 	LM_UINT8 Unused[1016];
 } T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE;
 
-
 /******************************************************************************/
 /* Host coalescing control registers. */
 /******************************************************************************/
@@ -2030,7 +1969,6 @@ typedef struct {
 	LM_UINT8 Unused5[768];
 } T3_HOST_COALESCING, *PT3_HOST_COALESCING;
 
-
 /******************************************************************************/
 /* Memory arbiter registers. */
 /******************************************************************************/
@@ -2049,7 +1987,6 @@ typedef struct {
 	LM_UINT8 Unused[1008];
 } T3_MEM_ARBITER, *PT3_MEM_ARBITER;
 
-
 /******************************************************************************/
 /* Buffer manager control register. */
 /******************************************************************************/
@@ -2094,7 +2031,6 @@ typedef struct {
 	LM_UINT8 Unused[936];
 } T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER;
 
-
 /******************************************************************************/
 /* Read DMA control registers. */
 /******************************************************************************/
@@ -2128,10 +2064,8 @@ typedef struct {
 	LM_UINT8 Unused[1016];
 } T3_DMA_READ, *PT3_DMA_READ;
 
-typedef union T3_CPU
+typedef union T3_CPU {
-{
+	struct {
-  struct
-  {
 		T3_32BIT_REGISTER mode;
 #define CPU_MODE_HALT   BIT_10
 #define CPU_MODE_RESET  BIT_0
@@ -2186,7 +2120,6 @@ typedef struct {
 	LM_UINT8 Unused[1016];
 } T3_DMA_WRITE, *PT3_DMA_WRITE;
 
-
 /******************************************************************************/
 /* Mailbox registers. */
 /******************************************************************************/
@@ -2229,7 +2162,6 @@ typedef struct {
 	LM_UINT8 Unused[496];
 } T3_GRC_MAILBOX, *PT3_GRC_MAILBOX;
 
-
 /******************************************************************************/
 /* Flow through queues. */
 /******************************************************************************/
@@ -2328,7 +2260,6 @@ typedef struct {
 	LM_UINT8 Unused2[736];
 } T3_FTQ, *PT3_FTQ;
 
-
 /******************************************************************************/
 /* Message signaled interrupt registers. */
 /******************************************************************************/
@@ -2345,7 +2276,6 @@ typedef struct {
 	LM_UINT8 Unused[1012];
 } T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT;
 
-
 /******************************************************************************/
 /* DMA Completion registes. */
 /******************************************************************************/
@@ -2359,7 +2289,6 @@ typedef struct {
 	LM_UINT8 Unused[1020];
 } T3_DMA_COMPLETION, *PT3_DMA_COMPLETION;
 
-
 /******************************************************************************/
 /* GRC registers. */
 /******************************************************************************/
@@ -2432,7 +2361,6 @@ typedef struct {
 #define GRC_MISC_MEMSIZE_16M      (6 << 18)
 #define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM            BIT_24
 
-
 	T3_32BIT_REGISTER Timer;
 
 	T3_32BIT_REGISTER RxCpuEvent;
@@ -2473,13 +2401,11 @@ typedef struct {
 	LM_UINT8 Unused[948];
 } T3_GRC, *PT3_GRC;
 
-
 /******************************************************************************/
 /* NVRAM control registers. */
 /******************************************************************************/
 
-typedef struct
+typedef struct {
-{
 	T3_32BIT_REGISTER Cmd;
 #define NVRAM_CMD_RESET                             BIT_0
 #define NVRAM_CMD_DONE                              BIT_3
@@ -2536,7 +2462,6 @@ typedef struct
 	LM_UINT8 Unused[988];
 } T3_NVRAM, *PT3_NVRAM;
 
-
 /******************************************************************************/
 /* NIC's internal memory. */
 /******************************************************************************/
@@ -2570,7 +2495,6 @@ typedef struct {
 	LM_UINT8 BufferDesc[16384];	/* 0x4000 */
 } T3_FIRST_32K_SRAM, *PT3_FIRST_32K_SRAM;
 
-
 /******************************************************************************/
 /* Memory layout. */
 /******************************************************************************/
@@ -2681,20 +2605,17 @@ typedef struct {
 	} uIntMem;
 } T3_STD_MEM_MAP, *PT3_STD_MEM_MAP;
 
-
 /******************************************************************************/
 /* Adapter info. */
 /******************************************************************************/
 
-typedef struct
+typedef struct {
-{
 	LM_UINT16 Svid;
 	LM_UINT16 Ssid;
 	LM_UINT32 PhyId;
 	LM_UINT32 Serdes;	/* 0 = copper PHY, 1 = Serdes */
 } LM_ADAPTER_INFO, *PLM_ADAPTER_INFO;
 
-
 /******************************************************************************/
 /* Packet queues. */
 /******************************************************************************/
@@ -2702,7 +2623,6 @@ typedef struct
 DECLARE_QUEUE_TYPE (LM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT);
 DECLARE_QUEUE_TYPE (LM_TX_PACKET_Q, MAX_TX_PACKET_DESC_COUNT);
 
-
 /******************************************************************************/
 /* Tx counters. */
 /******************************************************************************/
@@ -2717,7 +2637,6 @@ typedef struct {
 	LM_COUNTER NoTxPacketDescCnt;
 } LM_TX_COUNTERS, *PLM_TX_COUNTERS;
 
-
 /******************************************************************************/
 /* Rx counters. */
 /******************************************************************************/
@@ -2737,7 +2656,6 @@ typedef struct {
 	LM_COUNTER RxErrLargePacketCnt;
 } LM_RX_COUNTERS, *PLM_RX_COUNTERS;
 
-
 /******************************************************************************/
 /* Receive producer rings. */
 /******************************************************************************/
@@ -2749,7 +2667,6 @@ typedef enum {
 	T3_JUMBO_RCV_PROD_RING = 3
 } T3_RCV_PROD_RING, *PT3_RCV_PROD_RING;
 
-
 /******************************************************************************/
 /* Packet descriptor. */
 /******************************************************************************/
@@ -2792,7 +2709,6 @@ typedef struct _LM_PACKET {
 	} u;
 } LM_PACKET;
 
-
 /******************************************************************************/
 /* Tigon3 device block. */
 /******************************************************************************/
@@ -2997,7 +2913,6 @@ typedef struct _LM_DEVICE_BLOCK {
 #define T3_LINK_CHNG_MODE_USE_STATUS_REG            1
 #define T3_LINK_CHNG_MODE_USE_STATUS_BLOCK          2
 
-
 	/* LED mode. */
 	LM_UINT32 LedMode;
 
@@ -3082,7 +2997,6 @@ typedef struct _LM_DEVICE_BLOCK {
 	LM_UINT32 PhyCrcCount;
 } LM_DEVICE_BLOCK;
 
-
 #define T3_REG_CPU_VIEW               0xc0000000
 
 #define T3_BLOCK_DMA_RD               (1 << 0)
@@ -3216,7 +3130,6 @@ typedef struct _LM_DEVICE_BLOCK {
 #define TX_CPU_EVT_SW12             30
 #define TX_CPU_EVT_SW13             31
 
-
 /* TX-CPU event */
 #define TX_CPU_EVENT_SW_EVENT0      (1 << TX_CPU_EVT_SW0)
 #define TX_CPU_EVENT_SW_EVENT1      (1 << TX_CPU_EVT_SW1)
@@ -3251,12 +3164,10 @@ typedef struct _LM_DEVICE_BLOCK {
 #define TX_CPU_EVENT_SW_EVENT12     (1 << TX_CPU_EVT_SW12)
 #define TX_CPU_EVENT_SW_EVENT13     (1 << TX_CPU_EVT_SW13)
 
-
 #define TX_CPU_MASK (TX_CPU_EVENT_SW_EVENT0 | \
 		     TX_CPU_EVENT_SDI  | \
 		     TX_CPU_EVENT_SDC)
 
-
 #define T3_FTQ_TYPE1_UNDERFLOW_BIT   (1 << 29)
 #define T3_FTQ_TYPE1_PASS_BIT        (1 << 30)
 #define T3_FTQ_TYPE1_SKIP_BIT        (1 << 31)
@@ -3285,8 +3196,7 @@ typedef struct _LM_DEVICE_BLOCK {
 
 LM_STATUS LM_LoadFirmware (PLM_DEVICE_BLOCK pDevice,
 			   PT3_FWIMG_INFO pFwImg,
-			  LM_UINT32 LoadCpu,
+			   LM_UINT32 LoadCpu, LM_UINT32 StartCpu);
-			  LM_UINT32 StartCpu);
 
 /******************************************************************************/
 /* NIC register read/write macros. */
@@ -3355,7 +3265,6 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
 #define REG_WR_OFFSET(pDevice, Offset, Value32)                             \
     writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset))
 
-
 /* There could be problem access the memory window directly.  For now, */
 /* we have to go through the PCI configuration register. */
 #define MEM_RD(pDevice, AddrName)                                           \