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ColdFire: Multiple fixes for MCF5445x platforms

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Add FEC pin set and mii reset in __mii_init(). Change
legacy flash vendor from 2 to AMD LEGACY (0xFFF0),
change cfi_offset to 0, and change CFG_FLASH_CFI to
CONFIG_FLASH_CFI_LEGACY. Correct M54451EVB and
M54455EVB env settings in configuration file.

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
This commit is contained in:
TsiChung Liew 2008-08-19 00:26:25 +06:00 committed by John Rigby
parent 454e725b3a
commit f78ced3028
5 changed files with 12 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
board/freescale/m54451evb/m54451evb.c
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@ -49,7 +49,7 @@ phys_size_t initdram(int board_type)
* Serial Boot: The dram is already initialized in start.S * Serial Boot: The dram is already initialized in start.S
* only require to return DRAM size * only require to return DRAM size
*/ */
dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1; dramsize = CFG_SDRAM_SIZE * 0x100000;
#else #else
volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
@ -67,7 +67,7 @@ phys_size_t initdram(int board_type)
} }
i--; i--;
gpio->mscr_sdram = 0x44; gpio->mscr_sdram = CFG_SDRAM_DRV_STRENGTH;
sdram->sdcs0 = (CFG_SDRAM_BASE | i); sdram->sdcs0 = (CFG_SDRAM_BASE | i);

7
board/freescale/m54455evb/m54455evb.c
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@ -171,7 +171,7 @@ void pci_init_board(void)
} }
#endif /* CONFIG_PCI */ #endif /* CONFIG_PCI */
#if defined(CFG_FLASH_CFI) #if defined(CONFIG_FLASH_CFI_LEGACY)
#include <flash.h> #include <flash.h>
ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
{ {
@ -189,7 +189,7 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
info->erase_blk_tout = 16384; info->erase_blk_tout = 16384;
info->write_tout = 2; info->write_tout = 2;
info->buffer_write_tout = 5; info->buffer_write_tout = 5;
info->vendor = 2; /* CFI_CMDSET_AMD_STANDARD */ info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
info->cmd_reset = 0x00F0; info->cmd_reset = 0x00F0;
info->interface = FLASH_CFI_X8; info->interface = FLASH_CFI_X8;
info->legacy_unlock = 0; info->legacy_unlock = 0;
@ -199,12 +199,11 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
info->ext_addr = 0; info->ext_addr = 0;
info->cfi_version = 0x3133; info->cfi_version = 0x3133;
info->cfi_offset = 0x0055; info->cfi_offset = 0x0000;
info->addr_unlock1 = 0x00000555; info->addr_unlock1 = 0x00000555;
info->addr_unlock2 = 0x000002AA; info->addr_unlock2 = 0x000002AA;
info->name = "CFI conformant"; info->name = "CFI conformant";
info->size = 0; info->size = 0;
info->sector_count = CFG_ATMEL_TOTALSECT; info->sector_count = CFG_ATMEL_TOTALSECT;
info->start[0] = base; info->start[0] = base;

4
board/freescale/m54455evb/mii.c
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@ -237,6 +237,10 @@ void __mii_init(void)
fecp = (fec_t *) info->miibase; fecp = (fec_t *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */ /* We use strictly polling mode only */
fecp->eimr = 0; fecp->eimr = 0;

3
include/configs/M54451EVB.h
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@ -141,8 +141,7 @@
"load=tftp ${loadaddr) ${u-boot}\0" \ "load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \ "upd=run load; run prog\0" \
"prog=prot off 0 " MK_STR(CFG_UBOOT_END) \ "prog=prot off 0 " MK_STR(CFG_UBOOT_END) \
"; era 0 " MK_STR(CFG_UBOOT_END) \ "; era 0 " MK_STR(CFG_UBOOT_END) " ;" \
"2ffff;" \
"cp.b ${loadaddr} 0 ${filesize};" \ "cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \ "save\0" \
"" ""

3
include/configs/M54455EVB.h
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@ -388,9 +388,6 @@
#endif #endif
#endif #endif
#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#define CFG_FLASH_CHECKSUM
/* /*
* This is setting for JFFS2 support in u-boot. * This is setting for JFFS2 support in u-boot.
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.