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powerpc/p4080: Add workaround for erratum CPU22

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Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2010-05-05 22:35:27 -05:00
parent 61054ffa16
commit fd3c9befa8
4 changed files with 17 additions and 1 deletions
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4
arch/powerpc/cpu/mpc85xx/cmd_errata.c
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@ -44,7 +44,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
puts("Work-around for Erratum SERDES8 enabled\n"); puts("Work-around for Erratum SERDES8 enabled\n");
#endif #endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
puts("Work-around for Erratum CPU22 enabled\n");
#endif
return 0; return 0;
} }

7
arch/powerpc/cpu/mpc85xx/cpu_init.c
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@ -32,6 +32,7 @@
#include <ioports.h> #include <ioports.h>
#include <sata.h> #include <sata.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/cache.h>
#include <asm/mmu.h> #include <asm/mmu.h>
#include <asm/fsl_law.h> #include <asm/fsl_law.h>
#include <asm/fsl_serdes.h> #include <asm/fsl_serdes.h>
@ -245,6 +246,12 @@ int cpu_init_r(void)
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif #endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
flush_dcache();
mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
sync();
#endif
puts ("L2: "); puts ("L2: ");
#if defined(CONFIG_L2_CACHE) #if defined(CONFIG_L2_CACHE)

6
arch/powerpc/cpu/mpc85xx/release.S
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@ -136,6 +136,12 @@ __secondary_start_page:
mtspr L1CSR2,r8 mtspr L1CSR2,r8
#endif #endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
mfspr r8,L1CSR2
oris r8,r8,(L1CSR2_DCWS)@h
mtspr L1CSR2,r8
#endif
#ifdef CONFIG_BACKSIDE_L2_CACHE #ifdef CONFIG_BACKSIDE_L2_CACHE
/* Enable/invalidate the L2 cache */ /* Enable/invalidate the L2 cache */
msync msync

1
arch/powerpc/include/asm/processor.h
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@ -495,6 +495,7 @@
#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
#define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */
#define L1CSR2_DCWS 0x40000000 /* Data Cache Write Shadow */
#define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */ #define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */
#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */