MX5: rename mx51 to mx5

Rename mx51 to mx5 in order to support more mx51
like-style SOCs such as MX53 and the followings.

Signed-off-by: Jason Liu <r64343@freescale.com>

arch/arm/cpu/armv7/mx5/clock.c

@@ -71,7 +71,7 @@ u32 get_mcu_main_clk(void)
 
 	reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
 		MXC_CCM_CACRR_ARM_PODF_OFFSET;
-	freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
+	freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
 	return freq / (reg + 1);
 }
 
@@ -84,14 +84,14 @@ static u32 get_periph_clk(void)
 
 	reg = __raw_readl(&mxc_ccm->cbcdr);
 	if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
-		return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
+		return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
 	reg = __raw_readl(&mxc_ccm->cbcmr);
 	switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
 		MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
 	case 0:
-		return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
+		return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
 	case 1:
-		return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
+		return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
 	default:
 		return 0;
 	}
@@ -146,15 +146,15 @@ static u32 get_uart_clk(void)
 		MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
 	case 0x0:
 		freq = decode_pll(mxc_plls[PLL1_CLOCK],
-				    CONFIG_MX51_HCLK_FREQ);
+				    CONFIG_SYS_MX5_HCLK);
 		break;
 	case 0x1:
 		freq = decode_pll(mxc_plls[PLL2_CLOCK],
-				    CONFIG_MX51_HCLK_FREQ);
+				    CONFIG_SYS_MX5_HCLK);
 		break;
 	case 0x2:
 		freq = decode_pll(mxc_plls[PLL3_CLOCK],
-				    CONFIG_MX51_HCLK_FREQ);
+				    CONFIG_SYS_MX5_HCLK);
 		break;
 	default:
 		return 66500000;
@@ -181,7 +181,7 @@ u32 get_lp_apm(void)
 	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
 
 	if (((ccsr >> 9) & 1) == 0)
-		ret_val = CONFIG_MX51_HCLK_FREQ;
+		ret_val = CONFIG_SYS_MX5_HCLK;
 	else
 		ret_val = ((32768 * 1024));
 
@@ -207,17 +207,17 @@ u32 imx_get_cspiclk(void)
 	switch (clk_sel) {
 	case 0:
 		ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
-					CONFIG_MX51_HCLK_FREQ) /
+					CONFIG_SYS_MX5_HCLK) /
 					((pre_pdf + 1) * (pdf + 1));
 		break;
 	case 1:
 		ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
-					CONFIG_MX51_HCLK_FREQ) /
+					CONFIG_SYS_MX5_HCLK) /
 					((pre_pdf + 1) * (pdf + 1));
 		break;
 	case 2:
 		ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
-					CONFIG_MX51_HCLK_FREQ) /
+					CONFIG_SYS_MX5_HCLK) /
 					((pre_pdf + 1) * (pdf + 1));
 		break;
 	default:
@@ -248,7 +248,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 		return imx_get_cspiclk();
 	case MXC_FEC_CLK:
 		return decode_pll(mxc_plls[PLL1_CLOCK],
-				    CONFIG_MX51_HCLK_FREQ);
+				    CONFIG_SYS_MX5_HCLK);
 	default:
 		break;
 	}
@@ -269,16 +269,16 @@ u32 imx_get_fecclk(void)
 /*
  * Dump some core clockes.
  */
-int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	u32 freq;
 
-	freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
+	freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
-	printf("mx51 pll1: %dMHz\n", freq / 1000000);
+	printf("pll1: %dMHz\n", freq / 1000000);
-	freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
+	freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
-	printf("mx51 pll2: %dMHz\n", freq / 1000000);
+	printf("pll2: %dMHz\n", freq / 1000000);
-	freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
+	freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
-	printf("mx51 pll3: %dMHz\n", freq / 1000000);
+	printf("pll3: %dMHz\n", freq / 1000000);
 	printf("ipg clock     : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
 	printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
 
@@ -288,7 +288,7 @@ int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
 /***************************************************/
 
 U_BOOT_CMD(
-	clockinfo,	CONFIG_SYS_MAXARGS,	1,	do_mx51_showclocks,
+	clockinfo,	CONFIG_SYS_MAXARGS,	1,	do_mx5_showclocks,
-	"display mx51 clocks\n",
+	"display clocks\n",
 	""
 );

arch/arm/cpu/armv7/mx5/iomux.c

@@ -23,7 +23,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/sys_proto.h>
 

arch/arm/cpu/armv7/mx5/soc.c

@@ -33,28 +33,33 @@
 #include <fsl_esdhc.h>
 #endif
 
+#if defined(CONFIG_MX51)
+#define CPU_TYPE 0x51000
+#else
+#error "CPU_TYPE not defined"
+#endif
+
 u32 get_cpu_rev(void)
 {
-	int reg;
+	int system_rev = CPU_TYPE;
-	int system_rev;
+	int reg = __raw_readl(ROM_SI_REV);
 
-	reg = __raw_readl(ROM_SI_REV);
 	switch (reg) {
 	case 0x02:
-		system_rev = 0x51000 | CHIP_REV_1_1;
+		system_rev |= CHIP_REV_1_1;
 		break;
 	case 0x10:
 		if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
-			system_rev = 0x51000 | CHIP_REV_2_5;
+			system_rev |= CHIP_REV_2_5;
 		else
-			system_rev = 0x51000 | CHIP_REV_2_0;
+			system_rev |= CHIP_REV_2_0;
 		break;
 	case 0x20:
-		system_rev = 0x51000 | CHIP_REV_3_0;
+		system_rev |= CHIP_REV_3_0;
 		break;
 	return system_rev;
 	default:
-		system_rev = 0x51000 | CHIP_REV_1_0;
+		system_rev |= CHIP_REV_1_0;
 		break;
 	}
 	return system_rev;
@@ -67,9 +72,10 @@ int print_cpuinfo(void)
 	u32 cpurev;
 
 	cpurev = get_cpu_rev();
-	printf("CPU:   Freescale i.MX51 family rev%d.%d at %d MHz\n",
+	printf("CPU:   Freescale i.MX%x family rev%d.%d at %d MHz\n",
-		(cpurev & 0xF0) >> 4,
+		(cpurev & 0xFF000) >> 12,
-		(cpurev & 0x0F) >> 4,
+		(cpurev & 0x000F0) >> 4,
+		(cpurev & 0x0000F) >> 0,
 		mxc_get_clock(MXC_ARM_CLK) / 1000000);
 	return 0;
 }

arch/arm/cpu/armv7/mx5/timer.c

@@ -75,18 +75,18 @@ void reset_timer(void)
 void reset_timer_masked(void)
 {
 	ulong val = __raw_readl(&cur_gpt->counter);
-	lastinc = val / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
+	lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
 	timestamp = 0;
 }
 
 ulong get_timer_masked(void)
 {
 	ulong val = __raw_readl(&cur_gpt->counter);
-	val /= (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ);
+	val /= (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
 	if (val >= lastinc)
 		timestamp += (val - lastinc);
 	else
-		timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ))
+		timestamp += ((0xFFFFFFFF / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ))
 				- lastinc) + val;
 	lastinc = val;
 	return timestamp;
@@ -106,7 +106,7 @@ void set_timer(ulong t)
 void __udelay(unsigned long usec)
 {
 	unsigned long now, start, tmo;
-	tmo = usec * (CONFIG_MX51_CLK32 / 1000) / 1000;
+	tmo = usec * (CONFIG_SYS_MX5_CLK32 / 1000) / 1000;
 
 	if (!tmo)
 		tmo = 1;

arch/arm/include/asm/arch-mx5/iomux.h

@@ -20,13 +20,13 @@
  * MA 02111-1307 USA
  */
 
-#ifndef __MACH_MX51_IOMUX_H__
+#ifndef __MACH_MX5_IOMUX_H__
-#define __MACH_MX51_IOMUX_H__
+#define __MACH_MX5_IOMUX_H__
 
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
 
 typedef unsigned int iomux_pin_name_t;
 
@@ -190,4 +190,4 @@ void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
 unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
 void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
 
-#endif				/*  __MACH_MX51_IOMUX_H__ */
+#endif				/*  __MACH_MX5_IOMUX_H__ */

arch/arm/include/asm/arch-mx5/mx5x_pins.h

@@ -20,8 +20,8 @@
  * MA 02111-1307 USA
  */
 
-#ifndef __ASM_ARCH_MXC_MX51_PINS_H__
+#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__
-#define __ASM_ARCH_MXC_MX51_PINS_H__
+#define __ASM_ARCH_MX5_MX5X_PINS_H__
 
 #ifndef __ASSEMBLY__
 
@@ -415,4 +415,4 @@ enum iomux_pins {
 };
 
 #endif				/* __ASSEMBLY__ */
-#endif				/* __ASM_ARCH_MXC_MX51_PINS_H__ */
+#endif				/* __ASM_ARCH_MX5_MX5X_PINS_H__ */

board/freescale/mx51evk/mx51evk.c

@@ -23,7 +23,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
 #include <asm/arch/sys_proto.h>

board/ttcontrol/vision2/vision2.c

@@ -26,7 +26,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/iomux.h>
 #include <mxc_gpio.h>

boards.cfg

@@ -46,8 +46,8 @@ pm9263		arm	arm926ejs	-		ronetix		at91
 jadecpu		arm	arm926ejs	jadecpu		syteco		mb86r0x
 suen3		arm	arm926ejs	km_arm		keymile		kirkwood
 rd6281a		arm	arm926ejs	-		Marvell		kirkwood
-mx51evk		arm	armv7		mx51evk		freescale	mx51
+mx51evk		arm	armv7		mx51evk		freescale	mx5
-vision2		arm	armv7		vision2		ttcontrol	mx51
+vision2		arm	armv7		vision2		ttcontrol	mx5
 actux1		arm	ixp
 actux2		arm	ixp
 actux3		arm	ixp

include/configs/mx51evk.h

@@ -30,8 +30,8 @@
 #define CONFIG_MX51	/* in a mx51 */
 #define CONFIG_SKIP_RELOCATE_UBOOT
 
-#define CONFIG_MX51_HCLK_FREQ		24000000	/* RedBoot says 26MHz */
+#define CONFIG_SYS_MX5_HCLK	24000000
-#define CONFIG_MX51_CLK32		32768
+#define CONFIG_SYS_MX5_CLK32		32768
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 

include/configs/vision2.h

@@ -29,8 +29,8 @@
 #define CONFIG_MX51	/* in a mx51 */
 #define CONFIG_L2_OFF
 
-#define CONFIG_MX51_HCLK_FREQ		24000000
+#define CONFIG_SYS_MX5_HCLK	24000000
-#define CONFIG_MX51_CLK32		32768
+#define CONFIG_SYS_MX5_CLK32		32768
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO