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5 Commits

Author SHA1 Message Date
Wolfgang Denk
cd040a4953 arch/arm/cpu/arm_cortexa8/omap3/cache.S: make build with older tools 
The push / pop instructions used in this file are available only with
more recent tool chains:

cache.S: Assembler messages:
cache.S:133: Error: bad instruction `push {r0,r1,r2,lr}'
cache.S:160: Error: bad instruction `pop {r1,r2,r3,pc}'
cache.S:164: Error: bad instruction `push {r0,r1,r2,lr}'
cache.S:191: Error: bad instruction `pop {r1,r2,r3,pc}'

Change push/pop into stmfd/ldmfd instructions to support older
versions of binutils as well.

I verified that the modified source code generates exactly the same
binary code.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rix <tom@bumblecow.com>
 2010-06-18 16:01:07 +02:00
Vaibhav Hiremath
1a5038ca68 AM35x: Add support for EMIF4 
This patch adds support for the EMIF4 interface
available in the AM35x processors.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
 2010-06-08 10:07:19 -05:00
Vaibhav Hiremath
cae377b59a omap3: Consolidate SDRC related operations 
Consolidated SDRC related functions into one file - sdrc.c

And also replaced sdrc_init with generic memory init
function (mem_init), this generalization of omap memory setup
is necessary to support the new emif4 interface introduced in AM3517.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
 2010-06-08 10:07:18 -05:00
Vaibhav Hiremath
d11212e377 omap3: Calculate CS1 size only when SDRC is 
initialized for CS1

From: Vaibhav Hiremath <hvaibhav@ti.com>

The patch makes sure that size for SDRC CS1 gets calculated
only when the CS1 SDRC is initialized.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
 2010-06-08 10:07:18 -05:00
Peter Tyser
84ad688473 arm: Move cpu/$CPU to arch/arm/cpu/$CPU 
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
 2010-04-13 09:13:24 +02:00