Dave Liu 0a71c92c7e fsl-ddr: Fix power-down timing settings ...

1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but
   It should be set to tXP parameter, tXP=max(3CK, 7.5ns)
2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but
   It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter
   We are setting the mode register MR0[A12]='1'

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

2010-01-05 13:49:10 -06:00

..

ddr

fsl-ddr: Fix power-down timing settings

2010-01-05 13:49:10 -06:00

cpu.c

ppc/p4080: Add various p4080 related defines (and p4040)

2009-09-24 12:05:28 -05:00

fdt.c

ppc/85xx/86xx: Device tree fixup for number of cores

2009-09-08 09:10:08 -05:00

Makefile

ppc/85xx/86xx: Device tree fixup for number of cores

2009-09-08 09:10:08 -05:00

pci_cfg.c

ppc/8xxx: Remove is_fsl_pci_agent

2010-01-05 13:49:07 -06:00