Ilya Yanok
2aa8720257
davinci_emac: fix for running with dcache enabled ...
DaVinci EMAC is present on TI AM35xx SoCs (ARMv7) which run with D-Cache
enabled by default. So we have to take care and flush/invalidate the
cache before/after the DMA operations.
Please note that the receive buffer alignment to 32 byte boundary comes
from the old driver version I don't know if it is really needed or
alignment to cache line size is enough.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
2011-12-06 23:59:35 +01:00
2011-11-29 08:48:06 -06:00
2011-12-05 23:07:59 +01:00
2011-11-16 21:14:14 +01:00
2011-10-26 21:29:08 +02:00
2011-12-06 23:59:30 +01:00
2011-09-30 22:00:53 +02:00
2011-11-16 21:28:59 +01:00
2011-11-23 08:14:27 +01:00
2011-12-06 23:59:35 +01:00
2011-12-06 23:59:35 +01:00
2011-10-22 00:37:49 +02:00
2011-08-08 21:05:23 +02:00
2011-10-17 22:25:33 +02:00
2011-11-23 08:33:57 +01:00
2011-10-28 00:37:01 +02:00
2011-11-17 10:00:27 +01:00
2011-11-17 10:00:10 +01:00
2011-11-03 20:39:35 +01:00
2011-11-16 21:29:23 +01:00
2011-11-11 11:36:56 +01:00
2011-09-30 22:01:03 +02:00
2011-10-22 01:16:08 +02:00
2011-07-28 21:27:36 +02:00
2011-10-27 23:54:07 +02:00
2011-11-23 08:14:27 +01:00
2011-12-06 23:59:32 +01:00
2011-06-21 22:26:22 +02:00
2011-11-22 08:39:25 +01:00
2011-10-05 22:22:16 +02:00
2011-10-05 22:22:16 +02:00
2011-12-05 23:04:17 +01:00
2011-07-28 21:27:36 +02:00
2011-10-22 01:16:08 +02:00
2011-10-22 01:16:08 +02:00
2011-07-16 11:55:00 +02:00
2011-10-09 23:24:48 +02:00
2011-11-03 20:38:49 +01:00
2011-11-07 22:18:06 +01:00
2011-11-07 22:47:37 +01:00
2011-11-07 22:18:17 +01:00
2011-12-02 13:46:20 +09:00
2011-12-02 13:46:20 +09:00
2011-10-22 01:16:08 +02:00
2011-11-22 08:39:27 +01:00
2011-10-09 23:24:49 +02:00
2011-12-06 23:59:32 +01:00
2011-11-08 08:30:32 -06:00
2011-10-15 22:12:05 +02:00
2011-10-23 23:32:44 +02:00
2aa8720257