Grzegorz Bernacki 334e442e6f Set ips dividor to 1/4 of csb clock.
Previous setting cause ips clock to be out of spec. This bug was found by John
Rigby from Freescale.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2008-01-17 09:31:58 +01:00
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