Jon Loeliger cfc7a7f5bb cpu/86xx fixes. ...

Remove rev 1 fixes.
Always set PICGCR_MODE.
Enable machine check and provide board config option
to set and handle SoC error interrupts.

Include MSSSR0 in error message.

Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>

2007-08-10 11:02:32 -05:00

..

cache.S

Remove L2 Cache invalidate polling.

2006-05-19 13:54:02 -05:00

config.mk

Review cleanups.

2006-05-31 14:01:32 -05:00

cpu_init.c

cpu/86xx fixes.

2007-08-10 11:02:32 -05:00

cpu.c

Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx

2007-05-17 00:07:21 +02:00

interrupts.c

cpu/86xx fixes.

2007-08-10 11:02:32 -05:00

Makefile

Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts.

2007-08-06 00:22:24 +02:00

spd_sdram.c

Rewrote picos_to_clk() to avoid rounding errors.

2007-05-01 11:36:59 -05:00

speed.c

General indent and whitespace cleanups.

2006-08-22 12:06:18 -05:00

start.S

cpu/86xx fixes.

2007-08-10 11:02:32 -05:00

traps.c

cpu/86xx fixes.

2007-08-10 11:02:32 -05:00