Mike Frysinger
48ab150925
Blackfin: add workaround for anomaly 05000242
...
DESCRIPTION:
If the DF bit is set prior to a hardware reset, the PLL will continue to
divide CLKIN by 2 after the hardware reset, but the DF bit itself will be
cleared in the PLL_CTL register.
WORKAROUND:
Reprogram the PLL with DF cleared if the desire is to not divide CLKIN by
2 after reset.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-04-06 17:37:48 -04:00
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