mirror of
https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git
synced 2025-08-28 00:04:20 -04:00
8e585f02f8
Added board/freescale/m5329evb, cpu/mcf532x, drivers/net, drivers/serial, immap_5329.h, m5329.h, mcfrtc.h, include/configs/M5329EVB.h, lib_m68k/interrupts.c, and rtc/mcfrtc.c Modified CREDITS, MAKEFILE, Makefile, README, common/cmd_bdinfo.c, common/cmd_mii.c, include/asm-m68k/byteorder.h, include/asm-m68k/fec.h, include/asm-m68k/io.h, include/asm-m68k/mcftimer.h, include/asm-m68k/mcfuart.h, include/asm-m68k/ptrace.h, include/asm-m68k/u-boot.h, lib_m68k/Makefile, lib_m68k/board.c, lib_m68k/time.c, net/eth.c and rtc/Makefile Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
362 lines
12 KiB
C
362 lines
12 KiB
C
/*
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* mcfuart.h -- ColdFire internal UART support defines.
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*
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* File copied from mcfuart.h of uCLinux distribution:
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* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
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* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/****************************************************************************/
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#ifndef mcfuart_h
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#define mcfuart_h
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/****************************************************************************/
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#include <linux/config.h>
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/*
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* Define the base address of the UARTS within the MBAR address
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* space.
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*/
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#if defined(CONFIG_M5272)
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#define MCFUART_BASE1 0x100 /* Base address of UART1 */
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#define MCFUART_BASE2 0x140 /* Base address of UART2 */
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#elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
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#if defined(CONFIG_NETtel)
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#define MCFUART_BASE1 0x180 /* Base address of UART1 */
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#define MCFUART_BASE2 0x140 /* Base address of UART2 */
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#else
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#define MCFUART_BASE1 0x140 /* Base address of UART1 */
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#define MCFUART_BASE2 0x180 /* Base address of UART2 */
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#endif
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#elif defined(CONFIG_M5282) || defined(CONFIG_M5271)
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#define MCFUART_BASE1 0x200 /* Base address of UART1 */
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#define MCFUART_BASE2 0x240 /* Base address of UART2 */
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#define MCFUART_BASE3 0x280 /* Base address of UART3 */
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#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
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#if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
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#define MCFUART_BASE1 0x200 /* Base address of UART1 */
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#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
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#else
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#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
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#define MCFUART_BASE2 0x200 /* Base address of UART2 */
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#endif
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#endif
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/*
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* Define the ColdFire UART register set addresses.
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*/
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#define MCFUART_UMR 0x00 /* Mode register (r/w) */
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#define MCFUART_USR 0x04 /* Status register (r) */
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#define MCFUART_UCSR 0x04 /* Clock Select (w) */
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#define MCFUART_UCR 0x08 /* Command register (w) */
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#define MCFUART_URB 0x0c /* Receiver Buffer (r) */
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#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
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#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
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#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
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#define MCFUART_UISR 0x14 /* Interrup Status (r) */
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#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
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#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
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#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
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#ifdef CONFIG_M5272
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#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
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#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
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#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
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#else
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#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
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#endif
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#define MCFUART_UIPR 0x34 /* Input Port (r) */
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#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
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#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
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#ifdef CONFIG_M5249
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/* Note: This isn't in the 5249 docs */
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#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
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#endif
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/*
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* Define bit flags in Mode Register 1 (MR1).
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*/
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#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
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#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
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#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
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#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
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#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
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#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */
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#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */
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#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */
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#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */
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#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */
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#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */
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#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */
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#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */
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#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */
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/*
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* Define bit flags in Mode Register 2 (MR2).
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*/
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#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */
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#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */
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#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */
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#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */
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#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
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#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
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#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */
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#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */
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/*
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* Define bit flags in Status Register (USR).
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*/
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#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */
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#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */
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#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */
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#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */
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#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */
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#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */
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#define MCFUART_USR_RXFULL 0x02 /* Receiver full */
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#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */
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#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
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MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
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/*
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* Define bit flags in Clock Select Register (UCSR).
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*/
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#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
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#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */
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#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */
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#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */
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#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */
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#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */
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/*
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* Define bit flags in Command Register (UCR).
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*/
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#define MCFUART_UCR_CMDNULL 0x00 /* No command */
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#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */
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#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */
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#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */
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#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */
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#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
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#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */
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#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */
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#define MCFUART_UCR_TXNULL 0x00 /* No TX command */
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#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */
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#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */
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#define MCFUART_UCR_RXNULL 0x00 /* No RX command */
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#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */
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#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */
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/*
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* Define bit flags in Input Port Change Register (UIPCR).
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*/
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#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */
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#define MCFUART_UIPCR_CTS 0x01 /* CTS value */
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/*
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* Define bit flags in Input Port Register (UIP).
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*/
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#define MCFUART_UIPR_CTS 0x01 /* CTS value */
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/*
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* Define bit flags in Output Port Registers (UOP).
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* Clear bit by writing to UOP0, set by writing to UOP1.
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*/
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#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */
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/*
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* Define bit flags in the Auxiliary Control Register (UACR).
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*/
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#define MCFUART_UACR_IEC 0x01 /* Input enable control */
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/*
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* Define bit flags in Interrupt Status Register (UISR).
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* These same bits are used for the Interrupt Mask Register (UIMR).
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*/
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#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */
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#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */
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#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */
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#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */
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#ifdef CONFIG_M5272
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/*
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* Define bit flags in the Transmitter FIFO Register (UTF).
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*/
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#define MCFUART_UTF_TXB 0x1f /* transmitter data level */
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#define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */
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#define MCFUART_UTF_TXS 0xc0 /* transmitter status */
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/*
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* Define bit flags in the Receiver FIFO Register (URF).
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*/
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#define MCFUART_URF_RXB 0x1f /* receiver data level */
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#define MCFUART_URF_FULL 0x20 /* receiver fifo full */
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#define MCFUART_URF_RXS 0xc0 /* receiver status */
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#endif
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#ifdef CONFIG_MCFUART
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/* UART module registers */
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/* Register read/write struct */
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typedef struct uart {
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u8 umr; /* 0x00 Mode Register */
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u8 resv0[0x3];
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union {
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u8 usr; /* 0x04 Status Register */
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u8 ucsr; /* 0x04 Clock Select Register */
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};
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u8 resv1[0x3];
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u8 ucr; /* 0x08 Command Register */
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u8 resv2[0x3];
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union {
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u8 utb; /* 0x0c Transmit Buffer */
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u8 urb; /* 0x0c Receive Buffer */
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};
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u8 resv3[0x3];
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union {
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u8 uipcr; /* 0x10 Input Port Change Register */
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u8 uacr; /* 0x10 Auxiliary Control reg */
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};
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u8 resv4[0x3];
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union {
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u8 uimr; /* 0x14 Interrupt Mask reg */
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u8 uisr; /* 0x14 Interrupt Status reg */
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};
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u8 resv5[0x3];
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u8 ubg1; /* 0x18 Counter Timer Upper Register */
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u8 resv6[0x3];
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u8 ubg2; /* 0x1c Counter Timer Lower Register */
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u8 resv7[0x17];
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u8 uip; /* 0x34 Input Port Register */
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u8 resv8[0x3];
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u8 uop1; /* 0x38 Output Port Set Register */
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u8 resv9[0x3];
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u8 uop0; /* 0x3c Output Port Reset Register */
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} uart_t;
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/*********************************************************************
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* Universal Asynchronous Receiver Transmitter (UART)
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*********************************************************************/
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/* Bit definitions and macros for UMR */
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#define UART_UMR_BC(x) (((x)&0x03))
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#define UART_UMR_PT (0x04)
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#define UART_UMR_PM(x) (((x)&0x03)<<3)
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#define UART_UMR_ERR (0x20)
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#define UART_UMR_RXIRQ (0x40)
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#define UART_UMR_RXRTS (0x80)
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#define UART_UMR_SB(x) (((x)&0x0F))
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#define UART_UMR_TXCTS (0x10) /* Trsnsmit CTS */
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#define UART_UMR_TXRTS (0x20) /* Transmit RTS */
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#define UART_UMR_CM(x) (((x)&0x03)<<6) /* CM bits */
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#define UART_UMR_PM_MULTI_ADDR (0x1C)
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#define UART_UMR_PM_MULTI_DATA (0x18)
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#define UART_UMR_PM_NONE (0x10)
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#define UART_UMR_PM_FORCE_HI (0x0C)
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#define UART_UMR_PM_FORCE_LO (0x08)
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#define UART_UMR_PM_ODD (0x04)
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#define UART_UMR_PM_EVEN (0x00)
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#define UART_UMR_BC_5 (0x00)
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#define UART_UMR_BC_6 (0x01)
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#define UART_UMR_BC_7 (0x02)
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#define UART_UMR_BC_8 (0x03)
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#define UART_UMR_CM_NORMAL (0x00)
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#define UART_UMR_CM_ECH (0x40)
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#define UART_UMR_CM_LOCAL_LOOP (0x80)
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#define UART_UMR_CM_REMOTE_LOOP (0xC0)
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#define UART_UMR_SB_STOP_BITS_1 (0x07)
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#define UART_UMR_SB_STOP_BITS_15 (0x08)
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#define UART_UMR_SB_STOP_BITS_2 (0x0F)
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/* Bit definitions and macros for USR */
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#define UART_USR_RXRDY (0x01)
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#define UART_USR_FFULL (0x02)
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#define UART_USR_TXRDY (0x04)
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#define UART_USR_TXEMP (0x08)
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#define UART_USR_OE (0x10)
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#define UART_USR_PE (0x20)
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#define UART_USR_FE (0x40)
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#define UART_USR_RB (0x80)
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/* Bit definitions and macros for UCSR */
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#define UART_UCSR_TCS(x) (((x)&0x0F))
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#define UART_UCSR_RCS(x) (((x)&0x0F)<<4)
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#define UART_UCSR_RCS_SYS_CLK (0xD0)
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#define UART_UCSR_RCS_CTM16 (0xE0)
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#define UART_UCSR_RCS_CTM (0xF0)
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#define UART_UCSR_TCS_SYS_CLK (0x0D)
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#define UART_UCSR_TCS_CTM16 (0x0E)
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#define UART_UCSR_TCS_CTM (0x0F)
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/* Bit definitions and macros for UCR */
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#define UART_UCR_RXC(x) (((x)&0x03))
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#define UART_UCR_TXC(x) (((x)&0x03)<<2)
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#define UART_UCR_MISC(x) (((x)&0x07)<<4)
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#define UART_UCR_NONE (0x00)
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#define UART_UCR_STOP_BREAK (0x70)
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#define UART_UCR_START_BREAK (0x60)
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#define UART_UCR_BKCHGINT (0x50)
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#define UART_UCR_RESET_ERROR (0x40)
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#define UART_UCR_RESET_TX (0x30)
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#define UART_UCR_RESET_RX (0x20)
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#define UART_UCR_RESET_MR (0x10)
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#define UART_UCR_TX_DISABLED (0x08)
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#define UART_UCR_TX_ENABLED (0x04)
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#define UART_UCR_RX_DISABLED (0x02)
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#define UART_UCR_RX_ENABLED (0x01)
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/* Bit definitions and macros for UIPCR */
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#define UART_UIPCR_CTS (0x01)
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#define UART_UIPCR_COS (0x10)
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/* Bit definitions and macros for UACR */
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#define UART_UACR_IEC (0x01)
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/* Bit definitions and macros for UIMR */
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#define UART_UIMR_TXRDY (0x01)
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#define UART_UIMR_RXRDY_FU (0x02)
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#define UART_UIMR_DB (0x04)
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#define UART_UIMR_COS (0x80)
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/* Bit definitions and macros for UISR */
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#define UART_UISR_TXRDY (0x01)
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#define UART_UISR_RXRDY_FU (0x02)
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#define UART_UISR_DB (0x04)
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#define UART_UISR_RXFTO (0x08)
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#define UART_UISR_TXFIFO (0x10)
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#define UART_UISR_RXFIFO (0x20)
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#define UART_UISR_COS (0x80)
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/* Bit definitions and macros for UIP */
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#define UART_UIP_CTS (0x01)
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/* Bit definitions and macros for UOP1 */
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#define UART_UOP1_RTS (0x01)
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/* Bit definitions and macros for UOP0 */
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#define UART_UOP0_RTS (0x01)
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#endif /* CONFIG_MCFUART */
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/****************************************************************************/
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#endif /* mcfuart_h */
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