roy zang 4dbcd69e3e Introduce PLL_CFG[0:4] table for processor 7448/7447A/7455/7457. The original
multiplier table can not refect the real PLL clock behavior of these
processors. Please refer to the hardware specification for detailed
information of the corresponding processors.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2006-12-04 17:54:21 +08:00
..
2006-11-30 18:02:20 +01:00
2006-10-24 15:32:57 +02:00