Troy Kisky 1482410531 MX53: DDR: Fix ZQHWCTRL field TZQ_CS
Currently, board files are setting this field to 0x01
which the manual says is a reserved value. Change to
use the default of 0x02 - 128 cycles.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-04-16 14:53:58 +02:00
..
2011-10-15 22:20:36 +02:00