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Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR + IVOR15) to have valid and fetchable OP code. 1) While executing in translated space (AS=1), whenever a debug exception is generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to fetch an instruction from the debug exception vector (IVPR + IVOR15); since now we are in AS=0, the application needs to ensure the proper TLB configuration to have (IVOR + IVOR15) accessible from AS=0 also. Create a temporary TLB in AS0 to make sure debug exception verctor is accessible on debug exception. 2) Just after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>