u-boot

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History

Laurence Withers 88ac6b9d14 DaVinci DA850: UART2 clock ID comes from ASYNC3

On the DA830, UART2's clock is derived from PLL controller 0 output 2.
On the DA850, it is in the ASYNC3 group, and may be switched between PLL
controller 0 or 1. Fix the definition of the ID to match.

Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>

2012-09-01 14:58:14 +02:00

arm

DaVinci DA850: UART2 clock ID comes from ASYNC3

2012-09-01 14:58:14 +02:00

avr32

global_data: unify global flag defines

2012-08-09 21:46:32 +02:00

blackfin

Consolidate bootcount code into drivers/bootcount

2012-09-01 14:26:02 +02:00

m68k

global_data: unify global flag defines