mirror of
https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git
synced 2025-09-08 11:36:21 -04:00
8ca78f2c89
Previously boards used a variety of indentations, newline styles, and
colon styles for the PCI information that is printed on bootup. This
patch unifies the style to look like:
...
NAND: 1024 MiB
PCIE1: connected as Root Complex
Scanning PCI bus 01
04 01 8086 1010 0200 00
04 01 8086 1010 0200 00
03 00 10b5 8112 0604 00
02 01 10b5 8518 0604 00
02 02 10b5 8518 0604 00
08 00 1957 0040 0b20 00
07 00 10b5 8518 0604 00
09 00 10b5 8112 0604 00
07 01 10b5 8518 0604 00
07 02 10b5 8518 0604 00
06 00 10b5 8518 0604 00
02 03 10b5 8518 0604 00
01 00 10b5 8518 0604 00
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
Scanning PCI bus 0d
0d 00 1957 0040 0b20 00
PCIE2: Bus 0c - 0d
In: serial
...
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
CC: wd@denx.de
CC: sr@denx.de
CC: galak@kernel.crashing.org
406 lines
10 KiB
C
406 lines
10 KiB
C
/*
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* Copyright 2008-2010 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <asm/fsl_serdes.h>
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#include <spd.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <spd_sdram.h>
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#include <fdt_support.h>
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#include <tsec.h>
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#include <netdev.h>
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#include <sata.h>
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#include "../common/sgmii_riser.h"
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phys_size_t fixed_sdram(void);
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int board_early_init_f (void)
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{
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#ifdef CONFIG_MMC
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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setbits_be32(&gur->pmuxcr,
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(MPC85xx_PMUXCR_SD_DATA |
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MPC85xx_PMUXCR_SDHC_CD |
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MPC85xx_PMUXCR_SDHC_WP));
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#endif
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return 0;
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}
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int checkboard (void)
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{
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u8 vboot;
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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puts("Board: MPC8536DS ");
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#ifdef CONFIG_PHYS_64BIT
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puts("(36-bit addrmap) ");
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#endif
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printf ("Sys ID: 0x%02x, "
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"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
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in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
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in_8(pixis_base + PIXIS_PVER));
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vboot = in_8(pixis_base + PIXIS_VBOOT);
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switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
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case PIXIS_VBOOT_LBMAP_NOR0:
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puts ("vBank: 0\n");
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break;
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case PIXIS_VBOOT_LBMAP_NOR1:
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puts ("vBank: 1\n");
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break;
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case PIXIS_VBOOT_LBMAP_NOR2:
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puts ("vBank: 2\n");
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break;
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case PIXIS_VBOOT_LBMAP_NOR3:
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puts ("vBank: 3\n");
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break;
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case PIXIS_VBOOT_LBMAP_PJET:
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puts ("Promjet\n");
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break;
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case PIXIS_VBOOT_LBMAP_NAND:
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puts ("NAND\n");
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break;
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}
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return 0;
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}
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phys_size_t
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initdram(int board_type)
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{
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phys_size_t dram_size = 0;
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puts("Initializing....");
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#ifdef CONFIG_SPD_EEPROM
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dram_size = fsl_ddr_sdram();
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#else
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dram_size = fixed_sdram();
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#endif
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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puts(" DDR: ");
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return dram_size;
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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phys_size_t fixed_sdram (void)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile ccsr_ddr_t *ddr= &immap->im_ddr;
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uint d_init;
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
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ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
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ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
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ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
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ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
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ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
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ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
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#if defined (CONFIG_DDR_ECC)
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ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
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ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
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ddr->err_sbe = CONFIG_SYS_DDR_SBE;
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#endif
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asm("sync;isync");
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udelay(500);
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ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
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#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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d_init = 1;
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debug("DDR - 1st controller: memory initializing\n");
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/*
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* Poll until memory is initialized.
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* 512 Meg at 400 might hit this 200 times or so.
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*/
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while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
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udelay(1000);
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}
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debug("DDR: memory initialized\n\n");
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asm("sync; isync");
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udelay(500);
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#endif
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return 512 * 1024 * 1024;
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}
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#endif
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#ifdef CONFIG_PCI1
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static struct pci_controller pci1_hose;
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#endif
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif
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#ifdef CONFIG_PCIE2
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static struct pci_controller pcie2_hose;
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#endif
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#ifdef CONFIG_PCIE3
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static struct pci_controller pcie3_hose;
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#endif
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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struct fsl_pci_info pci_info[4];
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u32 devdisr, pordevsr, io_sel, sdrs2_io_sel;
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u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
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int first_free_busno = 0;
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int num = 0;
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int pcie_ep, pcie_configured;
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devdisr = in_be32(&gur->devdisr);
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pordevsr = in_be32(&gur->pordevsr);
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porpllsr = in_be32(&gur->porpllsr);
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io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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sdrs2_io_sel = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
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debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x\n",
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devdisr, sdrs2_io_sel, io_sel);
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if (sdrs2_io_sel == 7)
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printf(" Serdes2 disalbed\n");
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else if (sdrs2_io_sel == 4) {
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printf(" eTSEC1 is in sgmii mode.\n");
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printf(" eTSEC3 is in sgmii mode.\n");
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} else if (sdrs2_io_sel == 6)
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printf(" eTSEC1 is in sgmii mode.\n");
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puts("\n");
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#ifdef CONFIG_PCIE3
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pcie_configured = is_serdes_configured(PCIE3);
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
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set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
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LAW_TRGT_IF_PCIE_3);
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set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
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LAW_TRGT_IF_PCIE_3);
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SET_STD_PCIE_INFO(pci_info[num], 3);
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pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
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printf("PCIE3: connected to Slot3 as %s (base address %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie3_hose, first_free_busno);
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} else {
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printf("PCIE3: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
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#endif
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#ifdef CONFIG_PCIE1
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pcie_configured = is_serdes_configured(PCIE1);
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M,
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LAW_TRGT_IF_PCIE_1);
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set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
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LAW_TRGT_IF_PCIE_1);
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SET_STD_PCIE_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
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printf("PCIE1: connected to Slot1 as %s (base address %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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} else {
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printf("PCIE1: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
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#endif
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#ifdef CONFIG_PCIE2
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pcie_configured = is_serdes_configured(PCIE2);
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
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set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M,
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LAW_TRGT_IF_PCIE_2);
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set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
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LAW_TRGT_IF_PCIE_2);
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SET_STD_PCIE_INFO(pci_info[num], 2);
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pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
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printf("PCIE2: connected to Slot 2 as %s (base address %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie2_hose, first_free_busno);
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} else {
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printf("PCIE2: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
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#endif
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#ifdef CONFIG_PCI1
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pci_speed = 66666000;
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pci_32 = 1;
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pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
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pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M,
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LAW_TRGT_IF_PCI);
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set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K,
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LAW_TRGT_IF_PCI);
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SET_STD_PCI_INFO(pci_info[num], 1);
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pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
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printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33333000) ? "33" :
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(pci_speed == 66666000) ? "66" : "unknown",
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pci_clk_sel ? "sync" : "async",
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pci_agent ? "agent" : "host",
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pci_arb ? "arbiter" : "external-arbiter",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pci1_hose, first_free_busno);
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} else {
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printf("PCI: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
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#endif
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}
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#endif
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
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0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_TSEC_ENET
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struct tsec_info_struct tsec_info[2];
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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int num = 0;
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uint sdrs2_io_sel =
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(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) {
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tsec_info[num].phyaddr = 0;
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tsec_info[num].flags |= TSEC_SGMII;
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}
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num++;
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#endif
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#ifdef CONFIG_TSEC3
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SET_STD_TSEC_INFO(tsec_info[num], 3);
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if (sdrs2_io_sel == 4) {
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tsec_info[num].phyaddr = 1;
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tsec_info[num].flags |= TSEC_SGMII;
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}
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num++;
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#endif
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if (!num) {
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printf("No TSECs initialized\n");
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return 0;
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}
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#ifdef CONFIG_FSL_SGMII_RISER
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if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6))
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fsl_sgmii_riser_init(tsec_info, num);
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#endif
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tsec_eth_init(bis, tsec_info, num);
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#endif
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return pci_eth_init(bis);
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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FT_FSL_PCI_SETUP;
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#ifdef CONFIG_FSL_SGMII_RISER
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fsl_sgmii_riser_fdt_fixup(blob);
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#endif
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}
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#endif
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