Peter Tyser a2cd50ed6e 85xx: Add CPU 2 errata workaround to all 8548 boards ...

All mpc8548-based boards should implement the suggested workaround
to CPU 2 errata. Without the workaround, its possible for the
8548's core to hang while executing a msync or mbar 0 instruction
and a snoopable transaction from an I/O master tagged to make
quick forward progress is present.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>

2008-12-03 22:46:42 -06:00

..

config.mk

…

ddr.c

Pass dimm parameters to populate populate controller options

2008-10-18 21:54:04 +02:00

law.c

rename CFG_ macros to CONFIG_SYS

2008-10-18 21:54:03 +02:00

Makefile

FSL DDR: Convert MPC8548CDS to new DDR code.

2008-08-27 11:43:50 -05:00

mpc8548cds.c

85xx: Add CPU 2 errata workaround to all 8548 boards

2008-12-03 22:46:42 -06:00

tlb.c

rename CFG_ macros to CONFIG_SYS

2008-10-18 21:54:03 +02:00

u-boot.lds

mpc85xx: workaround old binutils bug

2008-08-10 22:41:12 +02:00