Priyanka Jain 32c8cfb23c fsl_esdhc: Deal with watermark level register related changes
P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark
level register description has been changed:

9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00
25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-10 11:17:55 -05:00
..
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-10-04 11:15:02 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2011-02-02 22:36:10 +01:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-10-18 22:33:32 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-07-16 10:55:09 -05:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-10-04 11:15:02 +02:00
2010-10-04 11:15:02 +02:00
2010-10-04 11:15:02 +02:00
2010-10-04 11:15:02 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00
2010-04-21 23:42:38 +02:00