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9dd611b8c1
Add Xilinx Spartan2E family FPGA support * Patch by Jeff Angielski, 02 Sep 2004: Add Added support for H2 revision of the EP8260 board. Fixed formatting for some of the EP8260 related source files.
114 lines
3.7 KiB
C
114 lines
3.7 KiB
C
/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef _SPARTAN2_H_
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#define _SPARTAN2_H_
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#include <xilinx.h>
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extern int Spartan2_load( Xilinx_desc *desc, void *image, size_t size );
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extern int Spartan2_dump( Xilinx_desc *desc, void *buf, size_t bsize );
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extern int Spartan2_info( Xilinx_desc *desc );
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extern int Spartan2_reloc( Xilinx_desc *desc, ulong reloc_off );
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/* Slave Parallel Implementation function table */
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typedef struct {
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Xilinx_pre_fn pre;
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Xilinx_pgm_fn pgm;
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Xilinx_init_fn init;
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Xilinx_err_fn err;
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Xilinx_done_fn done;
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Xilinx_clk_fn clk;
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Xilinx_cs_fn cs;
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Xilinx_wr_fn wr;
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Xilinx_rdata_fn rdata;
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Xilinx_wdata_fn wdata;
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Xilinx_busy_fn busy;
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Xilinx_abort_fn abort;
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Xilinx_post_fn post;
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int relocated;
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} Xilinx_Spartan2_Slave_Parallel_fns;
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/* Slave Serial Implementation function table */
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typedef struct {
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Xilinx_pre_fn pre;
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Xilinx_pgm_fn pgm;
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Xilinx_clk_fn clk;
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Xilinx_init_fn init;
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Xilinx_done_fn done;
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Xilinx_wr_fn wr;
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int relocated;
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} Xilinx_Spartan2_Slave_Serial_fns;
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/* Device Image Sizes
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*********************************************************************/
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/* Spartan-II (2.5V) */
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#define XILINX_XC2S15_SIZE 197728/8
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#define XILINX_XC2S30_SIZE 336800/8
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#define XILINX_XC2S50_SIZE 559232/8
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#define XILINX_XC2S100_SIZE 781248/8
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#define XILINX_XC2S150_SIZE 1040128/8
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/* Spartan-IIE (1.8V) */
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#define XILINX_XC2S50E_SIZE 630048/8
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#define XILINX_XC2S100E_SIZE 863840/8
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#define XILINX_XC2S150E_SIZE 1134496/8
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#define XILINX_XC2S200E_SIZE 1442016/8
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#define XILINX_XC2S300E_SIZE 1875648/8
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/* Descriptor Macros
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*********************************************************************/
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/* Spartan-II devices */
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#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie }
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#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie }
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#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie }
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#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie }
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#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie }
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#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie }
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#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie }
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#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie }
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#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie }
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#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
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{ Xilinx_Spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie }
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#endif /* _SPARTAN2_H_ */
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