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https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git
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cfd39cdf94
To prepare for the 85xx USB support, which requires interface enablement only once in (specified) order, no different than instructions for enabling the interface under 83xx. It is unknown why the original author enabled the interface twice (checked for references in errata, etc). Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
97 lines
2.7 KiB
C
97 lines
2.7 KiB
C
/*
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* (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
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*
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* Author: Tor Krill tor@excito.com
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <usb.h>
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#include <mpc83xx.h>
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#include <asm/io.h>
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#include <asm/bitops.h>
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#include "ehci.h"
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#include "ehci-fsl.h"
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#include "ehci-core.h"
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/*
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* Create the appropriate control structures to manage
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* a new EHCI host controller.
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*
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* Excerpts from linux ehci fsl driver.
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*/
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int ehci_hcd_init(void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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uint32_t addr, temp;
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addr = (uint32_t)&(im->usb[0]);
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hccr = (struct ehci_hccr *)(addr + FSL_SKIP_PCI);
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hcor = (struct ehci_hcor *)((uint32_t) hccr +
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HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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/* Configure clock */
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clrsetbits_be32(&(im->clk.sccr), MPC83XX_SCCR_USB_MASK,
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MPC83XX_SCCR_USB_DRCM_11);
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/* Confgure interface. */
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temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL));
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out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp
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| REFSEL_16MHZ | UTMI_PHY_EN);
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/* Wait for clock to stabilize */
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do {
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temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL));
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udelay(1000);
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} while (!(temp & PHY_CLK_VALID));
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/* Set to Host mode */
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temp = in_le32((void *)(addr + FSL_SOC_USB_USBMODE));
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out_le32((void *)(addr + FSL_SOC_USB_USBMODE), temp | CM_HOST);
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out_be32((void *)(addr + FSL_SOC_USB_SNOOP1), SNOOP_SIZE_2GB);
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out_be32((void *)(addr + FSL_SOC_USB_SNOOP2),
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0x80000000 | SNOOP_SIZE_2GB);
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/* Init phy */
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/* TODO: handle different phys? */
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out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI);
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/* Enable interface. */
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temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL));
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out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp | USB_EN);
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out_be32((void *)(addr + FSL_SOC_USB_PRICTRL), 0x0000000c);
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out_be32((void *)(addr + FSL_SOC_USB_AGECNTTHRSH), 0x00000040);
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out_be32((void *)(addr + FSL_SOC_USB_SICTRL), 0x00000001);
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temp = in_le32((void *)(addr + FSL_SOC_USB_USBMODE));
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return 0;
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}
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/*
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* Destroy the appropriate control structures corresponding
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* the the EHCI host controller.
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*/
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int ehci_hcd_stop(void)
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{
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return 0;
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}
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