Stefan Roese e1d1429b49 ppc4xx: Fix GPIO configuration for pcs440ep
The SRD0_PFC0 register was not configured correctly to enable the GPIO's
49-63 for GPIO. They have been configured as trace signals. This patch
fixes this by clearing the corresponding bit.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-02-04 11:47:40 +01:00
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