Shiraz Hashim f28e5c946d SPEAr: Correct SoC ID offset in misc configuration space ...

SoC Core ID offset is 0x30 in miscellaneous configuration address
space. It was wrongly mentioned as periph2 clk enable.

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

2012-07-07 14:07:42 +02:00

..

arm

SPEAr: Correct SoC ID offset in misc configuration space

2012-07-07 14:07:42 +02:00

avr32

avr32:board.c: fix compile warning

2012-06-04 09:21:34 +02:00

blackfin

CONFIG_SYS_BAUDRATE_TABLE: Add <config_fallbacks.h>, place there

2012-06-20 20:26:16 +02:00

m68k

net: move bootfile init into eth_initialize

2012-05-15 17:32:33 -05:00

microblaze

net: move bootfile init into eth_initialize

2012-05-15 17:32:33 -05:00

mips

MIPS: board.c: move extern declarations to u-boot-mips.h

2012-06-03 23:46:04 +02:00

nds32

net: move bootfile init into eth_initialize

2012-05-15 17:32:33 -05:00

nios2

net: punt bd->bi_ip_addr

2012-05-15 17:32:05 -05:00

openrisc

net: punt bd->bi_ip_addr

2012-05-15 17:32:05 -05:00

powerpc

MPC8xxx: Define cache ops for USB

2012-06-07 23:29:19 +02:00

sandbox

net: punt bd->bi_ip_addr

2012-05-15 17:32:05 -05:00

sh

sh: Add SH7269 device and RSK2+SH7269 board

2012-05-28 09:12:54 +09:00

sparc

net: move bootfile init into eth_initialize

2012-05-15 17:32:33 -05:00

x86

net: move bootfile init into eth_initialize

2012-05-15 17:32:33 -05:00

.gitignore

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