York Sun f5b6fb7c1b powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers ...

The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

2011-03-05 10:13:50 -06:00

..

common_timing_params.h

powerpc/8xxx: Enable DDR3 RDIMM support

2010-07-26 13:16:10 -05:00

ctrl_regs.c

powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers

2011-03-05 10:13:50 -06:00

ddr1_dimm_params.c

Move arch/ppc to arch/powerpc

2010-04-21 23:42:38 +02:00

ddr2_dimm_params.c

Enabled support for Rev 1.3 SPD for DDR2 DIMMs

2010-05-12 04:54:30 -05:00

ddr3_dimm_params.c

powerpc/8xxx: Enable DDR3 RDIMM support

2010-07-26 13:16:10 -05:00

ddr.h

powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3

2011-02-10 23:40:02 -06:00

lc_common_dimm_params.c

mpc8xxx: Display RDIMM if detected

2011-01-19 22:58:23 -06:00

main.c

8xxx/ddr: add support to only compute the ddr sdram size

2011-01-19 22:58:22 -06:00

Makefile

Switch from archive libraries to partial linking

2010-11-17 21:02:18 +01:00

options.c

mpc85xx: Enable unique mode registers and dynamic ODT for DDR3

2011-01-19 22:58:23 -06:00

util.c

Move arch/ppc to arch/powerpc

2010-04-21 23:42:38 +02:00