403 lines
14 KiB
C
403 lines
14 KiB
C
//========= Copyright Valve Corporation, All rights reserved. ============//
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//
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// Purpose:
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//
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// $NoKeywords: $
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//
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//=============================================================================//
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#pragma once
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typedef union EVENT_MASK(TC_deliver_mode) {
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struct {
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uint16 DD : 1; // both logical processors in deliver mode },
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uint16
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DB : 1; // logical processor 0 in deliver mode, 1 in build mode },
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uint16 DI : 1; // logical processor 0 in deliver mode, 1 is inactive },
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uint16
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BD : 1; // logical processor 0 in build mode, 1 in deliver mode },
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uint16 BB : 1; // both logical processors in build mode },
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uint16 BI : 1; // logical processor 0 in build mode, 1 is inactive },
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uint16 ID : 1; // logical processor 0 is inactive, 1 in deliver mode },
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uint16 IB : 1; // logical processor 0 is inactive, 1 in build mode }
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};
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uint16 flat;
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} EVENT_MASK(TC_deliver_mode);
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typedef union EVENT_MASK(BPU_fetch_request) {
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struct {
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uint16 TCMISS : 1; // Trace cache lookup miss },
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};
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uint16 flat;
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} EVENT_MASK(BPU_fetch_request);
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typedef union EVENT_MASK(ITLB_reference) {
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struct {
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uint16 HIT : 1; // ITLB hit },
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uint16 MISS : 1; // ITLB miss },
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uint16 HIT_UC : 1; // Uncacheable ITLB hit }
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};
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uint16 flat;
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} EVENT_MASK(ITLB_reference);
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typedef union EVENT_MASK(memory_cancel) {
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struct {
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uint16 dummy : 2;
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uint16 ST_RB_FULL : 1; // Replayed because no store request buffer is
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// available },
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uint16 _64K_CONF : 1; // Conflicts due to 64K aliasing }
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};
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uint16 flat;
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} EVENT_MASK(memory_cancel);
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typedef union EVENT_MASK(memory_complete) {
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struct {
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uint16 LSC : 1; // Load split completed, excluding UC/WC loads },
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uint16 SSC : 1; // Any split stores completed } }
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};
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uint16 flat;
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} EVENT_MASK(memory_complete);
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typedef union EVENT_MASK(load_port_replay) {
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struct {
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uint16 dummy : 1;
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uint16 SPLIT_LD : 1; // Split load } }
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};
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uint16 flat;
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} EVENT_MASK(load_port_replay);
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typedef union EVENT_MASK(store_port_replay) {
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struct {
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uint16 dummy0 : 1;
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uint16 SPLIT_ST : 1; // Split store } }
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};
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uint16 flat;
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} EVENT_MASK(store_port_replay);
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typedef union EVENT_MASK(MOB_load_replay) {
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struct {
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uint16 dummy0 : 1;
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uint16 NO_STA : 1; // Replayed because of unknown store address },
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uint16 dummy2 : 1;
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uint16 NO_STD : 1; // Replayed because of unknown store data },
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uint16
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PARTIAL_DATA : 1; // Replayed because of partially overlapped data
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// access between the load and store operations },
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uint16 UNALGN_ADDR : 1; // Replayed because the lower 4 bits of the
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// linear address do not match between the load
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// and store operations } }
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};
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uint16 flat;
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} EVENT_MASK(MOB_load_replay);
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typedef union EVENT_MASK(page_walk_type) {
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struct {
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uint16 DTMISS : 1; // Page walk for a data TLB miss },
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uint16 ITMISS : 1; // Page walk for an instruction TLB miss } }
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};
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uint16 flat;
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} EVENT_MASK(page_walk_type);
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typedef union EVENT_MASK(BSQ_cache_reference) {
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struct {
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uint16 RD_2ndL_HITS : 1; // Read 2nd level cache hit Shared },
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uint16 RD_2ndL_HITE : 1; // Read 2nd level cache hit Exclusive },
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uint16 RD_2ndL_HITM : 1; // Read 2nd level cache hit Modified },
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uint16 RD_3rdL_HITS : 1; // Read 3rd level cache hit Shared },
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uint16 RD_3rdL_HITE : 1; // Read 3rd level cache hit Exclusive },
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uint16 RD_3rdL_HITM : 1; // Read 3rd level cache hit Modified },
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uint16 dummy6 : 1;
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uint16 dummy7 : 1;
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uint16 RD_2ndL_MISS : 1; // Read 2nd level cache miss },
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uint16 RD_3rdL_MISS : 1; // Read 3rd level cache miss },
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uint16 WR_2ndL_MISS : 1; // Writeback lookup from DAC misses the 2nd
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// level cache } }
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};
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uint16 flat;
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} EVENT_MASK(BSQ_cache_reference);
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typedef union EVENT_MASK(IOQ) {
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struct {
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uint16 bit0 : 1; // bus request type (use 00001 for invalid or default)
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uint16 bit1 : 1; //
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uint16 bit2 : 1; //
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uint16 bit3 : 1; //
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uint16 bit4 : 1; //
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uint16 ALL_READ : 1; // Count read entries },
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uint16 ALL_WRITE : 1; // Count write entries },
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uint16 MEM_UC : 1; // Count UC memory access entries },
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uint16 MEM_WC : 1; // Count WC memory access entries },
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uint16 MEM_WT : 1; // Count WT memory access entries },
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uint16 MEM_WP : 1; // Count WP memory access entries },
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uint16 MEM_WB : 1; // Count WB memory access entries },
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uint16 dummy12 : 1;
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uint16 OWN : 1; // Count own store requests },
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uint16 OTHER : 1; // Count other and DMA store requests },
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uint16 PREFETCH : 1; // Include HW and SW prefetch requests } }
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};
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uint16 flat;
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} EVENT_MASK(IOQ);
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typedef union EVENT_MASK(FSB_data_activity) {
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struct {
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/* DRDY_OWN is mutually exclusive with DRDY_OTHER */
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/* DBSY_OWN is mutually exclusive with DBSY_OTHER */
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uint16 DRDY_DRV : 1; // Count when this processor drives data onto the
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// bus },
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uint16 DRDY_OWN : 1; // Count when this processor reads data from the
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// bus },
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uint16 DRDY_OTHER : 1; // Count when data is on the bus but not being
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// sampled by the processor },
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uint16 DBSY_DRV : 1; // Count when this processor reserves the bus for
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// driving data },
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uint16 DBSY_OWN : 1; // Count when this processor reserves the bus for
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// sampling data },
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uint16 DBSY_OTHER : 1; // Count when the bus is reserved for driving
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// data this processor will not sample } }
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};
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uint16 flat;
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} EVENT_MASK(FSB_data_activity);
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typedef union EVENT_MASK(BSQ) {
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struct {
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uint16 REQ_TYPE0 : 1; // Request type encoding bit 0 },
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uint16 REQ_TYPE1 : 1; // Request type encoding bit 1 },
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uint16 REQ_LEN0 : 1; // Request length encoding bit 0 },
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uint16 REQ_LEN1 : 1; // Request length encoding bit 1 },
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uint16 dummy4 : 1;
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uint16 REQ_IO_TYPE : 1; // Request type is input or output },
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uint16 REQ_LOCK_TYPE : 1; // Request type is bus lock },
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uint16 REQ_CACHE_TYPE : 1; // Request type is cacheable },
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uint16 REQ_SPLIT_TYPE : 1; // Request type is a bus 8-byte chunk split
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// across 8-byte boundary },
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uint16 REQ_DEM_TYPE : 1; // Request type is a demand (1) or prefetch
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// (0) },
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uint16 REQ_ORD_TYPE : 1; // Request is an ordered type },
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uint16 MEM_TYPE0 : 1; // Memory type encoding bit 0 },
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uint16 MEM_TYPE1 : 1; // Memory type encoding bit 1 },
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uint16 MEM_TYPE2 : 1; // Memory type encoding bit 2 } }
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};
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uint16 flat;
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} EVENT_MASK(BSQ);
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typedef union EVENT_MASK(firm_uop) {
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struct {
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uint16 dummy15 : 15;
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uint16 ALL : 1; // count all uops of this type } }
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};
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uint16 flat;
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} EVENT_MASK(firm_uop);
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typedef union EVENT_MASK(TC_misc) {
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struct {
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uint16 dymmy4 : 4;
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uint16 FLUSH : 1; // Number of flushes } }
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};
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uint16 flat;
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} EVENT_MASK(TC_misc);
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typedef union EVENT_MASK(global_power_events) {
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struct {
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uint16 Running : 1; // The processor is active } }
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};
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uint16 flat;
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} EVENT_MASK(global_power_events);
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typedef union EVENT_MASK(tc_ms_xfer) {
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struct {
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uint16 CISC : 1; // A TC to MS transfer ocurred } }
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};
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uint16 flat;
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} EVENT_MASK(tc_ms_xfer);
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typedef union EVENT_MASK(uop_queue_writes) {
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struct {
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uint16 FROM_TC_BUILD : 1; // uops written from TC build mode
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uint16 FROM_TC_DELIVER : 1; // uops written from TC deliver mode
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uint16 FROM_ROM : 1; // uops written from microcode ROM } }
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};
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uint16 flat;
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} EVENT_MASK(uop_queue_writes);
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typedef union EVENT_MASK(branch_type) {
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struct {
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uint16 dummy : 1;
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uint16 CONDITIONAL : 1; // Conditional jumps
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uint16 CALL : 1; // Direct or indirect call
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uint16 RETURN : 1; // Return branches
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uint16 INDIRECT : 1; // Returns, indirect calls, or indirect jumps
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};
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uint16 flat;
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} EVENT_MASK(branch_type);
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typedef union EVENT_MASK(resource_stall) {
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struct {
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uint16 dummy1 : 5;
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uint16 SBFULL : 1; // A Stall due to lack of store buffers } }
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};
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uint16 flat;
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} EVENT_MASK(resource_stall);
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typedef union EVENT_MASK(WC_Buffer) {
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struct {
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uint16 WCB_EVICTS : 1; // all causes },
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uint16 WCB_FULL_EVICT : 1; // no WC buffer is available },
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/* XXX: 245472-011 no longer lists bit 2, but that looks like
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a table formatting error. Keeping it for now. */
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uint16 WCB_HITM_EVICT : 1; // store encountered a Hit Modified
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// condition } }
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};
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uint16 flat;
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} EVENT_MASK(WC_Buffer);
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typedef union EVENT_MASK(b2b_cycles) {
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struct {
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uint16 dummy0 : 1;
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uint16 bit1 : 1; //
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uint16 bit2 : 1; //
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uint16 bit3 : 1; //
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uint16 bit4 : 1; //
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uint16 bit5 : 1; //
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uint16 bit6 : 1; //
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};
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uint16 flat;
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} EVENT_MASK(b2b_cycles);
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typedef union EVENT_MASK(bnr) {
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struct {
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uint16 bit0 : 1; //
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uint16 bit1 : 1; //
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uint16 bit2 : 1; //
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};
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uint16 flat;
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} EVENT_MASK(bnr);
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typedef union EVENT_MASK(snoop) {
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struct {
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uint16 dummy0 : 1;
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uint16 dummy1 : 1;
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uint16 bit2 : 1; //
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uint16 dummy3 : 1; //
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uint16 dummy4 : 1; //
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uint16 dummy5 : 1; //
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uint16 bit6 : 1; //
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uint16 bit7 : 1; //
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};
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uint16 flat;
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} EVENT_MASK(snoop);
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typedef union EVENT_MASK(response) {
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struct {
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uint16 dummy0 : 1; //
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uint16 bit1 : 1; //
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uint16 bit2 : 1; //
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uint16 dummy3 : 1; //
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uint16 dummy4 : 1; //
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uint16 dummy5 : 1; //
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uint16 dummy6 : 1; //
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uint16 dummy7 : 1; //
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uint16 bit8 : 1; //
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uint16 bit9 : 1; //
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};
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uint16 flat;
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} EVENT_MASK(response);
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typedef union EVENT_MASK(nbogus_bogus) {
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struct {
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uint16 NBOGUS : 1; // The marked uops are not bogus
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uint16 BOGUS : 1; // The marked uops are bogus
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};
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uint16 flat;
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} EVENT_MASK(nbogus_bogus);
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typedef union EVENT_MASK(execution_event) {
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struct {
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uint16 NBOGUS0 : 1; // non-bogus uops with tag bit 0 set },
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uint16 NBOGUS1 : 1; // non-bogus uops with tag bit 1 set },
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uint16 NBOGUS2 : 1; // non-bogus uops with tag bit 2 set },
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uint16 NBOGUS3 : 1; // non-bogus uops with tag bit 3 set },
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uint16 BOGUS0 : 1; // bogus uops with tag bit 0 set },
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uint16 BOGUS1 : 1; // bogus uops with tag bit 1 set },
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uint16 BOGUS2 : 1; // bogus uops with tag bit 2 set },
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uint16 BOGUS3 : 1; // bogus uops with tag bit 3 set } }
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};
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uint16 flat;
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} EVENT_MASK(execution_event);
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typedef union EVENT_MASK(instr_retired) {
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struct {
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uint16 NBOGUSNTAG : 1; // Non-bogus instructions that are not tagged },
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uint16 NBOGUSTAG : 1; // Non-bogus instructions that are tagged },
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uint16 BOGUSNTAG : 1; // Bogus instructions that are not tagged },
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uint16 BOGUSTAG : 1; // Bogus instructions that are tagged } }
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};
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uint16 flat;
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} EVENT_MASK(instr_retired);
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typedef union EVENT_MASK(uop_type) {
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struct {
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uint16 dummy0 : 1;
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uint16 TAGLOADS : 1; // The uop is a load operation },
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uint16 TAGSTORES : 1; // The uop is a store operation } }
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};
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uint16 flat;
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} EVENT_MASK(uop_type);
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typedef union EVENT_MASK(branch_retired) {
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struct {
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uint16 MMNP : 1; // Branch Not-taken Predicted
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uint16 MMNM : 1; // Branch Not-taken Mispredicted
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uint16 MMTP : 1; // Branch Taken Predicted
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uint16 MMTM : 1; // Branch Taken Mispredicted
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};
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uint16 flat;
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} EVENT_MASK(branch_retired);
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typedef union EVENT_MASK(mispred_branch_retired) {
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struct {
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uint16 NBOGUS : 1; // The retired branch is not bogus } }
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};
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uint16 flat;
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} EVENT_MASK(mispred_branch_retired);
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typedef union EVENT_MASK(x87_assist) {
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struct {
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uint16 FPSU : 1; // FP stack underflow },
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uint16 FPSO : 1; // FP stack overflow },
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uint16 POAO : 1; // x87 output overflow },
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uint16 POAU : 1; // x87 output underflow },
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uint16 PREA : 1; // x87 input assist } }
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};
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uint16 flat;
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} EVENT_MASK(x87_assist);
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typedef union EVENT_MASK(machine_clear) {
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struct {
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uint16 CLEAR : 1; // Count a portion of the cycles when the machine is
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// cleared },
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uint16 dummy1 : 1;
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uint16 MOCLEAR : 1; // Count clears due to memory ordering issues },
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uint16 dummy3 : 1;
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uint16 dummy4 : 1;
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uint16 dummy5 : 1;
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uint16
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SMCLEAR : 1; // Count clears due to self-modifying code issues } }
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};
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uint16 flat;
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} EVENT_MASK(machine_clear);
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typedef union EVENT_MASK(x87_SIMD_moves_uop) {
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struct {
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uint16 dummy3 : 3;
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uint16 ALLP0 : 1; // Count all x87/SIMD store/move uops },
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uint16 ALLP2 : 1; // count all x87/SIMD load uops } }
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};
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uint16 flat;
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} EVENT_MASK(x87_SIMD_moves_uop);
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