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vm:enable the instruction and data caches.

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Enable the instruction and data caches. Whether data is cached
will depend on the MMU entries.

Change-Id: I51e9ebc38924db5525d4e7ad9ab69b2a5b1ca7b4
This commit is contained in:
Kees Jongenburger 2013-01-02 17:50:11 +01:00
parent 5e3b51ba96
commit 09895f86fc
1 changed files with 6 additions and 1 deletions
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7
kernel/arch/arm/pg_utils.c
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@ -211,9 +211,14 @@ void vm_enable_paging(void)
/* Set all Domains to Client */ /* Set all Domains to Client */
write_dacr(0x55555555); write_dacr(0x55555555);
/* Enable MMU and access flag */
sctlr = read_sctlr(); sctlr = read_sctlr();
/* Enable MMU */
sctlr |= (SCTLR_M); sctlr |= (SCTLR_M);
/* Enable instruction and data cache */
sctlr |= SCTLR_C;
sctlr |= SCTLR_I;
write_sctlr(sctlr); write_sctlr(sctlr);
} }