i2c: general clean-up
Implement changes based on Kees comments on the code review: http://gerrit-minix.few.vu.nl/#/c/676/ Changes: - use spin API instead of micro_delay() for busy-wait loops. - use read16/write16/set16 from mmio.h to access I2C registers. - reduce the timeout for soft reset. - in read/write, don't mix variable declaration and initialization. - after transfer, wait for access ready instead of blindly delaying. - rename constants am335x, dm37xx to AM335X_I2C_BUS, DM37XX_I2C_BUS. - rename ADDRESS_MASK to MAX_I2C_SA_MASK for clairity. - rename omap_i2c_claim_bus() to omap_i2c_bus_is_free(). Change-Id: Ic221e6134e024ea0a6690f21cff208a728286948
This commit is contained in:
Thomas Cort
parent
99e91dab2f
commit
228e84ad2a
@ -12,6 +12,7 @@
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#include <minix/padconf.h>
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#include <minix/sysutil.h>
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#include <minix/type.h>
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#include <minix/spin.h>
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/* device headers */
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#include <minix/i2c.h>
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@ -29,8 +30,13 @@
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/* local headers */
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#include "omap_i2c.h"
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/* defines the set of register */
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/*
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* defines the set of register
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*
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* Warning: always use the 16-bit variants of read/write/set from mmio.h
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* to access these registers. The DM37XX TRM Section 17.6 warns that 32-bit
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* accesses can corrupt the register contents.
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*/
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typedef struct omap_i2c_registers
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{
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vir_bytes I2C_REVNB_LO; /* AM335X Only */
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@ -75,7 +81,7 @@ typedef struct omap_i2c_registers
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typedef struct omap_i2c_bus
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{
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enum bus_types
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{ am335x, dm37xx } bus_type;
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{ AM335X_I2C_BUS, DM37XX_I2C_BUS} bus_type;
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phys_bytes mr_base;
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phys_bytes mr_size;
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vir_bytes mapped_addr;
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@ -154,15 +160,15 @@ static omap_i2c_regs_t dm37xx_i2c_regs = {
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/* Define the buses available on each chip */
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static omap_i2c_bus_t am335x_i2c_buses[] = {
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{am335x, AM335X_I2C0_BASE, AM335X_I2C0_SIZE, 0, &am335x_i2c_regs,
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{AM335X_I2C_BUS, AM335X_I2C0_BASE, AM335X_I2C0_SIZE, 0, &am335x_i2c_regs,
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AM335X_FUNCTIONAL_CLOCK, AM335X_MODULE_CLOCK,
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BUS_SPEED_400KHz, AM335X_REV_MAJOR, AM335X_REV_MINOR,
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AM335X_I2C0_IRQ, 1, 1},
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{am335x, AM335X_I2C1_BASE, AM335X_I2C1_SIZE, 0, &am335x_i2c_regs,
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{AM335X_I2C_BUS, AM335X_I2C1_BASE, AM335X_I2C1_SIZE, 0, &am335x_i2c_regs,
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AM335X_FUNCTIONAL_CLOCK, AM335X_MODULE_CLOCK,
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BUS_SPEED_100KHz, AM335X_REV_MAJOR, AM335X_REV_MINOR,
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AM335X_I2C1_IRQ, 2, 3},
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{am335x, AM335X_I2C2_BASE, AM335X_I2C2_SIZE, 0, &am335x_i2c_regs,
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{AM335X_I2C_BUS, AM335X_I2C2_BASE, AM335X_I2C2_SIZE, 0, &am335x_i2c_regs,
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AM335X_FUNCTIONAL_CLOCK, AM335X_MODULE_CLOCK,
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BUS_SPEED_100KHz, AM335X_REV_MAJOR, AM335X_REV_MINOR,
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AM335X_I2C2_IRQ, 3, 3}
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@ -171,15 +177,15 @@ static omap_i2c_bus_t am335x_i2c_buses[] = {
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#define AM335X_OMAP_NBUSES (sizeof(am335x_i2c_buses) / sizeof(omap_i2c_bus_t))
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static omap_i2c_bus_t dm37xx_i2c_buses[] = {
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{dm37xx, DM37XX_I2C0_BASE, DM37XX_I2C0_SIZE, 0, &dm37xx_i2c_regs,
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{DM37XX_I2C_BUS, DM37XX_I2C0_BASE, DM37XX_I2C0_SIZE, 0, &dm37xx_i2c_regs,
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DM37XX_FUNCTIONAL_CLOCK, DM37XX_MODULE_CLOCK,
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BUS_SPEED_100KHz, DM37XX_REV_MAJOR, DM37XX_REV_MINOR,
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DM37XX_I2C0_IRQ, 1, 1},
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{dm37xx, DM37XX_I2C1_BASE, DM37XX_I2C1_SIZE, 0, &dm37xx_i2c_regs,
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{DM37XX_I2C_BUS, DM37XX_I2C1_BASE, DM37XX_I2C1_SIZE, 0, &dm37xx_i2c_regs,
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DM37XX_FUNCTIONAL_CLOCK, DM37XX_MODULE_CLOCK,
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BUS_SPEED_100KHz, DM37XX_REV_MAJOR, DM37XX_REV_MINOR,
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DM37XX_I2C1_IRQ, 2, 2},
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{dm37xx, DM37XX_I2C2_BASE, DM37XX_I2C2_SIZE, 0, &dm37xx_i2c_regs,
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{DM37XX_I2C_BUS, DM37XX_I2C2_BASE, DM37XX_I2C2_SIZE, 0, &dm37xx_i2c_regs,
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DM37XX_FUNCTIONAL_CLOCK, DM37XX_MODULE_CLOCK,
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BUS_SPEED_100KHz, DM37XX_REV_MAJOR, DM37XX_REV_MINOR,
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DM37XX_I2C2_IRQ, 3, 3}
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@ -208,8 +214,7 @@ static int omap_i2c_process(minix_i2c_ioctl_exec_t * m);
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/* Bus Specific Code */
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static void omap_i2c_flush(void);
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static uint16_t omap_i2c_poll(uint16_t mask);
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static int omap_i2c_claim_bus(void);
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static int omap_i2c_release_bus(void);
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static int omap_i2c_bus_is_free(void);
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static int omap_i2c_soft_reset(void);
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static void omap_i2c_bus_init(void);
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#if 0
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@ -224,13 +229,6 @@ static int omap_i2c_read(i2c_addr_t addr, uint8_t * buf, size_t buflen,
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static int omap_i2c_write(i2c_addr_t addr, const uint8_t * buf, size_t buflen,
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int dostop);
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/* Helpers for register access */
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#define reg_read(a) (*(volatile uint16_t *)(omap_i2c_bus->mapped_addr + a))
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#define reg_write(a,v) (*(volatile uint16_t *)(omap_i2c_bus->mapped_addr + a) = (v))
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#define reg_set_bit(a,v) reg_write((a), reg_read((a)) | (1<<v))
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#define reg_clear_bit(a,v) reg_write((a), reg_read((a)) & ~(1<<v))
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/*
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* Performs the action in minix_i2c_ioctl_exec_t.
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*/
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@ -251,9 +249,9 @@ omap_i2c_process(minix_i2c_ioctl_exec_t * ioctl_exec)
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omap_i2c_flush(); /* clear any garbage in the fifo */
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/* Check bus busy flag before using the bus */
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r = omap_i2c_claim_bus();
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if (r == -1) {
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log_warn(&log, "Can't Claim Bus\n");
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r = omap_i2c_bus_is_free();
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if (r == 0) {
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log_warn(&log, "Bus is busy\n");
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return EBUSY;
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}
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@ -282,8 +280,6 @@ omap_i2c_process(minix_i2c_ioctl_exec_t * ioctl_exec)
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return r;
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}
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omap_i2c_release_bus();
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return OK;
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}
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@ -304,13 +300,11 @@ omap_i2c_flush(void)
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if ((status & (1 << RRDY)) != 0) { /* bytes available for reading */
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/* consume the byte and throw it away */
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(void) reg_read(omap_i2c_bus->regs->I2C_DATA);
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(void) read16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_DATA);
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/* clear the read ready flag */
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omap_i2c_write_status(1 << RRDY);
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micro_delay(250);
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} else {
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break; /* buffer drained */
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}
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@ -324,55 +318,44 @@ omap_i2c_flush(void)
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static uint16_t
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omap_i2c_poll(uint16_t mask)
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{
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int tries;
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spin_t spin;
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uint16_t status;
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for (tries = 0; tries < 1000; tries++) {
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/* poll for up to 250 ms */
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spin_init(&spin, 250000);
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do {
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status = omap_i2c_read_status();
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if ((status & mask) != 0) { /* any bits in mask set */
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return status;
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}
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micro_delay(250); /* else wait and try again */
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}
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} while (spin_check(&spin));
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return status; /* timeout reached, abort */
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}
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/*
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* Poll Bus Busy Flag until the bus becomes free (return 0) or the timeout
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* expires (return -1).
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* Poll Bus Busy Flag until the bus becomes free (return 1) or the timeout
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* expires (return 0).
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*/
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static int
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omap_i2c_claim_bus(void)
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omap_i2c_bus_is_free(void)
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{
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int tries;
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spin_t spin;
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uint16_t status;
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for (tries = 0; tries < 1000; tries++) {
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/* wait for up to 1 second for the bus to become free */
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spin_init(&spin, 1000000);
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do {
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status = omap_i2c_read_status();
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if ((status & (1 << BB)) == 0) {
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return 0; /* bus is free */
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return 1; /* bus is free */
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}
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micro_delay(1000);
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}
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} while (spin_check(&spin));
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return -1; /* timeout expired */
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}
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/*
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* Clean up after a transfer
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*/
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static int
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omap_i2c_release_bus(void)
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{
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omap_i2c_write_status(0x7fff);
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micro_delay(50000);
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return 0;
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return 0; /* timeout expired */
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}
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static void
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@ -380,14 +363,14 @@ omap_i2c_clkconf(int i2c_bus_id)
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{
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clkconf_init();
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if (omap_i2c_bus->bus_type == dm37xx) {
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if (omap_i2c_bus->bus_type == DM37XX_I2C_BUS) {
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clkconf_set(CM_ICLKEN1_CORE, BIT((15 + i2c_bus_id)),
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0xffffffff);
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clkconf_set(CM_FCLKEN1_CORE, BIT((15 + i2c_bus_id)),
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0xffffffff);
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} else if (omap_i2c_bus->bus_type == am335x) {
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} else if (omap_i2c_bus->bus_type == AM335X_I2C_BUS) {
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switch (i2c_bus_id) {
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case 0:
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@ -417,7 +400,7 @@ omap_i2c_padconf(int i2c_bus_id)
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padconf_init();
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if (omap_i2c_bus->bus_type == am335x) {
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if (omap_i2c_bus->bus_type == AM335X_I2C_BUS) {
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/* use the options suggested in starterware driver */
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pinopts =
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@ -466,27 +449,27 @@ omap_i2c_padconf(int i2c_bus_id)
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static int
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omap_i2c_soft_reset(void)
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{
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int tries;
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spin_t spin;
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/* Disable to do soft reset */
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reg_write(omap_i2c_bus->regs->I2C_CON, 0);
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write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_CON, 0);
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micro_delay(50000);
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/* Do a soft reset */
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reg_write(omap_i2c_bus->regs->I2C_SYSC, (1 << SRST));
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write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_SYSC, (1 << SRST));
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/* Have to temporarily enable I2C to read RDONE */
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reg_set_bit(omap_i2c_bus->regs->I2C_CON, I2C_EN);
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set16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_CON, (1<<I2C_EN), (1<<I2C_EN));
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micro_delay(50000);
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/* wait for reset to complete */
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for (tries = 0; tries < 10000; tries++) {
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if (reg_read(omap_i2c_bus->regs->I2C_SYSS) & (1 << RDONE)) {
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/* wait up to 3 seconds for reset to complete */
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spin_init(&spin, 3000000);
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do {
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if (read16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_SYSS) & (1 << RDONE)) {
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return OK;
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}
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micro_delay(1000);
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}
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} while (spin_check(&spin));
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log_warn(&log, "Tried soft reset, but bus never came back.\n");
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return EIO;
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@ -532,10 +515,10 @@ omap_i2c_intr_enable(void)
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intmask |= (1 << NACK);
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intmask |= (1 << AL);
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if (omap_i2c_bus->bus_type == am335x) {
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reg_write(omap_i2c_bus->regs->I2C_IRQENABLE_SET, intmask);
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} else if (omap_i2c_bus->bus_type == dm37xx) {
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reg_write(omap_i2c_bus->regs->I2C_IE, intmask);
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if (omap_i2c_bus->bus_type == AM335X_I2C_BUS) {
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write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_IRQENABLE_SET, intmask);
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} else if (omap_i2c_bus->bus_type == DM37XX_I2C_BUS) {
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write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_IE, intmask);
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} else {
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log_warn(&log, "Don't know how to enable interrupts.\n");
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}
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@ -546,39 +529,39 @@ omap_i2c_bus_init(void)
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{
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/* Ensure i2c module is disabled before setting prescalar & bus speed */
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reg_write(omap_i2c_bus->regs->I2C_CON, 0);
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write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_CON, 0);
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micro_delay(50000);
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/* Disable autoidle */
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reg_clear_bit(omap_i2c_bus->regs->I2C_SYSC, AUTOIDLE);
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set16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_SYSC, (1<<AUTOIDLE), (0<<AUTOIDLE));
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/* Set prescalar to obtain 12 MHz i2c module clock */
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reg_write(omap_i2c_bus->regs->I2C_PSC,
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write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_PSC,
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((omap_i2c_bus->functional_clock / omap_i2c_bus->module_clock) -
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1));
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/* Set the bus speed */
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reg_write(omap_i2c_bus->regs->I2C_SCLL,
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write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_SCLL,
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((omap_i2c_bus->module_clock / (2 * omap_i2c_bus->bus_speed)) -
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7));
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reg_write(omap_i2c_bus->regs->I2C_SCLH,
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write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_SCLH,
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((omap_i2c_bus->module_clock / (2 * omap_i2c_bus->bus_speed)) -
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5));
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/* Set own I2C address */
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if (omap_i2c_bus->bus_type == am335x) {
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reg_write(omap_i2c_bus->regs->I2C_OA, I2C_OWN_ADDRESS);
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} else if (omap_i2c_bus->bus_type == dm37xx) {
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reg_write(omap_i2c_bus->regs->I2C_OA0, I2C_OWN_ADDRESS);
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if (omap_i2c_bus->bus_type == AM335X_I2C_BUS) {
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write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_OA, I2C_OWN_ADDRESS);
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} else if (omap_i2c_bus->bus_type == DM37XX_I2C_BUS) {
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write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_OA0, I2C_OWN_ADDRESS);
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} else {
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log_warn(&log, "Don't know how to set own address.\n");
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}
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/* Set TX/RX Threshold to 1 and disable I2C DMA */
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reg_write(omap_i2c_bus->regs->I2C_BUF, 0x0000);
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write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_BUF, 0x0000);
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/* Bring the i2c module out of reset */
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reg_set_bit(omap_i2c_bus->regs->I2C_CON, I2C_EN);
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set16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_CON, (1<<I2C_EN), (1<<I2C_EN));
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micro_delay(50000);
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/*
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@ -592,11 +575,11 @@ omap_i2c_read_status(void)
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{
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uint16_t status = 0x0000;
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if (omap_i2c_bus->bus_type == am335x) {
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if (omap_i2c_bus->bus_type == AM335X_I2C_BUS) {
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/* TRM says to use RAW for polling for events */
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status = reg_read(omap_i2c_bus->regs->I2C_IRQSTATUS_RAW);
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} else if (omap_i2c_bus->bus_type == dm37xx) {
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status = reg_read(omap_i2c_bus->regs->I2C_STAT);
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status = read16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_IRQSTATUS_RAW);
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} else if (omap_i2c_bus->bus_type == DM37XX_I2C_BUS) {
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status = read16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_STAT);
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} else {
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log_warn(&log, "Don't know how to read i2c bus status.\n");
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}
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@ -607,11 +590,11 @@ omap_i2c_read_status(void)
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static void
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omap_i2c_write_status(uint16_t mask)
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{
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if (omap_i2c_bus->bus_type == am335x) {
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if (omap_i2c_bus->bus_type == AM335X_I2C_BUS) {
|
||||
/* write 1's to IRQSTATUS (not RAW) to clear the bits */
|
||||
reg_write(omap_i2c_bus->regs->I2C_IRQSTATUS, mask);
|
||||
} else if (omap_i2c_bus->bus_type == dm37xx) {
|
||||
reg_write(omap_i2c_bus->regs->I2C_STAT, mask);
|
||||
write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_IRQSTATUS, mask);
|
||||
} else if (omap_i2c_bus->bus_type == DM37XX_I2C_BUS) {
|
||||
write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_STAT, mask);
|
||||
} else {
|
||||
log_warn(&log, "Don't know how to clear i2c bus status.\n");
|
||||
}
|
||||
@ -621,27 +604,30 @@ static int
|
||||
omap_i2c_read(i2c_addr_t addr, uint8_t * buf, size_t buflen, int dostop)
|
||||
{
|
||||
int r, i;
|
||||
uint16_t conopts = 0;
|
||||
uint16_t pollmask = 0;
|
||||
uint16_t errmask = 0;
|
||||
uint16_t conopts;
|
||||
uint16_t pollmask;
|
||||
uint16_t errmask;
|
||||
|
||||
/* Set address of slave device */
|
||||
addr &= ADDRESS_MASK; /* sanitize address (10-bit max) */
|
||||
conopts = 0;
|
||||
addr &= MAX_I2C_SA_MASK; /* sanitize address (10-bit max) */
|
||||
if (addr > 0x7f) {
|
||||
/* 10-bit extended address in use, need to set XSA */
|
||||
conopts |= (1 << XSA);
|
||||
}
|
||||
|
||||
errmask = 0;
|
||||
errmask |= (1 << ROVR);
|
||||
errmask |= (1 << AERR);
|
||||
errmask |= (1 << NACK);
|
||||
errmask |= (1 << AL);
|
||||
|
||||
pollmask = 0;
|
||||
pollmask |= (1 << RRDY);
|
||||
|
||||
/* Set bytes to read and slave address */
|
||||
reg_write(omap_i2c_bus->regs->I2C_CNT, buflen);
|
||||
reg_write(omap_i2c_bus->regs->I2C_SA, addr);
|
||||
write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_CNT, buflen);
|
||||
write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_SA, addr);
|
||||
|
||||
/* Set control register */
|
||||
conopts |= (1 << I2C_EN); /* enabled */
|
||||
@ -652,7 +638,7 @@ omap_i2c_read(i2c_addr_t addr, uint8_t * buf, size_t buflen, int dostop)
|
||||
conopts |= (1 << STP); /* stop condition */
|
||||
}
|
||||
|
||||
reg_write(omap_i2c_bus->regs->I2C_CON, conopts);
|
||||
write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_CON, conopts);
|
||||
|
||||
for (i = 0; i < buflen; i++) {
|
||||
/* Data to read? */
|
||||
@ -669,7 +655,7 @@ omap_i2c_read(i2c_addr_t addr, uint8_t * buf, size_t buflen, int dostop)
|
||||
}
|
||||
|
||||
/* read a byte */
|
||||
buf[i] = reg_read(omap_i2c_bus->regs->I2C_DATA) & 0xff;
|
||||
buf[i] = read16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_DATA) & 0xff;
|
||||
|
||||
/* clear the read ready flag */
|
||||
omap_i2c_write_status(pollmask);
|
||||
@ -681,8 +667,14 @@ omap_i2c_read(i2c_addr_t addr, uint8_t * buf, size_t buflen, int dostop)
|
||||
return EIO;
|
||||
}
|
||||
|
||||
/* Wait for operation to complete */
|
||||
pollmask = (1<<ARDY); /* poll access ready bit */
|
||||
r = omap_i2c_poll(pollmask);
|
||||
if ((r & pollmask) == 0) {
|
||||
log_warn(&log, "Read operation never finished.\n");
|
||||
return EBUSY;
|
||||
}
|
||||
omap_i2c_write_status(0x7fff);
|
||||
micro_delay(50000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -691,26 +683,29 @@ static int
|
||||
omap_i2c_write(i2c_addr_t addr, const uint8_t * buf, size_t buflen, int dostop)
|
||||
{
|
||||
int r, i;
|
||||
uint16_t conopts = 0;
|
||||
uint16_t pollmask = 0;
|
||||
uint16_t errmask = 0;
|
||||
uint16_t conopts;
|
||||
uint16_t pollmask;
|
||||
uint16_t errmask;
|
||||
|
||||
/* Set address of slave device */
|
||||
addr &= ADDRESS_MASK; /* sanitize address (10-bit max) */
|
||||
conopts = 0;
|
||||
addr &= MAX_I2C_SA_MASK; /* sanitize address (10-bit max) */
|
||||
if (addr > 0x7f) {
|
||||
/* 10-bit extended address in use, need to set XSA */
|
||||
conopts |= (1 << XSA);
|
||||
}
|
||||
|
||||
pollmask = 0;
|
||||
pollmask |= (1 << XRDY);
|
||||
|
||||
errmask = 0;
|
||||
errmask |= (1 << ROVR);
|
||||
errmask |= (1 << AERR);
|
||||
errmask |= (1 << NACK);
|
||||
errmask |= (1 << AL);
|
||||
|
||||
reg_write(omap_i2c_bus->regs->I2C_CNT, buflen);
|
||||
reg_write(omap_i2c_bus->regs->I2C_SA, addr);
|
||||
write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_CNT, buflen);
|
||||
write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_SA, addr);
|
||||
|
||||
/* Set control register */
|
||||
conopts |= (1 << I2C_EN); /* enabled */
|
||||
@ -723,7 +718,7 @@ omap_i2c_write(i2c_addr_t addr, const uint8_t * buf, size_t buflen, int dostop)
|
||||
}
|
||||
|
||||
omap_i2c_write_status(0x7fff);
|
||||
reg_write(omap_i2c_bus->regs->I2C_CON, conopts);
|
||||
write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_CON, conopts);
|
||||
|
||||
for (i = 0; i < buflen; i++) {
|
||||
|
||||
@ -737,7 +732,7 @@ omap_i2c_write(i2c_addr_t addr, const uint8_t * buf, size_t buflen, int dostop)
|
||||
return EBUSY;
|
||||
}
|
||||
|
||||
reg_write(omap_i2c_bus->regs->I2C_DATA, buf[i]);
|
||||
write16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_DATA, buf[i]);
|
||||
|
||||
/* clear the write ready flag */
|
||||
omap_i2c_write_status(pollmask);
|
||||
@ -745,11 +740,18 @@ omap_i2c_write(i2c_addr_t addr, const uint8_t * buf, size_t buflen, int dostop)
|
||||
|
||||
r = omap_i2c_read_status();
|
||||
if ((r & (1 << NACK)) != 0) {
|
||||
log_warn(&log, "NACK\n");
|
||||
return EIO;
|
||||
}
|
||||
|
||||
/* Wait for operation to complete */
|
||||
pollmask = (1<<ARDY); /* poll access ready bit */
|
||||
r = omap_i2c_poll(pollmask);
|
||||
if ((r & pollmask) == 0) {
|
||||
log_warn(&log, "Write operation never finished.\n");
|
||||
return EBUSY;
|
||||
}
|
||||
omap_i2c_write_status(0x7fff);
|
||||
micro_delay(50000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -826,15 +828,15 @@ omap_interface_setup(int (**process) (minix_i2c_ioctl_exec_t * ioctl_exec),
|
||||
omap_i2c_bus_init();
|
||||
|
||||
/* Get I2C Revision */
|
||||
if (omap_i2c_bus->bus_type == am335x) {
|
||||
if (omap_i2c_bus->bus_type == AM335X_I2C_BUS) {
|
||||
/* I2C_REVLO revision: major (bits 10-8), minor (bits 5-0) */
|
||||
i2c_rev = reg_read(omap_i2c_bus->regs->I2C_REVNB_LO);
|
||||
i2c_rev = read16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_REVNB_LO);
|
||||
major = (i2c_rev >> 8) & 0x07;
|
||||
minor = i2c_rev & 0x3f;
|
||||
|
||||
} else if (omap_i2c_bus->bus_type == dm37xx) {
|
||||
} else if (omap_i2c_bus->bus_type == DM37XX_I2C_BUS) {
|
||||
/* I2C_REV revision: major (bits 7-4), minor (bits 3-0) */
|
||||
i2c_rev = reg_read(omap_i2c_bus->regs->I2C_REV);
|
||||
i2c_rev = read16(omap_i2c_bus->mapped_addr + omap_i2c_bus->regs->I2C_REV);
|
||||
major = (i2c_rev >> 4) & 0x0f;
|
||||
minor = i2c_rev & 0x0f;
|
||||
} else {
|
||||
|
||||
@ -115,7 +115,7 @@
|
||||
|
||||
/* Masks */
|
||||
|
||||
#define ADDRESS_MASK (0x3ff) /* Highest 10 bit address -- 9..0 */
|
||||
#define MAX_I2C_SA_MASK (0x3ff) /* Highest 10 bit address -- 9..0 */
|
||||
|
||||
/* Bit Offsets within Registers (only those used are listed) */
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user