arm:mmc driver refactor.
Generalize the usage of mmc_send_cmd function to allow it to transfer data and remove direct invocations to mmchs_send_cmd. Change-Id: Iabb9a7d3f4ec57536407b369531ded2b8b649cce
This commit is contained in:
Kees Jongenburger
Kees Jongenburger
parent
2e3046757a
commit
718114d9b0
@ -3,6 +3,7 @@
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#include <minix/com.h>
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#include <minix/vm.h>
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#include <minix/spin.h>
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#include <minix/mmio.h>
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#include <sys/mman.h>
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#include <sys/time.h>
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@ -36,11 +37,12 @@ static int hook_id = 1;
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#define OMAP3_MMC1_IRQ 83 /* MMC/SD module 1 */
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#endif
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#ifdef AM335X
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#define OMAP3_MMC1_IRQ 64 /* MMC/SD module 1 */
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#define OMAP3_MMC1_IRQ 64 /* MMC/SD module 1 */
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#endif
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#endif
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#define SANE_TIMEOUT 500000 /* 500 MS */
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/*
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* Define a structure to be used for logging
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*/
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@ -50,37 +52,6 @@ static struct mmclog log = {
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.log_func = default_log
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};
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#define REG(x)(*((volatile uint32_t *)(x)))
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#define BIT(x)(0x1 << x)
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/* Write a uint32_t value to a memory address. */
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static inline void
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write32(uint32_t address, uint32_t value)
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{
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REG(address) = value;
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}
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/* Read an uint32_t from a memory address */
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static inline uint32_t
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read32(uint32_t address)
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{
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return REG(address);
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}
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/* Set a 32 bits value depending on a mask */
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static inline void
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set32(uint32_t address, uint32_t mask, uint32_t value)
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{
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uint32_t val;
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val = read32(address);
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/* clear the bits */
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val &= ~(mask);
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/* apply the value using the mask */
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val |= (value & mask);
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write32(address, val);
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}
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static uint32_t base_address;
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/*
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@ -150,7 +121,7 @@ mmchs_init(uint32_t instance)
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value |= MMCHS_SD_SYSCONFIG_ENAWAKEUP_EN;
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/* Smart-idle */
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value |= MMCHS_SD_SYSCONFIG_SIDLEMODE_IDLE;
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/* Booth the interface and functional can be switched off */
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/* Both the interface and functional can be switched off */
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value |= MMCHS_SD_SYSCONFIG_CLOCKACTIVITY_OFF;
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/* Go into wake-up mode when possible */
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value |= MMCHS_SD_SYSCONFIG_STANDBYMODE_WAKEUP_INTERNAL;
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@ -199,8 +170,8 @@ mmchs_init(uint32_t instance)
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// @TODO Fix external clock enable , this one is very slow
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// but we first need faster context switching
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//set32(base_address + MMCHS_SD_SYSCTL, MMCHS_SD_SYSCTL_CLKD,
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// (0x20 << 6));
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// set32(base_address + MMCHS_SD_SYSCTL, MMCHS_SD_SYSCTL_CLKD,
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// (0x20 << 6));
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set32(base_address + MMCHS_SD_SYSCTL, MMCHS_SD_SYSCTL_CLKD,
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(0x5 << 6));
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@ -233,7 +204,7 @@ mmchs_init(uint32_t instance)
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* raised for unknown reasons */
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set32(base_address + MMCHS_SD_IE, MMCHS_SD_IE_ERROR_MASK, 0x0fffffffu);
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/* clean the error interrupts */
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/* clear the error interrupts */
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set32(base_address + MMCHS_SD_STAT, MMCHS_SD_STAT_ERROR_MASK,
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0xffffffffu);
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@ -312,12 +283,13 @@ intr_wait(int mask)
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#ifdef USE_INTR
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if (sys_irqenable(&hook_id) != OK)
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printf("Failed to enable irqenable irq\n");
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/* Wait for a task completion interrupt. */
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/* Wait for a task completion interrupt. */
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message m;
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int ipc_status;
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int ticks = SANE_TIMEOUT * sys_hz() / 1000000;
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int ticks = SANE_TIMEOUT * sys_hz() / 1000000;
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if (ticks <= 0) ticks =1;
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if (ticks <= 0)
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ticks = 1;
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while (1) {
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int rr;
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sys_setalarm(ticks, 0);
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@ -337,10 +309,12 @@ intr_wait(int mask)
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if (v & mask) {
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sys_setalarm(0, 0);
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return 0;
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} else if (v & (1 << 15)){
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return 1; /* error */
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} else if (v & (1 << 15)) {
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return 1; /* error */
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} else {
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mmc_log_debug(&log, "unexpected HW interrupt 0x%08x mask 0X%08x\n", v, mask);
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mmc_log_debug(&log,
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"unexpected HW interrupt 0x%08x mask 0X%08x\n",
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v, mask);
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if (sys_irqenable(&hook_id) != OK)
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printf
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("Failed to re-enable irqenable irq\n");
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@ -363,24 +337,28 @@ intr_wait(int mask)
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blockdriver_mq_queue(&m, ipc_status);
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}
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}
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sys_setalarm(0, 0); /* cancel the alarm */
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sys_setalarm(0, 0); /* cancel the alarm */
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#else
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spin_t spin;
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spin_init(&spin, SANE_TIMEOUT);
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/* Wait for completion */
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int counter =0;
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int counter = 0;
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while (1 == 1) {
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counter ++;
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counter++;
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v = read32(base_address + MMCHS_SD_STAT);
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if (spin_check(&spin) == FALSE) {
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mmc_log_warn(&log, "Timeout waiting for interrupt (%d) value 0x%08x mask 0x%08x\n",counter, v,mask);
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mmc_log_warn(&log,
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"Timeout waiting for interrupt (%d) value 0x%08x mask 0x%08x\n",
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counter, v, mask);
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return 1;
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}
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if (v & mask) {
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return 0;
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} else if (v & 0xFF00) {
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mmc_log_debug(&log, "unexpected HW interrupt (%d) 0x%08x mask 0x%08x\n", v, mask);
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} else if (v & 0xFF00) {
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mmc_log_debug(&log,
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"unexpected HW interrupt (%d) 0x%08x mask 0x%08x\n",
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v, mask);
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return 1;
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}
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}
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@ -448,6 +426,8 @@ mmc_send_cmd(struct mmc_command *c)
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/* convert the command to a hsmmc command */
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int ret;
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uint32_t cmd, arg;
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uint32_t count;
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uint32_t value;
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cmd = MMCHS_SD_CMD_INDX_CMD(c->cmd);
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arg = c->args;
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@ -468,6 +448,45 @@ mmc_send_cmd(struct mmc_command *c)
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return 1;
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}
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/* read single block */
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if (c->cmd == MMC_READ_BLOCK_SINGLE) {
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cmd |= MMCHS_SD_CMD_DP_DATA; /* Command with data transfer */
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cmd |= MMCHS_SD_CMD_MSBS_SINGLE; /* single block */
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cmd |= MMCHS_SD_CMD_DDIR_READ; /* read data from card */
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}
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/* write single block */
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if (c->cmd == MMC_WRITE_BLOCK_SINGLE) {
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cmd |= MMCHS_SD_CMD_DP_DATA; /* Command with data transfer */
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cmd |= MMCHS_SD_CMD_MSBS_SINGLE; /* single block */
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cmd |= MMCHS_SD_CMD_DDIR_WRITE; /* write to the card */
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}
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/* check we are in a sane state */
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if ((read32(base_address + MMCHS_SD_STAT) & 0xffffu)) {
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mmc_log_warn(&log, "%s, interrupt already raised stat %08x\n",
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__FUNCTION__, read32(base_address + MMCHS_SD_STAT));
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write32(base_address + MMCHS_SD_STAT,
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MMCHS_SD_IE_CC_ENABLE_CLEAR);
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}
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if (cmd & MMCHS_SD_CMD_DP_DATA) {
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if (cmd & MMCHS_SD_CMD_DDIR_READ) {
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/* if we are going to read enable the buffer ready
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* interrupt */
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set32(base_address + MMCHS_SD_IE,
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MMCHS_SD_IE_BRR_ENABLE,
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MMCHS_SD_IE_BRR_ENABLE_ENABLE);
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} else {
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set32(base_address + MMCHS_SD_IE,
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MMCHS_SD_IE_BWR_ENABLE,
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MMCHS_SD_IE_BWR_ENABLE_ENABLE);
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}
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}
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set32(base_address + MMCHS_SD_BLK, MMCHS_SD_BLK_BLEN, 512);
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ret = mmchs_send_cmd(cmd, arg);
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/* copy response into cmd->resp */
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@ -488,14 +507,120 @@ mmc_send_cmd(struct mmc_command *c)
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return 1;
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}
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if (cmd & MMCHS_SD_CMD_DP_DATA) {
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count = 0;
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assert(c->data_len);
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if (cmd & MMCHS_SD_CMD_DDIR_READ) {
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if (intr_wait(MMCHS_SD_IE_BRR_ENABLE_ENABLE)) {
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intr_assert(MMCHS_SD_IE_BRR_ENABLE_ENABLE);
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mmc_log_warn(&log,
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"Timeout waiting for interrupt\n");
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return 1;
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}
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if (!(read32(base_address +
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MMCHS_SD_PSTATE) & MMCHS_SD_PSTATE_BRE_EN))
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{
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mmc_log_warn(&log,
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"Problem BRE should be true\n");
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return 1; /* We are not allowed to read
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* data from the data buffer */
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}
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for (count = 0; count < c->data_len; count += 4) {
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value = read32(base_address + MMCHS_SD_DATA);
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c->data[count] = *((char *) &value);
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c->data[count + 1] = *((char *) &value + 1);
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c->data[count + 2] = *((char *) &value + 2);
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c->data[count + 3] = *((char *) &value + 3);
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}
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/* Wait for TC */
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if (intr_wait(MMCHS_SD_IE_TC_ENABLE_ENABLE)) {
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intr_assert(MMCHS_SD_IE_TC_ENABLE_ENABLE);
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mmc_log_warn(&log,
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"Timeout waiting for interrupt\n");
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return 1;
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}
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write32(base_address + MMCHS_SD_STAT,
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MMCHS_SD_IE_TC_ENABLE_CLEAR);
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/* clear and disable the bbr interrupt */
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write32(base_address + MMCHS_SD_STAT,
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MMCHS_SD_IE_BRR_ENABLE_CLEAR);
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set32(base_address + MMCHS_SD_IE,
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MMCHS_SD_IE_BRR_ENABLE,
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MMCHS_SD_IE_BRR_ENABLE_DISABLE);
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} else {
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/* Wait for the MMCHS_SD_IE_BWR_ENABLE interrupt */
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if (intr_wait(MMCHS_SD_IE_BWR_ENABLE)) {
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intr_assert(MMCHS_SD_IE_BWR_ENABLE);
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mmc_log_warn(&log, "WFI failed\n");
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return 1;
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}
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/* clear the interrupt directly */
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intr_assert(MMCHS_SD_IE_BWR_ENABLE);
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if (!(read32(base_address +
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MMCHS_SD_PSTATE) & MMCHS_SD_PSTATE_BWE_EN))
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{
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mmc_log_warn(&log,
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"Error expected Buffer to be write enabled\n");
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return 1; /* not ready to write data */
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}
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for (count = 0; count < 512; count += 4) {
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while (!(read32(base_address +
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MMCHS_SD_PSTATE) &
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MMCHS_SD_PSTATE_BWE_EN)) {
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mmc_log_trace(&log,
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"Error expected Buffer to be write enabled(%d)\n",
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count);
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}
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*((char *) &value) = c->data[count];
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*((char *) &value + 1) = c->data[count + 1];
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*((char *) &value + 2) = c->data[count + 2];
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*((char *) &value + 3) = c->data[count + 3];
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write32(base_address + MMCHS_SD_DATA, value);
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}
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/* Wait for TC */
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if (intr_wait(MMCHS_SD_IE_TC_ENABLE_CLEAR)) {
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intr_assert(MMCHS_SD_IE_TC_ENABLE_CLEAR);
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mmc_log_warn(&log,
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"(Write) Timeout waiting for transfer complete\n");
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return 1;
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}
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intr_assert(MMCHS_SD_IE_TC_ENABLE_CLEAR);
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set32(base_address + MMCHS_SD_IE,
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MMCHS_SD_IE_BWR_ENABLE,
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MMCHS_SD_IE_BWR_ENABLE_DISABLE);
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}
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}
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return ret;
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}
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static struct mmc_command command;
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int
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mmc_send_app_cmd(struct sd_card_regs *card, struct mmc_command *c)
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{
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struct mmc_command command;
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command.cmd = MMC_APP_CMD;
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command.resp_type = RESP_LEN_48;
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command.args = MMC_ARG_RCA(card->rca);
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if (mmc_send_cmd(&command)) {
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return 1;
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}
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return mmc_send_cmd(c);
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}
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int
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card_goto_idle_state()
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{
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struct mmc_command command;
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command.cmd = MMC_GO_IDLE_STATE;
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command.resp_type = NO_RESPONSE;
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command.args = 0x00;
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@ -509,12 +634,16 @@ card_goto_idle_state()
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int
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card_identification()
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{
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struct mmc_command command;
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command.cmd = MMC_SEND_EXT_CSD;
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command.resp_type = RESP_LEN_48;
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command.args = MMCHS_SD_ARG_CMD8_VHS | MMCHS_SD_ARG_CMD8_CHECK_PATTERN;
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if (mmc_send_cmd(&command)) {
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// We currently only support 2.0,
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/* We currently only support 2.0, and 1.0 won't respond to
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* this request */
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mmc_log_warn(&log, "%s, non SDHC card inserted\n",
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__FUNCTION__);
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return 1;
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}
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@ -530,6 +659,7 @@ card_identification()
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int
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card_query_voltage_and_type(struct sd_card_regs *card)
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{
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struct mmc_command command;
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spin_t spin;
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command.cmd = MMC_APP_CMD;
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command.resp_type = RESP_LEN_48;
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@ -594,7 +724,7 @@ card_query_voltage_and_type(struct sd_card_regs *card)
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int
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card_identify(struct sd_card_regs *card)
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{
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struct mmc_command command;
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/* Send cmd 2 (all_send_cid) and expect 136 bits response */
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command.cmd = MMC_ALL_SEND_CID;
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command.resp_type = RESP_LEN_136;
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@ -629,6 +759,9 @@ card_identify(struct sd_card_regs *card)
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int
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card_csd(struct sd_card_regs *card)
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{
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/* Read the Card Specific Data register */
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struct mmc_command command;
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/* send_csd -> r2 response */
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command.cmd = MMC_SEND_CSD;
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command.resp_type = RESP_LEN_136;
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@ -657,6 +790,7 @@ card_csd(struct sd_card_regs *card)
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int
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select_card(struct sd_card_regs *card)
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{
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struct mmc_command command;
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command.cmd = MMC_SELECT_CARD;
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command.resp_type = RESP_LEN_48_CHK_BUSY;
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@ -672,60 +806,19 @@ int
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read_single_block(struct sd_card_regs *card,
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uint32_t blknr, unsigned char *buf)
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{
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uint32_t count;
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uint32_t value;
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struct mmc_command command;
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count = 0;
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command.cmd = MMC_READ_BLOCK_SINGLE;
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command.args = blknr;
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command.resp_type = RESP_LEN_48;
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command.data = buf;
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command.data_len = 512;
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set32(base_address + MMCHS_SD_IE, MMCHS_SD_IE_BRR_ENABLE,
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MMCHS_SD_IE_BRR_ENABLE_ENABLE);
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set32(base_address + MMCHS_SD_BLK, MMCHS_SD_BLK_BLEN, 512);
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/* read single block */
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if (mmchs_send_cmd(MMCHS_SD_CMD_INDX_CMD(MMC_READ_BLOCK_SINGLE)
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| MMCHS_SD_CMD_DP_DATA /* Command with data transfer */
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| MMCHS_SD_CMD_RSP_TYPE_48B /* type (R1) */
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| MMCHS_SD_CMD_MSBS_SINGLE /* single block */
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| MMCHS_SD_CMD_DDIR_READ /* read data from card */
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, blknr)) {
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if (mmc_send_cmd(&command)) {
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mmc_log_warn(&log, "Error sending command\n");
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return 1;
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}
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if (intr_wait(MMCHS_SD_IE_BRR_ENABLE_ENABLE)) {
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intr_assert(MMCHS_SD_IE_BRR_ENABLE_ENABLE);
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mmc_log_warn(&log, "Timeout waiting for interrupt\n");
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return 1;
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}
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if (!(read32(base_address + MMCHS_SD_PSTATE) & MMCHS_SD_PSTATE_BRE_EN)) {
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mmc_log_warn(&log, "Problem BRE should be true\n");
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return 1; /* We are not allowed to read data from the
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* data buffer */
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}
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for (count = 0; count < 512; count += 4) {
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value = read32(base_address + MMCHS_SD_DATA);
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buf[count] = *((char *) &value);
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buf[count + 1] = *((char *) &value + 1);
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buf[count + 2] = *((char *) &value + 2);
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buf[count + 3] = *((char *) &value + 3);
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}
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/* Wait for TC */
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||||
if (intr_wait(MMCHS_SD_IE_TC_ENABLE_ENABLE)) {
|
||||
intr_assert(MMCHS_SD_IE_TC_ENABLE_ENABLE);
|
||||
mmc_log_warn(&log, "Timeout waiting for interrupt\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
write32(base_address + MMCHS_SD_STAT, MMCHS_SD_IE_TC_ENABLE_CLEAR);
|
||||
|
||||
/* clear and disable the bbr interrupt */
|
||||
write32(base_address + MMCHS_SD_STAT, MMCHS_SD_IE_BRR_ENABLE_CLEAR);
|
||||
set32(base_address + MMCHS_SD_IE, MMCHS_SD_IE_BRR_ENABLE,
|
||||
MMCHS_SD_IE_BRR_ENABLE_DISABLE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -733,74 +826,22 @@ int
|
||||
write_single_block(struct sd_card_regs *card,
|
||||
uint32_t blknr, unsigned char *buf)
|
||||
{
|
||||
uint32_t count;
|
||||
uint32_t value;
|
||||
struct mmc_command command;
|
||||
|
||||
if ((read32(base_address + MMCHS_SD_STAT) & 0xffffu)) {
|
||||
mmc_log_warn(&log, "%s, interrupt already raised stat %08x\n",
|
||||
__FUNCTION__, read32(base_address + MMCHS_SD_STAT));
|
||||
write32(base_address + MMCHS_SD_STAT,
|
||||
MMCHS_SD_IE_CC_ENABLE_CLEAR);
|
||||
// return 1;
|
||||
}
|
||||
|
||||
set32(base_address + MMCHS_SD_IE, MMCHS_SD_IE_BWR_ENABLE,
|
||||
MMCHS_SD_IE_BWR_ENABLE_ENABLE);
|
||||
count = 0;
|
||||
|
||||
// set32(base_address + MMCHS_SD_IE, 0xfff , 0xfff);
|
||||
set32(base_address + MMCHS_SD_BLK, MMCHS_SD_BLK_BLEN, 512);
|
||||
|
||||
command.cmd = MMC_WRITE_BLOCK_SINGLE;
|
||||
command.args = blknr;
|
||||
command.resp_type = RESP_LEN_48;
|
||||
command.data = buf;
|
||||
command.data_len = 512;
|
||||
|
||||
/* write single block */
|
||||
if (mmchs_send_cmd(MMCHS_SD_CMD_INDX_CMD(MMC_WRITE_BLOCK_SINGLE)
|
||||
| MMCHS_SD_CMD_DP_DATA /* Command with data transfer */
|
||||
| MMCHS_SD_CMD_RSP_TYPE_48B /* type (R1b) */
|
||||
| MMCHS_SD_CMD_MSBS_SINGLE /* single block */
|
||||
| MMCHS_SD_CMD_DDIR_WRITE /* write to the card */
|
||||
, blknr)) {
|
||||
if (mmc_send_cmd(&command)) {
|
||||
mmc_log_warn(&log, "Write single block command failed\n");
|
||||
mmc_log_trace(&log, "STAT=(0x%08x)\n",
|
||||
read32(base_address + MMCHS_SD_STAT));
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Wait for the MMCHS_SD_IE_BWR_ENABLE interrupt */
|
||||
if (intr_wait(MMCHS_SD_IE_BWR_ENABLE)) {
|
||||
intr_assert(MMCHS_SD_IE_BWR_ENABLE);
|
||||
mmc_log_warn(&log, "WFI failed\n");
|
||||
return 1;
|
||||
}
|
||||
/* clear the interrupt directly */
|
||||
intr_assert(MMCHS_SD_IE_BWR_ENABLE);
|
||||
|
||||
if (!(read32(base_address + MMCHS_SD_PSTATE) & MMCHS_SD_PSTATE_BWE_EN)) {
|
||||
mmc_log_warn(&log,
|
||||
"Error expected Buffer to be write enabled\n");
|
||||
return 1; /* not ready to write data */
|
||||
}
|
||||
|
||||
|
||||
for (count = 0; count < 512; count += 4) {
|
||||
while (!(read32(base_address + MMCHS_SD_PSTATE) & MMCHS_SD_PSTATE_BWE_EN)){
|
||||
mmc_log_trace(&log, "Error expected Buffer to be write enabled(%d)\n", count);
|
||||
}
|
||||
*((char *) &value) = buf[count];
|
||||
*((char *) &value + 1) = buf[count + 1];
|
||||
*((char *) &value + 2) = buf[count + 2];
|
||||
*((char *) &value + 3) = buf[count + 3];
|
||||
write32(base_address + MMCHS_SD_DATA, value);
|
||||
}
|
||||
|
||||
|
||||
/* Wait for TC */
|
||||
if (intr_wait(MMCHS_SD_IE_TC_ENABLE_CLEAR)) {
|
||||
intr_assert(MMCHS_SD_IE_TC_ENABLE_CLEAR);
|
||||
mmc_log_warn(&log, "(Write) Timeout waiting for transfer complete\n");
|
||||
return 1;
|
||||
}
|
||||
intr_assert(MMCHS_SD_IE_TC_ENABLE_CLEAR);
|
||||
set32(base_address + MMCHS_SD_IE, MMCHS_SD_IE_BWR_ENABLE,
|
||||
MMCHS_SD_IE_BWR_ENABLE_DISABLE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user