Update vt6105
Change-Id: I8136a17eb47f626141bb20b9d6a30f82117425b7
This commit is contained in:
Jia-Ju Bai
David van Moolenbroek
parent
fee60e45e6
commit
8dc24c0650
0
minix/drivers/net/vt6105/Makefile
Executable file → Normal file
0
minix/drivers/net/vt6105/Makefile
Executable file → Normal file
@ -3,12 +3,13 @@ The vt6105 driver is for VIA Technology 6105/6106S Ethernet card.
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This driver is referred to Minix(3.4.0) rtl8169 driver,
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Linux(4.2.1) via-rhine driver and VT6105 Rhine III Specification(Rev 1.2).
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The supported PCI number is 1106:3106:1186:1403.
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Maybe other PCI numbers for VIA Rhine III can be supported.
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Revision 1.0 2016/10/18
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Authored by Jia-Ju Bai <baijiaju1990@163.com>
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Revision 1.1 2016/11/12
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Modification: Remove and rewrite Linux-derived code
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Authored by Jia-Ju Bai <baijiaju1990@163.com>
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Something can be improved:
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1. MII, WOL functions are not adequately defined and used.
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2. Link status report does not work well.
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84
minix/drivers/net/vt6105/io.h
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84
minix/drivers/net/vt6105/io.h
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@ -0,0 +1,84 @@
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#ifndef _IO_H
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#define _IO_H
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#include <sys/types.h>
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#include <minix/syslib.h>
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#include "vt6105.h"
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/* I/O function */
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static u8_t my_inb(u32_t port) {
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u32_t value;
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int r;
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#ifdef DMA_REG_MODE
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value = *(u8_t *)(port);
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#else
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if ((r = sys_inb(port, &value)) != OK)
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printf("vt6105: sys_inb failed: %d\n", r);
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#endif
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return (u8_t)value;
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}
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#define vt_in8(port, offset) (my_inb((port) + (offset)))
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static u16_t my_inw(u32_t port) {
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u32_t value;
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int r;
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#ifdef DMA_REG_MODE
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value = *(u16_t *)(port);
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#else
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if ((r = sys_inw(port, &value)) != OK)
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printf("vt6105: sys_inw failed: %d\n", r);
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#endif
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return (u16_t)value;
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}
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#define vt_in16(port, offset) (my_inw((port) + (offset)))
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static u32_t my_inl(u32_t port) {
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u32_t value;
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int r;
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#ifdef DMA_REG_MODE
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value = *(u32_t *)(port);
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#else
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if ((r = sys_inl(port, &value)) != OK)
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printf("vt6105: sys_inl failed: %d\n", r);
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#endif
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return value;
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}
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#define vt_in32(port, offset) (my_inl((port) + (offset)))
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static void my_outb(u32_t port, u8_t value) {
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int r;
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#ifdef DMA_REG_MODE
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*(u8_t *)(port) = value;
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#else
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if ((r = sys_outb(port, value)) != OK)
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printf("vt6105: sys_outb failed: %d\n", r);
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#endif
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}
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#define vt_out8(port, offset, value) \
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(my_outb(((port) + (offset)), (value)))
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static void my_outw(u32_t port, u16_t value) {
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int r;
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#ifdef DMA_REG_MODE
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*(u16_t *)(port) = value;
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#else
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if ((r = sys_outw(port, value)) != OK)
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printf("vt6105: sys_outw failed: %d\n", r);
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#endif
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}
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#define vt_out16(port, offset, value) \
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(my_outw(((port) + (offset)), (value)))
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static void my_outl(u16_t port, u32_t value) {
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int r;
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#ifdef DMA_REG_MODE
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*(u32_t *)(port) = value;
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#else
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if ((r = sys_outl(port, value)) != OK)
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printf("vt6105: sys_outl failed: %d\n", r);
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#endif
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}
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#define vt_out32(port, offset, value) \
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(my_outl(((port) + (offset)), (value)))
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#endif
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File diff suppressed because it is too large
Load Diff
0
minix/drivers/net/vt6105/vt6105.conf
Executable file → Normal file
0
minix/drivers/net/vt6105/vt6105.conf
Executable file → Normal file
@ -1,194 +1,140 @@
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#ifndef _vt_H
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#define _vt_H
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#include <minix/drivers.h>
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#include <minix/netdriver.h>
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#include <machine/pci.h>
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#include <minix/ds.h>
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#include <assert.h>
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/* PCI Register */
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#define VT_PCI_VID 0x00 /* Vendor ID */
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#define VT_PCI_DID 0x02 /* Device ID */
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#define VT_PCI_CMD 0x04 /* Command */
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#define VT_PCI_STS 0x06 /* Status */
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#define VT_PCI_RID 0x08 /* Revision ID */
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#define VT_PCI_CC 0x09 /* Class Code */
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#define VT_PCI_CLS 0x0c /* Cache Line Size */
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#define VT_PCI_LT 0x0d /* Latency Timer */
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#define VT_PCI_HT 0x0e /* Header Type */
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/* ======= General Parameter ======= */
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/* Global configure */
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#define DESC_BASE64
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/* Internal Register */
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#define VT_REG_ADDR 0x00 /* Ethernet Address */
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#define VT_REG_RCR 0x06 /* Receive Configure Request */
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#define VT_REG_TCR 0x07 /* Transmit Configure Request */
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#define VT_REG_CR 0x08 /* Control 0 */
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#define VT_REG_ISR 0x0c /* Interrupt Status */
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#define VT_REG_IMR 0x0e /* Interrupt Mask */
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#define VT_REG_MAR0 0x10 /* Multicast Address 0 */
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#define VT_REG_MAR1 0x14 /* Multicast Address 1 */
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#define VT_REG_RD_BASE 0x18 /* Receive Descriptor Base Address */
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#define VT_REG_TD_BASE 0x1c /* Transmit Descriptor Base Address */
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#define VT_REG_MII_CFG 0x6c /* MII Configuration */
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#define VT_REG_MII_STS 0x6d /* MII Status */
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#define VT_REG_BCR0 0x6e /* Bus Control 0 */
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#define VT_REG_BCR1 0x6f /* Bus Control 1 */
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#define VT_REG_MII_CR 0x70 /* MII Control */
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#define VT_REG_MII_ADDR 0x71 /* MII Interface Address*/
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#define VT_REG_MII_DATA 0x72 /* MII Data Port */
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#define VT_REG_EECSR 0x74 /* EEPROM Control/Status */
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#define VT_REG_CFG_A 0x78 /* Chip Configuration A */
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#define VT_REG_CFG_B 0x79 /* Chip Configuration B */
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#define VT_REG_CFG_C 0x7a /* Chip Configuration C */
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#define VT_REG_CFG_D 0x7b /* Chip Configuration D */
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#define VT_REG_MCR0 0x80 /* Miscellaneous Control 0 */
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#define VT_REG_MCR1 0x81 /* Miscellaneous Control 1 */
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#define VT_REG_STICK 0x83 /* Sticky Hardware Control */
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#define VT_REG_MISR 0x84 /* MII Interrupt Status */
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#define VT_REG_MIMR 0x86 /* MII Interrupt Mask */
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#define VT_REG_FCR0 0x98 /* Flow Control 0 */
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#define VT_REG_FCR1 0x99 /* Flow Control 1 */
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#define VT_REG_WOL_SET 0xA4 /* Wake On LAN Set */
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#define VT_REG_WOL_CLR 0xA0 /* Wake On LAN Clear */
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#define VT_REG_PCS_CLR 0xA5 /* Power Configuration Set */
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#define VT_REG_PCS_SET 0xA1 /* Power Configuration Clear */
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#define VT_REG_WOLC_SET 0xA7 /* WOL Configuration Set */
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#define VT_REG_WOLC_CLR 0xA3 /* WOL Configuration Clear */
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#define VT_REG_WOLS_SET 0xA8 /* WOL Status Clear */
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#define VT_REG_WOLS_CLR 0xAC /* WOL Status Set */
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/* Key internal register */
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#define REG_RCR 0x06
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#define REG_ISR 0x0c
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#define REG_IMR 0x0e
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#define REG_RX_DESC_BASEL 0x18
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#define REG_TX_DESC_BASEL 0x1c
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/* Interrupt Status/Mask Register */
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#define VT_INTR_RX_DONE 0x0001
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#define VT_INTR_TX_DONE 0x0002
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#define VT_INTR_RX_ERR 0x0004
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#define VT_INTR_TX_ERR 0x0008
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#define VT_INTR_RX_EMPTY 0x0020
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#define VT_INTR_PCI_ERR 0x0040
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#define VT_INTR_STS_MAX 0x0080
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#define VT_INTR_RX_EARLY 0x0100
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#define VT_INTR_TX_UNDER_RUN 0x0210
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#define VT_INTR_RX_OVERFLOW 0x0400
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#define VT_INTR_RX_DROPPED 0x0800
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#define VT_INTR_RX_NOBUF 0x1000
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#define VT_INTR_TX_ABORT 0x2000
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#define VT_INTR_PORT_CHANGE 0x4000
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#define VT_INTR_RX_WAKE_UP 0x8000
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#ifdef DESC_BASE_DMA64
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#define REG_RX_DESC_BASEU 0
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#define REG_TX_DESC_BASEU 0
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#endif
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/* Control Register Command */
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#define VT_CMD_START 0x0002
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#define VT_CMD_STOP 0x0004
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#define VT_CMD_RX_ON 0x0008
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#define VT_CMD_TX_ON 0x0010
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#define VT_CMD_TX_DEMAND 0x0020
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#define VT_CMD_RX_DEMAND 0x0040
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#define VT_CMD_EARLY_RX 0x0100
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#define VT_CMD_EARLY_TX 0x0200
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#define VT_CMD_FDUPLEX 0x0400
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#define VT_CMD_NO_POLL 0x0800
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#define VT_CMD_RESET 0x8000
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/* Key internal register width */
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#define WIDTH_REG_RCR 8
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#define WIDTH_REG_ISR 16
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#define WIDTH_REG_IMR 16
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/* Receive Configure Mode */
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#define VT_RCR_AP 0x10
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#define VT_RCR_AB 0x08
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#define VT_RCR_AM 0x04
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#define VT_RCR_AR 0x02
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#define VT_RCR_AE 0x01
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/* Interrupt statu and command */
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#define INTR_ISR_ERR 0x3ffc
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#define INTR_ISR_LINK_EVENT 0x4000
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#define INTR_ISR_RX_DONE 0x0001
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#define INTR_ISR_TX_DONE 0x0002
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#define INTR_ISR_CLEAR 0xbfbf
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#define INTR_IMR_ENABLE 0xfeff
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#define INTR_IMR_DISABLE 0x0000
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/* General Descriptor Flag */
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#define VT_DESC_OWN 0x80000000 /* Ownership */
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#define VT_DESC_FIRST 0x00000200 /* First Descriptor */
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#define VT_DESC_LAST 0x00000100 /* Last Descriptor */
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/* Descriptor status */
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#define DESC_STATUS_RX_RECV_ERR 0x000000bf
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#define DESC_STATUS_RX_RECV_CLEAR 0x80000000
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#define DESC_STATUS_TX_SEND_ERR 0x00008f10
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#define DESC_STATUS_TX_SEND_CLEAR 0x00000000
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/* Rx Descriptor Flag */
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#define VT_DESC_RX_LENMASK 0x7fff0000 /* Receive Frame Length Mask */
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#define VT_DESC_RX_OK 0x00008000 /* Receive OK */
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#define VT_DESC_RX_MAR 0x00002000 /* Multicast Address Received */
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#define VT_DESC_RX_BAR 0x00001000 /* Broadcast Address Received */
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#define VT_DESC_RX_PHY 0x00000800 /* Physical Address Received */
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#define VT_DESC_RX_LINK_ERR 0x00000080 /* Descriptor Link Structure Error */
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#define VT_DESC_RX_RUNT 0x00000020 /* Runt Packet */
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#define VT_DESC_RX_LONG 0x00000010 /* Long Packet */
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#define VT_DESC_RX_FOV 0x00000008 /* FIFO Overflow */
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#define VT_DESC_RX_FAE 0x00000004 /* Frame Align Error */
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#define VT_DESC_RX_CRCE 0x00000002 /* CRC Error */
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#define VT_DESC_RX_ERR 0x00000001 /* Receive Error */
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#define VT_DESC_RX_ALL_ERR (VT_DESC_RX_LINK_ERR | VT_DESC_RX_RUNT | \
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VT_DESC_RX_LONG | VT_DESC_RX_FOV | \
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VT_DESC_RX_FAE | VT_DESC_RX_CRCE | VT_DESC_RX_ERR)
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#define VT_DESC_RX_PACK (VT_DESC_FIRST | VT_DESC_LAST)
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/* Tx Descriptor Flag */
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#define VT_DESC_TX_ERR 0x00008000 /* Transmit Error */
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#define VT_DESC_TX_UDF 0x00000800 /* FIFO Underflow */
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#define VT_DESC_TX_CRS 0x00000400 /* Carrier Sense Lost Detect */
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#define VT_DESC_TX_OWC 0x00000200 /* Out of Window Collision */
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#define VT_DESC_TX_ABT 0x00000100 /* Excessive Collision Abort */
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#define VT_DESC_TX_CDH 0x00000010 /* Collision Detect */
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/* WOL status */
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#define VT_WOL_UCAST 0x10
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#define VT_WOL_MAGIC 0x20
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#define VT_WOL_MCAST 0x30
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#define VT_WOL_LINK_UP 0x40
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#define VT_WOL_LINK_DOWN 0x80
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/* Rx mode */
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#define RCR_UNICAST 0x10
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#define RCR_MULTICAST 0x04
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#define RCR_BROADCAST 0x08
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/* Link status */
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#define VT_LINK_UP 1
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#define VT_LINK_DOWN 0
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#define VT_LINK_UNKNOWN -1
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#define LINK_UP 1
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#define LINK_DOWN 0
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#define LINK_UNKNOWN -1
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#define VT_RX_BUF_SIZE 1536
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#define VT_TX_BUF_SIZE 1536
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#define VT_RX_DESC_NUM 64
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#define VT_TX_DESC_NUM 64
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/* Basic Rx/Tx parameters */
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#define RX_BUF_SIZE 1536
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#define TX_BUF_SIZE 1536
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#define RX_DESC_NUM 64
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#define TX_DESC_NUM 64
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/* #define VT6105_DEBUG */
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/* ======= Self-defined Parameter ======= */
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#define DESC_OWN 0x80000000
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#define DESC_FIRST 0x00000200
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#define DESC_LAST 0x00000100
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/* Data Descriptor */
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#define DESC_RX_LENMASK 0x7fff0000
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#define DESC_RX_OK 0x00008000
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#define DESC_RX_NORMAL (DESC_FIRST | DESC_LAST)
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#define REG_ADDR 0x00
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#define REG_TCR 0x07
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#define REG_CR 0x08
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#define REG_BCR0 0x6e
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#define REG_MCR1 0x81
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#define REG_STICK 0x83
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#define REG_MII_CFG 0x6c
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#define REG_MII_CR 0x70
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#define REG_MII_ADDR 0x71
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#define REG_MII_DATA 0x72
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#define REG_WOL_SET 0xa4
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#define REG_WOLC_SET 0xa7
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#define CMD_START 0x0002
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#define CMD_STOP 0x0004
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#define CMD_RX_ON 0x0008
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#define CMD_TX_ON 0x0010
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#define CMD_TX_DEMAND 0x0020
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#define CMD_RX_DEMAND 0x0040
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#define CMD_FDUPLEX 0x0400
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#define CMD_NO_POLL 0x0800
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#define CMD_RESET 0x8000
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/* ======= Data Descriptor ======= */
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typedef struct vt_desc {
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u32_t status; /* command/status */
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u32_t length; /* Buffer/Frame length */
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u32_t addr; /* DMA buffer address */
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u32_t next_desc; /* Next descriptor */
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u32_t status;
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u32_t length;
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u32_t addr;
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u32_t next;
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} vt_desc;
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/* Driver Data Structure */
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typedef struct vt_driver {
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u16_t vt_base_addr; /* Base address */
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int vt_revision; /* Revision ID */
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int vt_irq; /* IRQ number */
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int vt_mode;
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int vt_link; /* Whether link-up */
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int vt_recv_flag; /* Receive flag */
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int vt_send_flag; /* Send flag */
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int vt_report_link;
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int vt_tx_alive;
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int vt_tx_busy;
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u32_t base_addr; /* Base address */
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int revision; /* Revision ID */
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int irq; /* IRQ number */
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int mode;
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int link; /* Whether link-up */
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int recv_flag; /* Receive flag */
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int send_flag; /* Send flag */
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int tx_busy;
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/* Buffer */
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size_t vt_buf_size;
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char *vt_buf;
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size_t buf_size;
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char *buf;
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/* Rx data */
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int vt_rx_head;
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int rx_head;
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struct {
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phys_bytes buf_dma;
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char *buf;
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} vt_rx[VT_RX_DESC_NUM];
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vt_desc *vt_rx_desc; /* Rx descriptor buffer */
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phys_bytes vt_rx_desc_dma; /* Rx descriptor DMA buffer */
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} rx[RX_DESC_NUM];
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vt_desc *rx_desc; /* Rx descriptor buffer */
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phys_bytes rx_desc_dma; /* Rx descriptor DMA buffer */
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/* Tx data */
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int vt_tx_head;
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int vt_tx_tail;
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int tx_head;
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int tx_tail;
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struct {
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int busy;
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phys_bytes buf_dma;
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char *buf;
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} vt_tx[VT_TX_DESC_NUM];
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vt_desc *vt_tx_desc; /* Tx descriptor buffer */
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phys_bytes vt_tx_desc_dma; /* Tx descriptor DMA buffer */
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int vt_tx_busy_num; /* Number of busy Tx descriptors */
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} tx[TX_DESC_NUM];
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vt_desc *tx_desc; /* Tx descriptor buffer */
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phys_bytes tx_desc_dma; /* Tx descriptor DMA buffer */
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int tx_busy_num; /* Number of busy Tx descriptors */
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int vt_hook; /* IRQ hook id at kernel */
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eth_stat_t vt_stat;
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int hook; /* IRQ hook id at kernel */
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eth_stat_t stat;
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char vt_name[20];
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char name[20];
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} vt_driver;
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#endif
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