0a6a1f1d05
This brings our tree to NetBSD 7.0, as found on -current on the 10-10-2015. This updates: - LLVM to 3.6.1 - GCC to GCC 5.1 - Replace minix/commands/zdump with usr.bin/zdump - external/bsd/libelf has moved to /external/bsd/elftoolchain/ - Import ctwm - Drop sprintf from libminc Change-Id: I149836ac18e9326be9353958bab9b266efb056f0
64 lines
1.6 KiB
Makefile
64 lines
1.6 KiB
Makefile
# $NetBSD: Makefile,v 1.14 2015/01/29 20:41:35 joerg Exp $
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LIB= LLVMARMCodeGen
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.include <bsd.init.mk>
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.PATH: ${LLVM_SRCDIR}/lib/Target/ARM
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SRCS+= ARMAsmPrinter.cpp \
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ARMBaseInstrInfo.cpp \
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ARMBaseRegisterInfo.cpp \
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ARMConstantIslandPass.cpp \
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ARMConstantPoolValue.cpp \
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ARMExpandPseudoInsts.cpp \
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ARMFastISel.cpp \
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ARMFrameLowering.cpp \
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ARMHazardRecognizer.cpp \
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ARMISelDAGToDAG.cpp \
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ARMISelLowering.cpp \
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ARMInstrInfo.cpp \
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ARMLoadStoreOptimizer.cpp \
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ARMMCInstLower.cpp \
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ARMMachineFunctionInfo.cpp \
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ARMOptimizeBarriersPass.cpp \
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ARMRegisterInfo.cpp \
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ARMSelectionDAGInfo.cpp \
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ARMSubtarget.cpp \
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ARMTargetMachine.cpp \
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ARMTargetObjectFile.cpp \
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ARMTargetTransformInfo.cpp \
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A15SDOptimizer.cpp \
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MLxExpansionPass.cpp \
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Thumb1InstrInfo.cpp \
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Thumb1FrameLowering.cpp \
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Thumb1RegisterInfo.cpp \
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Thumb2ITBlockPass.cpp \
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Thumb2InstrInfo.cpp \
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Thumb2RegisterInfo.cpp \
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Thumb2SizeReduction.cpp
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TABLEGEN_SRC= ARM.td
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TABLEGEN_INCLUDES= -I${LLVM_SRCDIR}/lib/Target/ARM
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TABLEGEN_OUTPUT= \
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ARMGenRegisterInfo.inc|-gen-register-info \
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ARMGenInstrInfo.inc|-gen-instr-info \
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ARMGenCodeEmitter.inc|-gen-emitter \
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ARMGenMCCodeEmitter.inc|-gen-emitter \
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ARMGenMCPseudoLowering.inc|-gen-pseudo-lowering \
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ARMGenAsmWriter.inc|-gen-asm-writer \
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ARMGenAsmMatcher.inc|-gen-asm-matcher \
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ARMGenDAGISel.inc|-gen-dag-isel \
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ARMGenFastISel.inc|-gen-fast-isel \
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ARMGenCallingConv.inc|-gen-callingconv \
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ARMGenSubtargetInfo.inc|-gen-subtarget \
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ARMGenDisassemblerTables.inc|-gen-disassembler
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.include "${.PARSEDIR}/../../tablegen.mk"
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.if defined(HOSTLIB)
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.include <bsd.hostlib.mk>
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.else
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.include <bsd.lib.mk>
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.endif
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