140 lines
3.2 KiB
C
140 lines
3.2 KiB
C
#ifndef _SDR_H
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#define _SDR_H
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/* ======= General Parameter ======= */
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/* Global configure */
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#define DMA_LENGTH_BY_FRAME
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#define DMA_BASE_IOMAP
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#define MIXER_AC97
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#include <minix/audio_fw.h>
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#include <sys/types.h>
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#include <sys/ioc_sound.h>
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#include <minix/sound.h>
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#include <machine/pci.h>
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#include <sys/mman.h>
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#include "io.h"
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/* Subdevice type */
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#define DAC 0
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#define ADC 1
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#define MIX 2
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/* PCI number and driver name */
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#define VENDOR_ID 0x1013
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#define DEVICE_ID 0x6005
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#define DRIVER_NAME "CS4281"
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/* Volume option */
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#define GET_VOL 0
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#define SET_VOL 1
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/* Interrupt control */
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#define INTR_ENABLE 1
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#define INTR_DISABLE 0
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/* Interrupt status */
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#define INTR_STS_DAC 0x0100
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#define INTR_STS_ADC 0x0200
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/* ======= Self-defined Parameter ======= */
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#define REG_INTR_STS 0x0000
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#define REG_INTR_CTRL 0x0008
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#define REG_INTR_MASK 0x000c
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#define REG_CONF_WRITE 0x03e0
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#define REG_POWER_EXT 0x03e4
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#define REG_SPOWER_CTRL 0x03ec
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#define REG_CONF_LOAD 0x03f0
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#define REG_CLK_CTRL 0x0400
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#define REG_MASTER_CTRL 0x0420
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#define REG_CODEC_CTRL 0x0460
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#define REG_CODEC_STATUS 0x0464
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#define REG_CODEC_OSV 0x0468
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#define REG_CODEC_ADDR 0x046c
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#define REG_CODEC_DATA 0x0470
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#define REG_CODEC_SDA 0x047c
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#define REG_SOUND_POWER 0x0740
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#define REG_DAC_SAMPLE_RATE 0x0744
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#define REG_ADC_SAMPLE_RATE 0x0748
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#define REG_SRC_SLOT 0x075c
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#define REG_PCM_LVOL 0x0760
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#define REG_PCM_RVOL 0x0764
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#define REG_DAC_HDSR 0x00f0
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#define REG_DAC_DCC 0x0114
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#define REG_DAC_DMR 0x0150
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#define REG_DAC_DCR 0x0154
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#define REG_DAC_FCR 0x0180
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#define REG_DAC_FSIC 0x0214
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#define REG_ADC_HDSR 0x00f4
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#define REG_ADC_DCC 0x0124
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#define REG_ADC_DMR 0x0158
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#define REG_ADC_DCR 0x015c
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#define REG_ADC_FCR 0x0184
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#define REG_ADC_FSIC 0x0214
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#define REG_DAC_DMA_ADDR 0x0118
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#define REG_DAC_DMA_LEN 0x011c
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#define REG_ADC_DMA_ADDR 0x0128
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#define REG_ADC_DMA_LEN 0x012c
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#define CODEC_REG_POWER 0x26
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#define STS_CODEC_DONE 0x0008
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#define STS_CODEC_VALID 0x0002
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#define CMD_POWER_DOWN (1 << 14)
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#define CMD_PORT_TIMING (1 << 16)
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#define CMD_AC97_MODE (1 << 1)
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#define CMD_MASTER_SERIAL (1 << 0)
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#define CMD_INTR_ENABLE 0x03
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#define CMD_INTR_DMA 0x00040000
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#define CMD_INTR_DMA0 0x0100
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#define CMD_INTR_DMA1 0x0200
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#define CMD_DMR_INIT 0x50
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#define CMD_DMR_WRITE 0x08
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#define CMD_DMR_READ 0x04
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#define CMD_DMR_BIT8 (1 << 16)
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#define CMD_DMR_MONO (1 << 17)
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#define CMD_DMR_UNSIGN (1 << 19)
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#define CMD_DMR_BIT32 (1 << 20)
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#define CMD_DMR_SWAP (1 << 22)
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#define CMD_DMR_POLL (1 << 28)
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#define CMD_DMR_DMA (1 << 29)
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#define CMD_DCR_MASK (1 << 0)
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#define CMD_FCR_FEN (1 << 31)
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#define CMD_DAC_FCR_INIT 0x01002000
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#define CMD_ADC_FCR_INIT 0x0b0a2020
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static u32_t dcr_data, dmr_data, fcr_data;
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static u32_t g_sample_rate[] = {
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48000, 44100, 22050, 16000, 11025, 8000
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};
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/* Driver Data Structure */
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typedef struct aud_sub_dev_conf_t {
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u32_t stereo;
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u16_t sample_rate;
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u32_t nr_of_bits;
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u32_t sign;
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u32_t busy;
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u32_t fragment_size;
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u8_t format;
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} aud_sub_dev_conf_t;
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typedef struct DEV_STRUCT {
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char *name;
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u16_t vid;
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u16_t did;
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u32_t devind;
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u32_t base[6];
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char irq;
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char revision;
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u32_t intr_status;
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} DEV_STRUCT;
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void dev_mixer_write(u32_t *base, u32_t reg, u32_t val);
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u32_t dev_mixer_read(u32_t *base, u32_t reg);
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#endif
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