f7df02e747
This is a driver-breaking update to the netdriver library, which is
used by all network drivers. The aim of this change is to make the
library more compatible with NetBSD, and in particular with various
features that are expected to be supported by the NetBSD userland.
The main changes made by this patch are the following:
- each network driver now has a NetBSD-style short device name;
- drivers are not expected to receive packets right after startup;
- extended support for receipt modes, including multicast lists;
- support for multiple parallel send, receive requests;
- embedding of I/O vectors in send and receive requests;
- support for capabilities, including checksum offloading;
- support for reporting link status updates to the TCP/IP stack;
- support for setting and retrieving media status;
- support for changing the hardware (MAC) address;
- support for NetBSD interface flags IFF_DEBUG, IFF_LINK[0-2];
- support for NetBSD error statistics;
- support for regular time-based ("tick") callbacks.
IMPORTANT: this patch applies a minimal update to the existing drivers
in order to make them work at all with the new netdriver library. It
however does *not* change all drivers to make use of the new features.
In fact, strictly speaking, all drivers are now violating requirements
imposed by the new library in one way or another, most notably by
enabling packet receipt when starting the driver. Changing all the
drivers to be compliant, and to support the newly added options, is
left to future patches. The existing drivers should currently *not*
be taken as examples of how to implement a new network driver!
With that said, a few drivers have already been changed to make use of
some of the new features: fxp, e1000, rtl8139, and rtl8169 now report
link and media status, and the last three of those now support setting
the hardware MAC address on the fly. In addition, dp8390 has been
changed to default to PCI autoconfiguration if no configuration is
specified through environment variables.
Change-Id: I4b3ea9c0b9bc25d5b0609c6ff256fb0db71cdc42
123 lines
6.3 KiB
C
123 lines
6.3 KiB
C
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/* ====== ethernet card info. ====== */
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typedef struct ether_card
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{
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unsigned int ec_mode;
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port_t ec_port;
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int ec_irq;
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int ec_hook;
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} ether_card_t;
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/*
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* NOTE: Not all the CSRs are defined. Just the ones that were deemed
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* necessary or potentially useful.
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*/
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/* Control and Status Register Addresses */
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#define LANCE_CSR0 0 /* Controller Status Register */
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#define LANCE_CSR1 1 /* Initialization Block Address (Lower) */
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#define LANCE_CSR2 2 /* Initialization Block Address (Upper) */
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#define LANCE_CSR3 3 /* Interrupt Masks and Deferral Control */
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#define LANCE_CSR4 4 /* Test and Features Control */
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#define LANCE_CSR5 5 /* Extended Control and Interrupt */
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#define LANCE_CSR8 8 /* Logical Address Filter 0 */
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#define LANCE_CSR9 9 /* Logical Address Filter 1 */
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#define LANCE_CSR10 10 /* Logical Address Filter 2 */
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#define LANCE_CSR11 11 /* Logical Address Filter 3 */
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#define LANCE_CSR15 15 /* Mode */
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#define LANCE_CSR88 88 /* Chip ID Register (Lower) */
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#define LANCE_CSR89 89 /* Chip ID Register (Upper) */
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/* Control and Status Register 0 (CSR0) */
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#define LANCE_CSR0_ERR 0x8000 /* Error Occurred */
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#define LANCE_CSR0_BABL 0x4000 /* Transmitter Timeout Error */
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#define LANCE_CSR0_CERR 0x2000 /* Collision Error */
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#define LANCE_CSR0_MISS 0x1000 /* Missed Frame */
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#define LANCE_CSR0_MERR 0x0800 /* Memory Error */
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#define LANCE_CSR0_RINT 0x0400 /* Receive Interrupt */
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#define LANCE_CSR0_TINT 0x0200 /* Transmit Interrupt */
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#define LANCE_CSR0_IDON 0x0100 /* Initialization Done */
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#define LANCE_CSR0_INTR 0x0080 /* Interrupt Flag */
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#define LANCE_CSR0_IENA 0x0040 /* Interrupt Enable */
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#define LANCE_CSR0_RXON 0x0020 /* Receive On */
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#define LANCE_CSR0_TXON 0x0010 /* Transmit On */
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#define LANCE_CSR0_TDMD 0x0008 /* Transmit Demand */
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#define LANCE_CSR0_STOP 0x0004 /* Stop */
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#define LANCE_CSR0_STRT 0x0002 /* Start */
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#define LANCE_CSR0_INIT 0x0001 /* Init */
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/* Control and Status Register 3 (CSR3) */
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/* 0x8000 Reserved */
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#define LANCE_CSR3_BABLM 0x4000 /* Babble Mask */
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/* 0x2000 Reserved */
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#define LANCE_CSR3_MISSM 0x1000 /* Missed Frame Mask */
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#define LANCE_CSR3_MERRM 0x0800 /* Memory Error Mask */
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#define LANCE_CSR3_RINTM 0x0400 /* Receive Interrupt Mask */
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#define LANCE_CSR3_TINTM 0x0200 /* Transmit Interrupt Mask */
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#define LANCE_CSR3_IDONM 0x0100 /* Initialization Done Mask */
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/* 0x0080 Reserved */
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#define LANCE_CSR3_DXSUFLO 0x0040 /* Disable Transmit Stop on Underflow */
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#define LANCE_CSR3_LAPPEN 0x0020 /* Look Ahead Packet Processing Enable */
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#define LANCE_CSR3_DXMT2PD 0x0010 /* Disable Transmit Two Part Deferral */
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#define LANCE_CSR3_EMBA 0x0008 /* Enable Modified Back-off Algorithm */
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#define LANCE_CSR3_BSWP 0x0004 /* Byte Swap */
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/* 0x0002 Reserved
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* 0x0001 Reserved */
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/* Control and Status Register 4 (CSR4) */
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#define LANCE_CSR4_EN124 0x8000 /* Enable CSR124 Access */
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#define LANCE_CSR4_DMAPLUS 0x4000 /* Disable DMA Burst Transfer Counter */
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#define LANCE_CSR4_TIMER 0x2000 /* Enable Bus Activity Timer */
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#define LANCE_CSR4_DPOLL 0x1000 /* Disable Transmit Polling */
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#define LANCE_CSR4_APAD_XMT 0x0800 /* Auto Pad Transmit */
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#define LANCE_CSR4_ASTRP_RCV 0x0400 /* Auto Strip Receive */
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#define LANCE_CSR4_MFCO 0x0200 /* Missed Frame Counter Overflow */
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#define LANCE_CSR4_MFCOM 0x0100 /* Missed Frame Counter Overflow Mask */
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#define LANCE_CSR4_UINTCMD 0x0080 /* User Interrupt Command */
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#define LANCE_CSR4_UINT 0x0040 /* User Interrupt */
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#define LANCE_CSR4_RCVCCO 0x0020 /* Receive Collision Counter Overflow */
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#define LANCE_CSR4_RCVCCOM 0x0010 /* Receive Collision Counter Overflow
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* Mask */
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#define LANCE_CSR4_TXSTRT 0x0008 /* Transmit Start */
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#define LANCE_CSR4_TXSTRTM 0x0004 /* Transmit Start Mask */
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#define LANCE_CSR4_JAB 0x0002 /* Jabber Error */
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#define LANCE_CSR4_JABM 0x0001 /* Jabber Error Mask */
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/* Control and Status Register 5 (CSR5) */
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#define LANCE_CSR5_TOKINTD 0x8000 /* Transmit OK Interrupt Disable */
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#define LANCE_CSR5_LINTEN 0x4000 /* Last Transmit Interrupt Enable */
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/* 0x2000 Reserved
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* 0x1000 Reserved */
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#define LANCE_CSR5_SINT 0x0800 /* System Interrupt */
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#define LANCE_CSR5_SINTE 0x0400 /* System Interrupt Enable */
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#define LANCE_CSR5_SLPINT 0x0200 /* Sleep Interrupt */
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#define LANCE_CSR5_SLPINTE 0x0100 /* Sleep Interrupt Enable */
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#define LANCE_CSR5_EXDINT 0x0080 /* Excessive Deferral Interrupt */
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#define LANCE_CSR5_EXDINTE 0x0040 /* Excessive Deferral Interrupt Enable */
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#define LANCE_CSR5_MPPLBA 0x0020 /* Magic Packet Physical Logical Broadcast
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* Accept */
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#define LANCE_CSR5_MPINT 0x0010 /* Magic Packet Interrupt */
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#define LANCE_CSR5_MPINTE 0x0008 /* Magic Packet Interrupt Enable */
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#define LANCE_CSR5_MPEN 0x0004 /* Magic Packet Enable */
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#define LANCE_CSR5_MPMODE 0x0002 /* Magic Packet Mode */
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#define LANCE_CSR5_SPND 0x0001 /* Suspend */
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/* Control and Status Register 15 (CSR15) */
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#define LANCE_CSR15_PROM 0x8000 /* Promiscuous Mode */
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#define LANCE_CSR15_DRCVBC 0x4000 /* Disable Receive Broadcast */
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#define LANCE_CSR15_DRCVPA 0x2000 /* Disable Receive Physical Address */
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#define LANCE_CSR15_DLNKTST 0x1000 /* Disable Link Status */
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#define LANCE_CSR15_DAPC 0x0800 /* Disable Automatic Polarity Correction */
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#define LANCE_CSR15_MENDECL 0x0400 /* MENDEC Loopback Mode */
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#define LANCE_CSR15_LRT 0x0200 /* Low Receive Threshold (T-MAU Mode) */
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#define LANCE_CSR15_TSEL 0x0200 /* Transmit Mode Select (AUI Mode) */
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/* 0x0100 Portsel[1]
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* 0x0080 Portsel[0] */
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#define LANCE_CSR15_INTL 0x0040 /* Internal Loopback */
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#define LANCE_CSR15_DRTY 0x0020 /* Disable Retry */
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#define LANCE_CSR15_FCOLL 0x0010 /* Force Collision */
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#define LANCE_CSR15_DXMTFCS 0x0008 /* Disable Transmit CRC (FCS) */
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#define LANCE_CSR15_LOOP 0x0004 /* Loopback Enable */
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#define LANCE_CSR15_DTX 0x0002 /* Disable Transmit */
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#define LANCE_CSR15_DRX 0x0001 /* Disable Receiver */
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