0a6a1f1d05
This brings our tree to NetBSD 7.0, as found on -current on the 10-10-2015. This updates: - LLVM to 3.6.1 - GCC to GCC 5.1 - Replace minix/commands/zdump with usr.bin/zdump - external/bsd/libelf has moved to /external/bsd/elftoolchain/ - Import ctwm - Drop sprintf from libminc Change-Id: I149836ac18e9326be9353958bab9b266efb056f0
256 lines
9.4 KiB
C
256 lines
9.4 KiB
C
/* $NetBSD: cpu_extended_state.h,v 1.9 2014/02/25 22:16:52 dsl Exp $ */
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#ifndef _X86_CPU_EXTENDED_STATE_H_
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#define _X86_CPU_EXTENDED_STATE_H_
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/*
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* This file contains definitions of structures that match the memory
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* layouts used x86 processors to save floating point registers and other
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* extended cpu state.
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* This includes registers (etc) used by SSE/SSE2/SSE3/SSSE3/SSE4 and
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* the later AVX instructions.
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* The definitions are such that any future 'extended state' should
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* be handled (provided the kernel doesn't need to know the actual contents.
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*
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* The actual structures the cpu accesses must be aligned to 16 for
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* FXSAVE and 64 for XSAVE. The types aren't aligned because copies
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* do not need extra alignment.
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*
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* The slightly different layout saved by the i387 fsave in also defined.
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* This is only normally written by pre Pentium II type cpus that don't
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* support the fxsave instruction.
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*
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* Associated save instructions:
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* FNSAVE: Saves x87 state in 108 bytes (original i387 layout).
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* Then reinitialies the fpu.
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* FSAVE: Encodes to FWAIT followed by FNSAVE.
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* FXSAVE: Saves the x87 state and XMM (aka SSE) registers to the
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* first 448 (max) bytes of a 512 byte area.
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* This layout does not match that written by FNSAVE.
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* XSAVE: Uses the same layout for the x87 and XMM registers,
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* followed by a 64byte header and separate save areas
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* for additional extended cpu state.
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* The x87 state is always saved, the others conditionally.
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* XSAVEOPT: As XSAVE but (IIRC) only writes the registers blocks
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* that have been modified.
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*/
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#ifdef __lint__
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/* Lint has different packing rules and doesn't understand __aligned() */
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#define __CTASSERT_NOLINT(x) __CTASSERT(1)
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#else
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#define __CTASSERT_NOLINT(x) __CTASSERT(x)
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#endif
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/*
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* Layout for code/data pointers relating to FP exceptions.
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* Marked 'packed' because they aren't always 64bit aligned.
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* Since the x86 cpu supports misaligned accesses it isn't
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* worth avoiding the 'packed' attribute.
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*/
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union fp_addr {
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uint64_t fa_64; /* Linear address for 64bit systems */
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struct {
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uint32_t fa_off; /* linear address for 32 bit */
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uint16_t fa_seg; /* code/data (etc) segment */
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uint16_t fa_opcode; /* last opcode (sometimes) */
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} fa_32;
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} __packed __aligned(4);
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/* The x87 registers are 80 bits */
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struct fpacc87 {
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uint64_t f87_mantissa; /* mantissa */
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uint16_t f87_exp_sign; /* exponent and sign */
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} __packed __aligned(2);
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/* The x87 registers padded out to 16 bytes for fxsave */
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struct fpaccfx {
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struct fpacc87 r __aligned(16);
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};
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/* The SSE/SSE2 registers are 128 bits */
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struct xmmreg {
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uint8_t xmm_bytes[16];
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};
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/* The AVX registers are 256 bits, but the low bits are the xmmregs */
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struct ymmreg {
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uint8_t ymm_bytes[16];
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};
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/*
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* Floating point unit registers (fsave instruction).
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* The s87_ac[] and fx_87_ac[] are relative to the stack top.
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* The 'tag word' contains 2 bits per register and refers to
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* absolute register numbers.
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* The cpu sets the tag values 0b01 (zero) and 0b10 (special) when a value
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* is loaded. The software need only set 0b00 (used) and 0xb11 (unused).
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* The fxsave 'Abridged tag word' in inverted.
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*/
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struct save87 {
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uint16_t s87_cw __aligned(4); /* control word (16bits) */
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uint16_t s87_sw __aligned(4); /* status word (16bits) */
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uint16_t s87_tw __aligned(4); /* tag word (16bits) */
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union fp_addr s87_ip; /* floating point instruction pointer */
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#define s87_opcode s87_ip.fa_32.fa_opcode /* opcode last executed (11bits) */
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union fp_addr s87_dp; /* floating operand offset */
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struct fpacc87 s87_ac[8]; /* accumulator contents, 0-7 */
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};
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__CTASSERT_NOLINT(sizeof (struct save87) == 108);
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/* FPU/MMX/SSE/SSE2 context */
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struct fxsave {
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/*0*/ uint16_t fx_cw; /* FPU Control Word */
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uint16_t fx_sw; /* FPU Status Word */
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uint8_t fx_tw; /* FPU Tag Word (abridged) */
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uint16_t fx_opcode; /* FPU Opcode */
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union fp_addr fx_ip; /* FPU Instruction Pointer */
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/*16*/ union fp_addr fx_dp; /* FPU Data pointer */
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uint32_t fx_mxcsr; /* MXCSR Register State */
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uint32_t fx_mxcsr_mask;
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struct fpaccfx fx_87_ac[8]; /* 8 x87 registers */
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struct xmmreg fx_xmm[16]; /* XMM regs (8 in 32bit modes) */
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uint8_t fx_rsvd[48];
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uint8_t fx_kernel[48]; /* Not written by the hardware */
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} __aligned(16);
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__CTASSERT_NOLINT(sizeof (struct fxsave) == 512);
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/* The end of the fsave buffer can be used by the operating system */
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struct fxsave_os {
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uint8_t fxo_fxsave[512 - 48];
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/* 48 bytes available, NB copied to/from userspace */
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uint16_t fxo_dflt_cw; /* Control word for signal handlers */
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};
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/*
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* For XSAVE a 64byte header follows the fxsave data.
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* Currently it only contains one field of which only 3 bits are defined.
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* Some other parts must be zero - zero it all.
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*
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* The xsh_xstate_bv bits match those of XCR0:
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* XCR0_X87 0x00000001 x87 FPU/MMX state
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* XCR0_SSE 0x00000002 SSE state
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* XCR0_AVX 0x00000004 AVX state (ymmn registers)
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*
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* The offsets and sizes of any save areas can be found by reading
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* the correct control registers.
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*/
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struct xsave_header {
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uint64_t xsh_fxsave[64]; /* to align in the union */
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uint64_t xsh_xstate_bv; /* bitmap of saved sub structures */
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uint64_t xsh_rsrvd[2]; /* must be zero */
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uint64_t xsh_reserved[5];/* best if zero */
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};
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__CTASSERT(sizeof (struct xsave_header) == 512 + 64);
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/*
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* The ymm save area actually follows the xsave_header.
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*/
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struct xsave_ymm {
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struct ymmreg xs_ymm[16]; /* High bits of YMM registers */
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};
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__CTASSERT(sizeof (struct xsave_ymm) == 256);
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/*
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* The following union is placed at the end of the pcb.
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* It is defined this way to separate the definitions and to
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* minimise the number of union/struct selectors.
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* NB: Some userspace stuff (eg firefox) uses it to parse ucontext.
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*/
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union savefpu {
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struct save87 sv_87;
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struct fxsave sv_xmm;
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#ifdef _KERNEL
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struct fxsave_os sv_os;
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struct xsave_header sv_xsave_hdr;
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#endif
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};
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/*
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* 80387 control and status word bits
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*
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* The only reference I can find to bits 0x40 and 0x80 in the control word
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* is for the Weitek 1167/3167.
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* I (dsl) can't find why the default word has 0x40 set.
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*
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* A stack error is signalled as an INVOP that also sets STACK_FAULT
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* (other INVOP do not clear STACK_FAULT).
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*/
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/* Interrupt masks (set masks interrupt) and status bits */
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#define EN_SW_INVOP 0x0001 /* Invalid operation */
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#define EN_SW_DENORM 0x0002 /* Denormalized operand */
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#define EN_SW_ZERODIV 0x0004 /* Divide by zero */
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#define EN_SW_OVERFLOW 0x0008 /* Overflow */
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#define EN_SW_UNDERFLOW 0x0010 /* Underflow */
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#define EN_SW_PRECLOSS 0x0020 /* Loss of precision */
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/* Status word bits (reserved in control word) */
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#define EN_SW_STACK_FAULT 0x0040 /* Stack under/overflow */
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#define EN_SW_ERROR_SUMMARY 0x0080 /* Unmasked error has ocurred */
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/* Control bits (badly named) */
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#define EN_SW_CTL_PREC 0x0300 /* Precision control */
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#define EN_SW_PREC_24 0x0000 /* Single precision */
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#define EN_SW_PREC_53 0x0200 /* Double precision */
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#define EN_SW_PREC_64 0x0300 /* Extended precision */
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#define EN_SW_CTL_ROUND 0x0c00 /* Rounding control */
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#define EN_SW_ROUND_EVEN 0x0000 /* Round to nearest even */
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#define EN_SW_ROUND_DOWN 0x0400 /* Round towards minus infinity */
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#define EN_SW_ROUND_UP 0x0800 /* Round towards plus infinity */
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#define EN_SW_ROUND_ZERO 0x0c00 /* Round towards zero (truncates) */
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#define EN_SW_CTL_INF 0x1000 /* Infinity control, not used */
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/*
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* The standard 0x87 control word from finit is 0x37F, giving:
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* round to nearest
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* 64-bit precision
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* all exceptions masked.
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*
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* NetBSD used to select:
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* round to nearest
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* 53-bit precision
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* all exceptions masked.
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* Stating: 64-bit precision often gives bad results with high level
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* languages because it makes the results of calculations depend on whether
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* intermediate values are stored in memory or in FPU registers.
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* Also some 'pathological divisions' give an error in the LSB because
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* the value is first rounded up when the 64bit mantissa is generated,
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* and then again when it is truncated to 53 bits.
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*
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* However the C language explicitly allows the extra precision.
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*
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* The iBCS control word has underflow, overflow, zero divide, and invalid
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* operation exceptions unmasked. But that causes an unexpected exception
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* in the test program 'paranoia' and makes denormals useless (DBL_MIN / 2
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* underflows). It doesn't make a lot of sense to trap underflow without
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* trapping denormals.
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*/
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#define __INITIAL_NPXCW__ 0x037f
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/* Modern NetBSD uses the default control word.. */
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#define __NetBSD_NPXCW__ __INITIAL_NPXCW__
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/* NetBSD before 6.99.26 forced IEEE double precision. */
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#define __NetBSD_COMPAT_NPXCW__ 0x127f
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/* FreeBSD leaves some exceptions unmasked as well. */
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#define __FreeBSD_NPXCW__ 0x1272
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/* iBCS2 goes a bit further and leaves the underflow exception unmasked. */
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#define __iBCS2_NPXCW__ 0x0262
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/* Linux just uses the default control word. */
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#define __Linux_NPXCW__ __INITIAL_NPXCW__
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/* SVR4 uses the same control word as iBCS2. */
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#define __SVR4_NPXCW__ 0x0262
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/*
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* The default MXCSR value at reset is 0x1f80, IA-32 Instruction
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* Set Reference, pg. 3-369.
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*
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* The low 6 bits of the mxcsr are the fp status bits (same order as x87).
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* Bit 6 is 'denormals are zero' (speeds up calculations).
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* Bits 7-16 are the interrupt mask bits (same order, 1 to mask).
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* Bits 13 and 14 are rounding control.
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* Bit 15 is 'flush to zero' - affects underflow.
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* Bits 16-31 must be zero.
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*/
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#define __INITIAL_MXCSR__ 0x1f80
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#define __INITIAL_MXCSR_MASK__ 0xffbf
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#endif /* _X86_CPU_EXTENDED_STATE_H_ */
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