95 lines
2.9 KiB
C
95 lines
2.9 KiB
C
#ifndef __OMAP_RTC_REGISTERS_H
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#define __OMAP_RTC_REGISTERS_H
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/* RTC Addresses for am335x (BeagleBone White / BeagleBone Black) */
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/* Base Addresses */
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#define AM335X_RTC_SS_BASE 0x44e3e000
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/* Size of RTC Register Address Range */
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#define AM335X_RTC_SS_SIZE 0x1000
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/* Register Offsets */
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#define AM335X_RTC_SS_SECONDS_REG 0x0
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#define AM335X_RTC_SS_MINUTES_REG 0x4
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#define AM335X_RTC_SS_HOURS_REG 0x8
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#define AM335X_RTC_SS_DAYS_REG 0xC
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#define AM335X_RTC_SS_MONTHS_REG 0x10
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#define AM335X_RTC_SS_YEARS_REG 0x14
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#define AM335X_RTC_SS_WEEKS_REG 0x18
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#define AM335X_RTC_SS_ALARM_SECONDS_REG 0x20
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#define AM335X_RTC_SS_ALARM_MINUTES_REG 0x24
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#define AM335X_RTC_SS_ALARM_HOURS_REG 0x28
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#define AM335X_RTC_SS_ALARM_DAYS_REG 0x2C
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#define AM335X_RTC_SS_ALARM_MONTHS_REG 0x30
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#define AM335X_RTC_SS_ALARM_YEARS_REG 0x34
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#define AM335X_RTC_SS_RTC_CTRL_REG 0x40
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#define AM335X_RTC_SS_RTC_STATUS_REG 0x44
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#define AM335X_RTC_SS_RTC_INTERRUPTS_REG 0x48
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#define AM335X_RTC_SS_RTC_COMP_LSB_REG 0x4C
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#define AM335X_RTC_SS_RTC_COMP_MSB_REG 0x50
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#define AM335X_RTC_SS_RTC_OSC_REG 0x54
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#define AM335X_RTC_SS_RTC_SCRATCH0_REG 0x60
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#define AM335X_RTC_SS_RTC_SCRATCH1_REG 0x64
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#define AM335X_RTC_SS_RTC_SCRATCH2_REG 0x68
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#define AM335X_RTC_SS_KICK0R 0x6C
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#define AM335X_RTC_SS_KICK1R 0x70
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#define AM335X_RTC_SS_RTC_REVISION 0x74
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#define AM335X_RTC_SS_RTC_SYSCONFIG 0x78
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#define AM335X_RTC_SS_RTC_IRQWAKEEN 0x7C
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#define AM335X_RTC_SS_ALARM2_SECONDS_REG 0x80
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#define AM335X_RTC_SS_ALARM2_MINUTES_REG 0x84
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#define AM335X_RTC_SS_ALARM2_HOURS_REG 0x88
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#define AM335X_RTC_SS_ALARM2_DAYS_REG 0x8C
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#define AM335X_RTC_SS_ALARM2_MONTHS_REG 0x90
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#define AM335X_RTC_SS_ALARM2_YEARS_REG 0x94
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#define AM335X_RTC_SS_RTC_PMIC 0x98
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#define AM335X_RTC_SS_RTC_DEBOUNCE 0x9C
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/* Constants */
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#define AM335X_RTC_SS_KICK0R_UNLOCK_MASK 0x83E70B13
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#define AM335X_RTC_SS_KICK1R_UNLOCK_MASK 0x95A4F1E0
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#define AM335X_RTC_SS_KICK0R_LOCK_MASK 0x546f6d20
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#define AM335X_RTC_SS_KICK1R_LOCK_MASK 0x436f7274
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/* Bits */
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/* RTC_SS_RTC_STATUS_REG */
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#define RTC_BUSY_BIT 0
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/* RTC_SS_RTC_CTRL_REG */
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#define RTC_STOP_BIT 0
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/* RTC_SS_RTC_SYSCONFIG */
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#define NOIDLE_BIT 0
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/* RTC_SS_RTC_OSC_REG */
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#define EN_32KCLK_BIT 6
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/* RTC_SS_RTC_PMIC */
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#define PWR_ENABLE_EN_BIT 16
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/* RTC_SS_RTC_INTERRUPTS_REG */
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#define IT_ALARM2_BIT 4
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/* Clocks */
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#define CM_RTC_RTC_CLKCTRL 0x800
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#define CM_RTC_RTC_CLKCTRL_IDLEST ((0<<17)|(0<<16))
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#define CM_RTC_RTC_CLKCTRL_MODULEMODE ((1<<1)|(0<<0))
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#define CM_RTC_RTC_CLKCTRL_MASK (CM_RTC_RTC_CLKCTRL_IDLEST|CM_RTC_RTC_CLKCTRL_MODULEMODE)
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#define CM_RTC_CLKSTCTRL 0x804
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#define CLKACTIVITY_RTC_32KCLK (1<<9)
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#define CLKACTIVITY_L4_RTC_GCLK (1<<8)
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#define CLKTRCTRL ((0<<1)|(0<<0))
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#define CM_RTC_CLKSTCTRL_MASK (CLKACTIVITY_RTC_32KCLK|CLKACTIVITY_L4_RTC_GCLK|CLKTRCTRL)
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int omap_rtc_init(void);
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int omap_rtc_get_time(struct tm *t, int flags);
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int omap_rtc_set_time(struct tm *t, int flags);
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int omap_rtc_pwr_off(void);
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void omap_rtc_exit(void);
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#endif /* __OMAP_RTC_REGISTERS_H */
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