b6cbf7203b
This patch imports the unmodified current version of NetBSD libc. The NetBSD includes are in /nbsd_include, while the libc code itself is split between lib/nbsd_libc and common/lib/libc.
130 lines
5.1 KiB
Groff
130 lines
5.1 KiB
Groff
.\" $NetBSD: atomic_ops.3,v 1.5 2010/04/14 08:49:49 jruoho Exp $
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.\"
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.\" Copyright (c) 2007, 2008 The NetBSD Foundation, Inc.
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.\" All rights reserved.
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.\"
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.\" This code is derived from software contributed to The NetBSD Foundation
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.\" by Jason R. Thorpe.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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.\" ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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.\" POSSIBILITY OF SUCH DAMAGE.
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.\"
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.Dd April 14, 2010
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.Dt ATOMIC_OPS 3
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.Os
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.Sh NAME
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.Nm atomic_ops
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.Nd atomic memory operations
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.\" .Sh LIBRARY
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.\" .Lb libc
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.Sh SYNOPSIS
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.In sys/atomic.h
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.Sh DESCRIPTION
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The
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.Nm atomic_ops
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family of functions provide atomic memory operations.
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There are 7 classes of atomic memory operations available:
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.Pp
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.Bl -tag -width "atomic_swap(3)" -offset indent
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.It Xr atomic_add 3
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These functions perform atomic addition.
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.It Xr atomic_and 3
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These functions perform atomic logical
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.Dq and .
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.It Xr atomic_cas 3
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These functions perform atomic compare-and-swap.
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.It Xr atomic_dec 3
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These functions perform atomic decrement.
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.It Xr atomic_inc 3
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These functions perform atomic increment.
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.It Xr atomic_or 3
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These functions perform atomic logical
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.Dq or .
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.It Xr atomic_swap 3
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These functions perform atomic swap.
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.El
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.Ss Synchronization Mechanisms
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Where the architecture does not provide hardware support for atomic compare
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and swap (CAS), atomicity is provided by a restartable sequence or by a
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spinlock.
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The chosen method is not ordinarily distinguishable by or visible to users
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of the interface.
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The following architectures can be assumed to provide CAS in hardware:
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alpha, amd64, i386, powerpc, powerpc64, sparc64.
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.Ss Scope and Restrictions
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If hardware CAS is available, the atomic operations are globally atomic:
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operations within a memory region shared between processes are
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guaranteed to be performed atomically.
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If hardware CAS is not available, it may only be assumed that the operations
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are atomic with respect to threads in the same process.
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Additionally, if hardware CAS is not available, the atomic operations must
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not be used within a signal handler.
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.Pp
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Users of atomic memory operations should not make assumptions about how
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the memory access is performed
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.Pq specifically, the width of the memory access .
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For this reason, applications making use of atomic memory operations should
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limit their use to regular memory.
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The results of using atomic memory operations on anything other than
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regular memory are undefined.
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.Pp
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Users of atomic memory operations should take care to modify any given
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memory location either entirely with atomic operations or entirely with
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some other synchronization mechanism.
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Intermixing of atomic operations with other synchronization mechanisms
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for the same memory location results in undefined behavior.
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.Ss Visibility and Ordering of Memory Accesses
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If hardware CAS is available, stores to the target memory location by an
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atomic operation will reach global visibility before the operation
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completes.
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If hardware CAS is not available, the store may not reach global visibility
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until some time after the atomic operation has completed.
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However, in all cases a subsequent atomic operation on the same memory cell
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will be delayed until the result of any preceeding operation has reached
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global visibility.
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.Pp
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Atomic operations are strongly ordered with respect to each other.
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The global visibility of other loads and stores before and after an atomic
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operation is undefined.
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Applications that require synchronization of loads and stores with respect
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to an atomic operation must use memory barriers.
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See
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.Xr membar_ops 3 .
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.Ss Performance
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Because atomic memory operations require expensive synchronization at the
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hardware level, applications should take care to minimize their use.
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In certain cases, it may be more appropriate to use a mutex, especially
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if more than one memory location will be modified.
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.Sh SEE ALSO
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.Xr atomic_add 3 ,
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.Xr atomic_and 3 ,
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.Xr atomic_cas 3 ,
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.Xr atomic_dec 3 ,
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.Xr atomic_inc 3 ,
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.Xr atomic_or 3 ,
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.Xr atomic_swap 3 ,
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.Xr membar_ops 3
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.Sh HISTORY
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The
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.Nm atomic_ops
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functions first appeared in
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.Nx 5.0 .
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