84d9c625bf
- Fix for possible unset uid/gid in toproto
- Fix for default mtree style
- Update libelf
- Importing libexecinfo
- Resynchronize GCC, mpc, gmp, mpfr
- build.sh: Replace params with show-params.
This has been done as the make target has been renamed in the same
way, while a new target named params has been added. This new
target generates a file containing all the parameters, instead of
printing it on the console.
- Update test48 with new etc/services (Fix by Ben Gras <ben@minix3.org)
get getservbyport() out of the inner loop
Change-Id: Ie6ad5226fa2621ff9f0dee8782ea48f9443d2091
363 lines
15 KiB
C
363 lines
15 KiB
C
/* $NetBSD: cacheinfo.h,v 1.17 2013/10/28 05:41:49 msaitoh Exp $ */
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#ifndef _X86_CACHEINFO_H_
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#define _X86_CACHEINFO_H_
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struct x86_cache_info {
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uint8_t cai_index;
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uint8_t cai_desc;
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uint8_t cai_associativity;
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u_int cai_totalsize; /* #entries for TLB, bytes for cache */
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u_int cai_linesize; /*
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* or page size for TLB,
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* or prefetch size
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*/
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#ifndef _KERNEL
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const char *cai_string;
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#endif
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};
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#define CAI_ITLB 0 /* Instruction TLB (4K pages) */
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#define CAI_ITLB2 1 /* Instruction TLB (2/4M pages) */
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#define CAI_DTLB 2 /* Data TLB (4K pages) */
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#define CAI_DTLB2 3 /* Data TLB (2/4M pages) */
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#define CAI_ICACHE 4 /* Instruction cache */
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#define CAI_DCACHE 5 /* Data cache */
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#define CAI_L2CACHE 6 /* Level 2 cache */
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#define CAI_L3CACHE 7 /* Level 3 cache */
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#define CAI_L1_1GBITLB 8 /* L1 1GB Page instruction TLB */
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#define CAI_L1_1GBDTLB 9 /* L1 1GB Page data TLB */
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#define CAI_L2_1GBITLB 10 /* L2 1GB Page instruction TLB */
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#define CAI_L2_1GBDTLB 11 /* L2 1GB Page data TLB */
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#define CAI_L2_ITLB 12 /* L2 Instruction TLB (4K pages) */
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#define CAI_L2_ITLB2 13 /* L2 Instruction TLB (2/4M pages) */
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#define CAI_L2_DTLB 14 /* L2 Data TLB (4K pages) */
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#define CAI_L2_DTLB2 15 /* L2 Data TLB (2/4M pages) */
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#define CAI_L2_STLB 16 /* Shared L2 TLB (4K pages) */
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#define CAI_L2_STLB2 17 /* Shared L2 TLB (4K/2M pages) */
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#define CAI_PREFETCH 18 /* Prefetch */
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#define CAI_COUNT 19
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/*
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* AMD Cache Info:
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*
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* Barcelona, Phenom:
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*
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* Function 8000.0005 L1 TLB/Cache Information
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* EAX -- L1 TLB 2/4MB pages
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* EBX -- L1 TLB 4K pages
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* ECX -- L1 D-cache
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* EDX -- L1 I-cache
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*
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* Function 8000.0006 L2 TLB/Cache Information
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* EAX -- L2 TLB 2/4MB pages
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* EBX -- L2 TLB 4K pages
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* ECX -- L2 Unified cache
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* EDX -- L3 Unified Cache
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*
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* Function 8000.0019 TLB 1GB Page Information
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* EAX -- L1 1GB pages
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* EBX -- L2 1GB pages
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* ECX -- reserved
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* EDX -- reserved
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*
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* Athlon, Duron:
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*
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* Function 8000.0005 L1 TLB/Cache Information
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* EAX -- L1 TLB 2/4MB pages
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* EBX -- L1 TLB 4K pages
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* ECX -- L1 D-cache
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* EDX -- L1 I-cache
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*
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* Function 8000.0006 L2 TLB/Cache Information
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* EAX -- L2 TLB 2/4MB pages
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* EBX -- L2 TLB 4K pages
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* ECX -- L2 Unified cache
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* EDX -- reserved
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*
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* K5, K6:
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*
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* Function 8000.0005 L1 TLB/Cache Information
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* EAX -- reserved
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* EBX -- TLB 4K pages
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* ECX -- L1 D-cache
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* EDX -- L1 I-cache
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*
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* K6-III:
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*
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* Function 8000.0006 L2 Cache Information
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* EAX -- reserved
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* EBX -- reserved
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* ECX -- L2 Unified cache
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* EDX -- reserved
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*/
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/* L1 TLB 2/4MB pages */
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#define AMD_L1_EAX_DTLB_ASSOC(x) (((x) >> 24) & 0xff)
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#define AMD_L1_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff)
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#define AMD_L1_EAX_ITLB_ASSOC(x) (((x) >> 8) & 0xff)
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#define AMD_L1_EAX_ITLB_ENTRIES(x) ( (x) & 0xff)
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/* L1 TLB 4K pages */
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#define AMD_L1_EBX_DTLB_ASSOC(x) (((x) >> 24) & 0xff)
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#define AMD_L1_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff)
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#define AMD_L1_EBX_ITLB_ASSOC(x) (((x) >> 8) & 0xff)
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#define AMD_L1_EBX_ITLB_ENTRIES(x) ( (x) & 0xff)
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/* L1 Data Cache */
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#define AMD_L1_ECX_DC_SIZE(x) ((((x) >> 24) & 0xff) * 1024)
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#define AMD_L1_ECX_DC_ASSOC(x) (((x) >> 16) & 0xff)
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#define AMD_L1_ECX_DC_LPT(x) (((x) >> 8) & 0xff)
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#define AMD_L1_ECX_DC_LS(x) ( (x) & 0xff)
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/* L1 Instruction Cache */
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#define AMD_L1_EDX_IC_SIZE(x) ((((x) >> 24) & 0xff) * 1024)
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#define AMD_L1_EDX_IC_ASSOC(x) (((x) >> 16) & 0xff)
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#define AMD_L1_EDX_IC_LPT(x) (((x) >> 8) & 0xff)
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#define AMD_L1_EDX_IC_LS(x) ( (x) & 0xff)
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/* Note for L2 TLB -- if the upper 16 bits are 0, it is a unified TLB */
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/* L2 TLB 2/4MB pages */
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#define AMD_L2_EAX_DTLB_ASSOC(x) (((x) >> 28) & 0xf)
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#define AMD_L2_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff)
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#define AMD_L2_EAX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf)
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#define AMD_L2_EAX_IUTLB_ENTRIES(x) ( (x) & 0xfff)
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/* L2 TLB 4K pages */
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#define AMD_L2_EBX_DTLB_ASSOC(x) (((x) >> 28) & 0xf)
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#define AMD_L2_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff)
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#define AMD_L2_EBX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf)
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#define AMD_L2_EBX_IUTLB_ENTRIES(x) ( (x) & 0xfff)
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/* L2 Cache */
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#define AMD_L2_ECX_C_SIZE(x) ((((x) >> 16) & 0xffff) * 1024)
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#define AMD_L2_ECX_C_ASSOC(x) (((x) >> 12) & 0xf)
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#define AMD_L2_ECX_C_LPT(x) (((x) >> 8) & 0xf)
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#define AMD_L2_ECX_C_LS(x) ( (x) & 0xff)
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/* L3 Cache */
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#define AMD_L3_EDX_C_SIZE(x) ((((x) >> 18) & 0xffff) * 1024 * 512)
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#define AMD_L3_EDX_C_ASSOC(x) (((x) >> 12) & 0xff)
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#define AMD_L3_EDX_C_LPT(x) (((x) >> 8) & 0xf)
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#define AMD_L3_EDX_C_LS(x) ( (x) & 0xff)
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/* L1 TLB 1GB pages */
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#define AMD_L1_1GB_EAX_DTLB_ASSOC(x) (((x) >> 28) & 0xf)
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#define AMD_L1_1GB_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff)
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#define AMD_L1_1GB_EAX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf)
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#define AMD_L1_1GB_EAX_IUTLB_ENTRIES(x) ( (x) & 0xfff)
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/* L2 TLB 1GB pages */
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#define AMD_L2_1GB_EBX_DUTLB_ASSOC(x) (((x) >> 28) & 0xf)
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#define AMD_L2_1GB_EBX_DUTLB_ENTRIES(x) (((x) >> 16) & 0xfff)
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#define AMD_L2_1GB_EBX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf)
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#define AMD_L2_1GB_EBX_IUTLB_ENTRIES(x) ( (x) & 0xfff)
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/*
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* VIA Cache Info:
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*
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* Nehemiah (at least)
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*
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* Function 8000.0005 L1 TLB/Cache Information
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* EAX -- reserved
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* EBX -- L1 TLB 4K pages
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* ECX -- L1 D-cache
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* EDX -- L1 I-cache
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*
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* Function 8000.0006 L2 Cache Information
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* EAX -- reserved
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* EBX -- reserved
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* ECX -- L2 Unified cache
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* EDX -- reserved
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*/
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/* L1 TLB 4K pages */
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#define VIA_L1_EBX_DTLB_ASSOC(x) (((x) >> 24) & 0xff)
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#define VIA_L1_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff)
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#define VIA_L1_EBX_ITLB_ASSOC(x) (((x) >> 8) & 0xff)
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#define VIA_L1_EBX_ITLB_ENTRIES(x) ( (x) & 0xff)
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/* L1 Data Cache */
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#define VIA_L1_ECX_DC_SIZE(x) ((((x) >> 24) & 0xff) * 1024)
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#define VIA_L1_ECX_DC_ASSOC(x) (((x) >> 16) & 0xff)
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#define VIA_L1_ECX_DC_LPT(x) (((x) >> 8) & 0xff)
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#define VIA_L1_ECX_DC_LS(x) ( (x) & 0xff)
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/* L1 Instruction Cache */
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#define VIA_L1_EDX_IC_SIZE(x) ((((x) >> 24) & 0xff) * 1024)
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#define VIA_L1_EDX_IC_ASSOC(x) (((x) >> 16) & 0xff)
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#define VIA_L1_EDX_IC_LPT(x) (((x) >> 8) & 0xff)
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#define VIA_L1_EDX_IC_LS(x) ( (x) & 0xff)
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/* L2 Cache (pre-Nehemiah) */
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#define VIA_L2_ECX_C_SIZE(x) ((((x) >> 24) & 0xff) * 1024)
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#define VIA_L2_ECX_C_ASSOC(x) (((x) >> 16) & 0xff)
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#define VIA_L2_ECX_C_LPT(x) (((x) >> 8) & 0xff)
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#define VIA_L2_ECX_C_LS(x) ( (x) & 0xff)
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/* L2 Cache (Nehemiah and newer) */
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#define VIA_L2N_ECX_C_SIZE(x) ((((x) >> 16) & 0xffff) * 1024)
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#define VIA_L2N_ECX_C_ASSOC(x) (((x) >> 12) & 0xf)
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#define VIA_L2N_ECX_C_LPT(x) (((x) >> 8) & 0xf)
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#define VIA_L2N_ECX_C_LS(x) ( (x) & 0xff)
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#ifdef _KERNEL
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#define __CI_TBL(a,b,c,d,e,f) { a, b, c, d, e }
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#else
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#define __CI_TBL(a,b,c,d,e,f) { a, b, c, d, e, f }
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#endif
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/*
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* XXX Currently organized mostly by cache type, but would be
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* XXX easier to maintain if it were in descriptor type order.
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*/
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#define INTEL_CACHE_INFO { \
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__CI_TBL(CAI_ITLB, 0x01, 4, 32, 4 * 1024, NULL), \
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__CI_TBL(CAI_ITLB2, 0x02, 0xff, 2, 4 * 1024 * 1024, NULL), \
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__CI_TBL(CAI_DTLB, 0x03, 4, 64, 4 * 1024, NULL), \
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__CI_TBL(CAI_DTLB2, 0x04, 4, 8, 4 * 1024 * 1024, NULL), \
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__CI_TBL(CAI_DTLB2, 0x05, 4, 32, 4 * 1024 * 1024, NULL), \
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__CI_TBL(CAI_ITLB2, 0x0b, 4, 4, 4 * 1024 * 1024, NULL), \
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__CI_TBL(CAI_ITLB, 0x4f, 0xff, 32, 4 * 1024, NULL), \
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__CI_TBL(CAI_ITLB, 0x50, 0xff, 64, 4 * 1024, "4K/4M: 64 entries"), \
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__CI_TBL(CAI_ITLB, 0x51, 0xff, 64, 4 * 1024, "4K/4M: 128 entries"),\
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__CI_TBL(CAI_ITLB, 0x52, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\
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__CI_TBL(CAI_ITLB, 0x55, 0xff, 64, 4 * 1024, "2M/4M: 7 entries"), \
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__CI_TBL(CAI_DTLB2, 0x56, 4, 16, 4 * 1024 * 1024, NULL), \
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__CI_TBL(CAI_DTLB2, 0x57, 4, 16, 4 * 1024, NULL), \
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__CI_TBL(CAI_DTLB2, 0x59, 0xff, 16, 4 * 1024, NULL), \
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__CI_TBL(CAI_DTLB, 0x5a, 0xff, 64, 4 * 1024, "2M/4M: 32 entries (L0)"), \
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__CI_TBL(CAI_DTLB, 0x5b, 0xff, 64, 4 * 1024, "4K/4M: 64 entries"), \
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__CI_TBL(CAI_DTLB, 0x5c, 0xff, 64, 4 * 1024, "4K/4M: 128 entries"),\
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__CI_TBL(CAI_DTLB, 0x5d, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\
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__CI_TBL(CAI_ITLB, 0x61, 0xff, 48, 4 * 1024, NULL), \
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__CI_TBL(CAI_L1_1GBDTLB,0x63, 4, 4,1024*1024 * 1024, NULL), \
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__CI_TBL(CAI_ITLB2, 0x76, 0xff, 8, 4 * 1024 * 1024, "2M/4M: 8 entries"), \
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__CI_TBL(CAI_ITLB, 0xb0, 4,128, 4 * 1024, NULL), \
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__CI_TBL(CAI_ITLB, 0xb1, 4, 64, 0, "8 2M/4 4M entries"), \
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__CI_TBL(CAI_ITLB, 0xb2, 4, 64, 4 * 1024, NULL), \
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__CI_TBL(CAI_DTLB, 0xb3, 4,128, 4 * 1024, NULL), \
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__CI_TBL(CAI_DTLB, 0xb4, 4,256, 4 * 1024, NULL), \
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__CI_TBL(CAI_ITLB, 0xb5, 8, 64, 4 * 1024, NULL), \
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__CI_TBL(CAI_ITLB, 0xb6, 8,128, 4 * 1024, NULL), \
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__CI_TBL(CAI_DTLB, 0xba, 4, 64, 4 * 1024, NULL), \
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__CI_TBL(CAI_DTLB, 0xc0, 4, 8, 4 * 1024, "4K/4M: 8 entries"), \
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__CI_TBL(CAI_L2_STLB2, 0xc1, 8,1024, 4 * 1024, "4K/2M: 1024 entries"), \
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__CI_TBL(CAI_DTLB, 0xc2, 4, 16, 4 * 1024, "2M/4M: 16 entries"), \
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__CI_TBL(CAI_L2_STLB, 0xca, 4,512, 4 * 1024, "4K/4M: 512 entries"), \
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__CI_TBL(CAI_ICACHE, 0x06, 4, 8 * 1024, 32, NULL), \
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__CI_TBL(CAI_ICACHE, 0x08, 4, 16 * 1024, 32, NULL), \
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__CI_TBL(CAI_ICACHE, 0x09, 4, 32 * 1024, 64, NULL), \
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__CI_TBL(CAI_DCACHE, 0x0a, 2, 8 * 1024, 32, NULL), \
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__CI_TBL(CAI_DCACHE, 0x0c, 4, 16 * 1024, 32, NULL), \
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__CI_TBL(CAI_DCACHE, 0x0d, 4, 16 * 1024, 64, NULL), \
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__CI_TBL(CAI_DCACHE, 0x0e, 6, 24 * 1024, 64, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x21, 8, 256 * 1024, 64, NULL), /* L2 (MLC) */ \
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__CI_TBL(CAI_L3CACHE, 0x22, 0xff, 512 * 1024, 64, "sectored, 4-way "), \
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__CI_TBL(CAI_L3CACHE, 0x23, 0xff, 1 * 1024 * 1024, 64, "sectored, 8-way "), \
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__CI_TBL(CAI_L2CACHE, 0x24, 16, 1 * 1024 * 1024, 64, NULL), \
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__CI_TBL(CAI_L3CACHE, 0x25, 0xff, 2 * 1024 * 1024, 64, "sectored, 8-way "), \
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__CI_TBL(CAI_L3CACHE, 0x29, 0xff, 4 * 1024 * 1024, 64, "sectored, 8-way "), \
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__CI_TBL(CAI_DCACHE, 0x2c, 8, 32 * 1024, 64, NULL), \
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__CI_TBL(CAI_ICACHE, 0x30, 8, 32 * 1024, 64, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x39, 4, 128 * 1024, 64, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x3a, 6, 192 * 1024, 64, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x3b, 2, 128 * 1024, 64, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x3c, 4, 256 * 1024, 64, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x3d, 6, 384 * 1024, 64, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x3e, 4, 512 * 1024, 64, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x40, 0, 0, 0, "not present"), \
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__CI_TBL(CAI_L2CACHE, 0x41, 4, 128 * 1024, 32, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x42, 4, 256 * 1024, 32, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x43, 4, 512 * 1024, 32, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x44, 4, 1 * 1024 * 1024, 32, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x45, 4, 2 * 1024 * 1024, 32, NULL), \
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__CI_TBL(CAI_L3CACHE, 0x46, 4, 4 * 1024 * 1024, 64, NULL), \
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__CI_TBL(CAI_L3CACHE, 0x47, 8, 8 * 1024 * 1024, 64, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x48, 12, 3 * 1024 * 1024, 64, NULL), \
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\
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/* 0x49 Is L2 on Xeon MP (Family 0f, Model 06), L3 otherwise */ \
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__CI_TBL(CAI_L2CACHE, 0x49, 16, 4 * 1024 * 1024, 64, NULL), \
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__CI_TBL(CAI_L3CACHE, 0x49, 16, 4 * 1024 * 1024, 64, NULL), \
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__CI_TBL(CAI_L3CACHE, 0x4a, 12, 6 * 1024 * 1024, 64, NULL), \
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__CI_TBL(CAI_L3CACHE, 0x4b, 16, 8 * 1024 * 1024, 64, NULL), \
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__CI_TBL(CAI_L3CACHE, 0x4c, 12,12 * 1024 * 1024, 64, NULL), \
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__CI_TBL(CAI_L3CACHE, 0x4d, 16,16 * 1024 * 1024, 64, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x4e, 24, 6 * 1024 * 1024, 64, NULL), \
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__CI_TBL(CAI_DCACHE, 0x60, 8, 16 * 1024, 64, NULL), \
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__CI_TBL(CAI_DCACHE, 0x66, 4, 8 * 1024, 64, NULL), \
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__CI_TBL(CAI_DCACHE, 0x67, 4, 16 * 1024, 64, NULL), \
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__CI_TBL(CAI_DCACHE, 0x68, 4, 32 * 1024, 64, NULL), \
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__CI_TBL(CAI_ICACHE, 0x70, 8, 12 * 1024, 64, "12K uOp cache"), \
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__CI_TBL(CAI_ICACHE, 0x71, 8, 16 * 1024, 64, "16K uOp cache"), \
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__CI_TBL(CAI_ICACHE, 0x72, 8, 32 * 1024, 64, "32K uOp cache"), \
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__CI_TBL(CAI_ICACHE, 0x73, 8, 64 * 1024, 64, "64K uOp cache"), \
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__CI_TBL(CAI_L2CACHE, 0x78, 4, 1 * 1024 * 1024, 64, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x79, 8, 128 * 1024, 64, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x7a, 8, 256 * 1024, 64, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x7b, 8, 512 * 1024, 64, NULL), \
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__CI_TBL(CAI_L2CACHE, 0x7c, 8, 1 * 1024 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L2CACHE, 0x7d, 8, 2 * 1024 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L2CACHE, 0x7f, 2, 512 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L2CACHE, 0x80, 8, 512 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L2CACHE, 0x82, 8, 256 * 1024, 32, NULL), \
|
|
__CI_TBL(CAI_L2CACHE, 0x83, 8, 512 * 1024, 32, NULL), \
|
|
__CI_TBL(CAI_L2CACHE, 0x84, 8, 1 * 1024 * 1024, 32, NULL), \
|
|
__CI_TBL(CAI_L2CACHE, 0x85, 8, 2 * 1024 * 1024, 32, NULL), \
|
|
__CI_TBL(CAI_L2CACHE, 0x86, 4, 512 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L2CACHE, 0x87, 8, 1 * 1024 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L3CACHE, 0xd0, 4, 512 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L3CACHE, 0xd1, 4, 1 * 1024 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L3CACHE, 0xd2, 4, 2 * 1024 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L3CACHE, 0xd6, 8, 1 * 1024 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L3CACHE, 0xd7, 8, 2 * 1024 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L3CACHE, 0xd8, 8, 4 * 1024 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L3CACHE, 0xdc, 12, 3 * 512 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L3CACHE, 0xdd, 12, 3 * 1024 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L3CACHE, 0xde, 12, 6 * 1024 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L3CACHE, 0xe2, 16, 2 * 1024 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L3CACHE, 0xe3, 16, 4 * 1024 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L3CACHE, 0xe4, 16, 8 * 1024 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L3CACHE, 0xea, 24,12 * 1024 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L3CACHE, 0xeb, 24,18 * 1024 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_L3CACHE, 0xec, 24,24 * 1024 * 1024, 64, NULL), \
|
|
__CI_TBL(CAI_PREFETCH, 0xf0, 0, 0, 64, NULL), \
|
|
__CI_TBL(CAI_PREFETCH, 0xf1, 0, 0,128, NULL), \
|
|
/* 0xff means no cache information in CPUID leaf 2 (and use leaf 4) */ \
|
|
__CI_TBL(0, 0, 0, 0, 0, NULL) \
|
|
}
|
|
|
|
#define AMD_L2CACHE_INFO { \
|
|
__CI_TBL(0, 0x01, 1, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x02, 2, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x04, 4, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x06, 8, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x08, 16, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x0a, 32, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x0b, 48, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x0c, 64, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x0d, 96, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x0e, 128, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x0f, 0xff, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x00, 0, 0, 0, NULL) \
|
|
}
|
|
|
|
#define AMD_L3CACHE_INFO { \
|
|
__CI_TBL(0, 0x01, 1, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x02, 2, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x04, 4, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x06, 8, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x08, 16, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x0a, 32, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x0b, 48, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x0c, 64, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x0d, 96, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x0e, 128, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x0f, 0xff, 0, 0, NULL), \
|
|
__CI_TBL(0, 0x00, 0, 0, 0, NULL) \
|
|
}
|
|
|
|
#endif /* _X86_CACHEINFO_H_ */
|