1004 lines
29 KiB
C
1004 lines
29 KiB
C
/*
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* lance.c
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*
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* This file contains a ethernet device driver for AMD LANCE based ethernet
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* cards.
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*
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* Created: Jul 27, 2002 by Kazuya Kodama <kazuya@nii.ac.jp>
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* Adapted for Minix 3: Sep 05, 2005 by Joren l'Ami <jwlami@cs.vu.nl>
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*/
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#define VERBOSE 0 /* Verbose debugging output */
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#define LANCE_FKEY 0 /* Use function key to dump Lance stats */
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#include <minix/drivers.h>
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#include <minix/netdriver.h>
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#include <net/hton.h>
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#include <net/gen/ether.h>
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#include <net/gen/eth_io.h>
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#include <assert.h>
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#include <minix/syslib.h>
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#include <minix/endpoint.h>
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#include <machine/pci.h>
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#include <minix/ds.h>
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#include "lance.h"
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static int do_init(unsigned int instance, ether_addr_t *addr);
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static void ec_confaddr(ether_addr_t *addr);
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static void ec_reinit(ether_card_t *ec);
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static void ec_reset(ether_card_t *ec);
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static void do_intr(unsigned int mask);
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static void do_mode(unsigned int mode);
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static int do_send(struct netdriver_data *data, size_t size);
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static ssize_t do_recv(struct netdriver_data *data, size_t max);
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static void do_stat(eth_stat_t *stat);
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static void do_stop(void);
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static void lance_dump(void);
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static void do_other(const message *m_ptr, int ipc_status);
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static void get_addressing(int devind, ether_card_t *ec);
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static int lance_probe(ether_card_t *ec, unsigned int skip);
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static void lance_init_hw(ether_card_t *ec, ether_addr_t *addr);
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/* Accesses Lance Control and Status Registers */
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static u8_t in_byte(port_t port);
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static u16_t in_word(port_t port);
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static void out_word(port_t port, u16_t value);
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static u16_t read_csr(port_t ioaddr, u16_t csrno);
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static void write_csr(port_t ioaddr, u16_t csrno, u16_t value);
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static ether_card_t ec_state;
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static int ec_instance;
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/* --- LANCE --- */
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/* General */
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typedef uint32_t Address;
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#define ETH_FRAME_LEN 1518
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#define LANCE_MUST_PAD 0x00000001
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#define LANCE_ENABLE_AUTOSELECT 0x00000002
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#define LANCE_SELECT_PHONELINE 0x00000004
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#define LANCE_MUST_UNRESET 0x00000008
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static const struct lance_chip_type
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{
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int id_number;
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const char *name;
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int flags;
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} chip_table[] = {
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{0x0000, "LANCE 7990", /* Ancient lance chip. */
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LANCE_MUST_PAD + LANCE_MUST_UNRESET},
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{0x0003, "PCnet/ISA 79C960", /* 79C960 PCnet/ISA. */
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LANCE_ENABLE_AUTOSELECT},
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{0x2260, "PCnet/ISA+ 79C961", /* 79C961 PCnet/ISA+, Plug-n-Play. */
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LANCE_ENABLE_AUTOSELECT},
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{0x2420, "PCnet/PCI 79C970", /* 79C970 or 79C974 PCnet-SCSI, PCI. */
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LANCE_ENABLE_AUTOSELECT},
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{0x2430, "PCnet32", /* 79C965 PCnet for VL bus. */
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LANCE_ENABLE_AUTOSELECT},
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{0x2621, "PCnet/PCI-II 79C970A", /* 79C970A PCInetPCI II. */
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LANCE_ENABLE_AUTOSELECT},
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{0x2625, "PCnet-FAST III 79C973",/* 79C973 PCInet-FAST III. */
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LANCE_ENABLE_AUTOSELECT},
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{0x2626, "PCnet/HomePNA 79C978",
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LANCE_ENABLE_AUTOSELECT|LANCE_SELECT_PHONELINE},
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{0x0, "PCnet (unknown)",
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LANCE_ENABLE_AUTOSELECT},
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};
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/* ############## for LANCE device ############## */
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#define LANCE_ETH_ADDR 0x0
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#define LANCE_DATA 0x10
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#define LANCE_ADDR 0x12
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#define LANCE_RESET 0x14
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#define LANCE_BUS_IF 0x16
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#define LANCE_TOTAL_SIZE 0x18
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/* Use 2^4=16 {Rx,Tx} buffers */
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#define LANCE_LOG_RX_BUFFERS 4
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#define RX_RING_SIZE (1 << (LANCE_LOG_RX_BUFFERS))
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#define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
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#define RX_RING_LEN_BITS ((LANCE_LOG_RX_BUFFERS) << 29)
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#define LANCE_LOG_TX_BUFFERS 4
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#define TX_RING_SIZE (1 << (LANCE_LOG_TX_BUFFERS))
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#define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
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#define TX_RING_LEN_BITS ((LANCE_LOG_TX_BUFFERS) << 29)
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/* for lance_interface */
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struct lance_init_block
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{
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unsigned short mode;
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unsigned char phys_addr[6];
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unsigned long filter[2];
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Address rx_ring;
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Address tx_ring;
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};
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struct lance_rx_head
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{
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union {
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Address base;
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unsigned char addr[4];
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} u;
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short buf_length; /* 2s complement */
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short msg_length;
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};
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struct lance_tx_head
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{
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union {
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Address base;
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unsigned char addr[4];
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} u;
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short buf_length; /* 2s complement */
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short misc;
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};
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struct lance_interface
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{
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struct lance_init_block init_block;
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struct lance_rx_head rx_ring[RX_RING_SIZE];
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struct lance_tx_head tx_ring[TX_RING_SIZE];
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unsigned char rbuf[RX_RING_SIZE][ETH_FRAME_LEN];
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unsigned char tbuf[TX_RING_SIZE][ETH_FRAME_LEN];
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};
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/* =============== global variables =============== */
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/* AKA the stuff that really should have been in ether_card_t */
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static struct lance_interface *lp;
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#define LANCE_BUF_SIZE (sizeof(struct lance_interface))
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static char *lance_buf = NULL;
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static int rx_slot_nr = 0; /* Rx-slot number */
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static int tx_slot_nr = 0; /* Tx-slot number */
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static int cur_tx_slot_nr = 0; /* Tx-slot number */
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static phys_bytes tx_ring_base[TX_RING_SIZE]; /* Tx-slot physical address */
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static char isstored[TX_RING_SIZE]; /* Tx-slot in-use */
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static const struct netdriver lance_table = {
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.ndr_init = do_init,
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.ndr_stop = do_stop,
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.ndr_mode = do_mode,
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.ndr_recv = do_recv,
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.ndr_send = do_send,
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.ndr_stat = do_stat,
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.ndr_intr = do_intr,
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.ndr_other = do_other,
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};
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/*===========================================================================*
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* main *
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*===========================================================================*/
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int main(int argc, char **argv)
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{
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env_setargs(argc, argv);
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netdriver_task(&lance_table);
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return 0;
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}
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/*===========================================================================*
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* lance_dump *
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*===========================================================================*/
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static void lance_dump()
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{
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ether_card_t *ec;
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int isr, csr;
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unsigned short ioaddr;
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printf("\n");
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ec = &ec_state;
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printf("lance statistics of instance %d:\n", ec_instance);
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printf("recvErr :%8ld\t", ec->eth_stat.ets_recvErr);
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printf("sendErr :%8ld\t", ec->eth_stat.ets_sendErr);
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printf("OVW :%8ld\n", ec->eth_stat.ets_OVW);
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printf("CRCerr :%8ld\t", ec->eth_stat.ets_CRCerr);
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printf("frameAll :%8ld\t", ec->eth_stat.ets_frameAll);
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printf("missedP :%8ld\n", ec->eth_stat.ets_missedP);
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printf("packetR :%8ld\t", ec->eth_stat.ets_packetR);
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printf("packetT :%8ld\t", ec->eth_stat.ets_packetT);
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printf("transDef :%8ld\n", ec->eth_stat.ets_transDef);
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printf("collision :%8ld\t", ec->eth_stat.ets_collision);
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printf("transAb :%8ld\t", ec->eth_stat.ets_transAb);
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printf("carrSense :%8ld\n", ec->eth_stat.ets_carrSense);
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printf("fifoUnder :%8ld\t", ec->eth_stat.ets_fifoUnder);
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printf("fifoOver :%8ld\t", ec->eth_stat.ets_fifoOver);
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printf("CDheartbeat:%8ld\n", ec->eth_stat.ets_CDheartbeat);
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printf("OWC :%8ld\t", ec->eth_stat.ets_OWC);
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ioaddr = ec->ec_port;
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isr = read_csr(ioaddr, LANCE_CSR0);
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printf("isr = 0x%x, flags = 0x%x\n", isr,
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ec->flags);
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printf("irq = %d\tioadr = 0x%x\n", ec->ec_irq, ec->ec_port);
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csr = read_csr(ioaddr, LANCE_CSR0);
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printf("CSR0: 0x%x\n", csr);
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csr = read_csr(ioaddr, LANCE_CSR3);
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printf("CSR3: 0x%x\n", csr);
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csr = read_csr(ioaddr, LANCE_CSR4);
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printf("CSR4: 0x%x\n", csr);
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csr = read_csr(ioaddr, LANCE_CSR5);
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printf("CSR5: 0x%x\n", csr);
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csr = read_csr(ioaddr, LANCE_CSR15);
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printf("CSR15: 0x%x\n", csr);
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}
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/*===========================================================================*
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* do_other *
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*===========================================================================*/
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static void do_other(const message *m_ptr, int ipc_status)
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{
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if (is_ipc_notify(ipc_status) && m_ptr->m_source == TTY_PROC_NR)
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lance_dump();
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}
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/*===========================================================================*
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* ec_confaddr *
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*===========================================================================*/
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static void ec_confaddr(ether_addr_t *addr)
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{
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int i;
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char eakey[16];
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static char eafmt[]= "x:x:x:x:x:x";
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long v;
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/* User defined ethernet address? */
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strlcpy(eakey, "LANCE0_EA", sizeof(eakey));
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eakey[5] += ec_instance;
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for (i = 0; i < 6; i++)
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{
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v= addr->ea_addr[i];
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if (env_parse(eakey, eafmt, i, &v, 0x00L, 0xFFL) != EP_SET)
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break;
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addr->ea_addr[i]= v;
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}
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if (i != 0 && i != 6)
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{
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/* It's all or nothing; force a panic. */
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panic("invalid ethernet address supplied");
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}
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}
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/*===========================================================================*
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* do_init *
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*===========================================================================*/
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static int do_init(unsigned int instance, ether_addr_t *addr)
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{
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/* Initialize the lance driver. */
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ether_card_t *ec;
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#if VERBOSE
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int i, r;
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#endif
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#if LANCE_FKEY
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int fkeys, sfkeys;
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#endif
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#if LANCE_FKEY
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fkeys = sfkeys = 0;
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bit_set( sfkeys, 7 );
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if ( (r = fkey_map(&fkeys, &sfkeys)) != OK )
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printf("Warning: lance couldn't observe Shift+F7 key: %d\n",r);
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#endif
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ec_instance = instance;
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/* Initialize the driver state. */
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ec= &ec_state;
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memset(ec, 0, sizeof(*ec));
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strlcpy(ec->port_name, "lance#0", sizeof(ec->port_name));
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ec->port_name[6] += instance;
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/* See if there is a matching card. */
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if (!lance_probe(ec, instance))
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return ENXIO;
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/* Initialize the hardware. */
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lance_init_hw(ec, addr);
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#if VERBOSE
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printf("%s: Ethernet address ", ec->port_name);
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for (i= 0; i < 6; i++)
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printf("%x%c", addr->ea_addr[i], i < 5 ? ':' : '\n');
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#endif
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return OK;
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}
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/*===========================================================================*
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* ec_reinit *
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*===========================================================================*/
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static void ec_reinit(ether_card_t *ec)
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{
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int i;
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unsigned short ioaddr = ec->ec_port;
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/* stop */
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write_csr(ioaddr, LANCE_CSR0, LANCE_CSR0_STOP);
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/* purge Tx-ring */
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tx_slot_nr = cur_tx_slot_nr = 0;
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for (i=0; i<TX_RING_SIZE; i++)
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{
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lp->tx_ring[i].u.base = 0;
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isstored[i]=0;
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}
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/* re-init Rx-ring */
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rx_slot_nr = 0;
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for (i=0; i<RX_RING_SIZE; i++)
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{
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lp->rx_ring[i].buf_length = -ETH_FRAME_LEN;
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lp->rx_ring[i].u.addr[3] |= 0x80;
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}
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/* Set 'Receive Mode' */
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if (ec->flags & ECF_PROMISC)
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{
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write_csr(ioaddr, LANCE_CSR15, LANCE_CSR15_PROM);
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}
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else
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{
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if (ec->flags & (ECF_BROAD | ECF_MULTI))
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{
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write_csr(ioaddr, LANCE_CSR15, 0x0000);
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}
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else
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{
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write_csr(ioaddr, LANCE_CSR15, LANCE_CSR15_DRCVBC);
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}
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}
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/* start && enable interrupt */
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write_csr(ioaddr, LANCE_CSR0,
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LANCE_CSR0_IDON|LANCE_CSR0_IENA|LANCE_CSR0_STRT);
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return;
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}
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/*===========================================================================*
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* do_mode *
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*===========================================================================*/
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static void do_mode(unsigned int mode)
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{
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ether_card_t *ec;
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ec = &ec_state;
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ec->flags &= ~(ECF_PROMISC | ECF_MULTI | ECF_BROAD);
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if (mode & NDEV_PROMISC)
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ec->flags |= ECF_PROMISC | ECF_MULTI | ECF_BROAD;
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if (mode & NDEV_MULTI)
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ec->flags |= ECF_MULTI;
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if (mode & NDEV_BROAD)
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ec->flags |= ECF_BROAD;
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ec_reinit(ec);
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}
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/*===========================================================================*
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* do_intr *
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*===========================================================================*/
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static void do_intr(unsigned int __unused mask)
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{
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ether_card_t *ec;
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int must_restart = 0;
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int r, check, status;
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int isr = 0x0000;
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unsigned short ioaddr;
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ec = &ec_state;
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ioaddr = ec->ec_port;
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for (;;)
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{
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#if VERBOSE
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printf("ETH: Reading ISR...");
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#endif
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isr = read_csr(ioaddr, LANCE_CSR0);
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if (isr & (LANCE_CSR0_ERR|LANCE_CSR0_RINT|LANCE_CSR0_TINT)) {
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write_csr(ioaddr, LANCE_CSR0,
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isr & ~(LANCE_CSR0_IENA|LANCE_CSR0_TDMD|LANCE_CSR0_STOP
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|LANCE_CSR0_STRT|LANCE_CSR0_INIT) );
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}
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write_csr(ioaddr, LANCE_CSR0,
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LANCE_CSR0_BABL|LANCE_CSR0_CERR|LANCE_CSR0_MISS|LANCE_CSR0_MERR
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|LANCE_CSR0_IDON|LANCE_CSR0_IENA);
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if ((isr & (LANCE_CSR0_TINT|LANCE_CSR0_RINT|LANCE_CSR0_MISS
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|LANCE_CSR0_BABL|LANCE_CSR0_ERR)) == 0x0000)
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{
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#if VERBOSE
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printf("OK\n");
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#endif
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break;
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}
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if (isr & LANCE_CSR0_MISS)
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{
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#if VERBOSE
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printf("RX Missed Frame\n");
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#endif
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ec->eth_stat.ets_recvErr++;
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}
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if ((isr & LANCE_CSR0_BABL) || (isr & LANCE_CSR0_TINT))
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{
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if (isr & LANCE_CSR0_BABL)
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{
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#if VERBOSE
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printf("TX Timeout\n");
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#endif
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ec->eth_stat.ets_sendErr++;
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}
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if (isr & LANCE_CSR0_TINT)
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{
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#if VERBOSE
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printf("TX INT\n");
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#endif
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/* status check: restart if needed. */
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status = lp->tx_ring[cur_tx_slot_nr].u.base;
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/* did an error (UFLO, LCOL, LCAR, RTRY) occur? */
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if (status & 0x40000000)
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{
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status = lp->tx_ring[cur_tx_slot_nr].misc;
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ec->eth_stat.ets_sendErr++;
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if (status & 0x0400) /* RTRY */
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ec->eth_stat.ets_transAb++;
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if (status & 0x0800) /* LCAR */
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ec->eth_stat.ets_carrSense++;
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if (status & 0x1000) /* LCOL */
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ec->eth_stat.ets_OWC++;
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if (status & 0x4000) /* UFLO */
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{
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ec->eth_stat.ets_fifoUnder++;
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must_restart=1;
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}
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}
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else
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{
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if (status & 0x18000000)
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ec->eth_stat.ets_collision++;
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ec->eth_stat.ets_packetT++;
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}
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}
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/* transmit a packet on the next slot if it exists. */
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check = 0;
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if (isstored[cur_tx_slot_nr]==1)
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{
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/* free the tx-slot just transmitted */
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isstored[cur_tx_slot_nr]=0;
|
|
cur_tx_slot_nr = (cur_tx_slot_nr + 1) & TX_RING_MOD_MASK;
|
|
|
|
/* next tx-slot is ready? */
|
|
if (isstored[cur_tx_slot_nr]==1)
|
|
check=1;
|
|
else
|
|
check=0;
|
|
}
|
|
else
|
|
{
|
|
panic("got premature TX INT..");
|
|
}
|
|
if (check==1)
|
|
{
|
|
lp->tx_ring[cur_tx_slot_nr].u.addr[3] = 0x83;
|
|
write_csr(ioaddr, LANCE_CSR0, LANCE_CSR0_IENA|LANCE_CSR0_TDMD);
|
|
}
|
|
/* we set a buffered message in the slot if it exists. */
|
|
/* and transmit it, if needed. */
|
|
if (!must_restart)
|
|
netdriver_send();
|
|
}
|
|
if (isr & LANCE_CSR0_RINT)
|
|
{
|
|
#if VERBOSE
|
|
printf("RX INT\n");
|
|
#endif
|
|
netdriver_recv();
|
|
}
|
|
|
|
if (must_restart == 1)
|
|
{
|
|
#if VERBOSE
|
|
printf("ETH: restarting...\n");
|
|
#endif
|
|
|
|
ec_reset(ec);
|
|
}
|
|
}
|
|
|
|
/* reenable interrupts */
|
|
if ((r = sys_irqenable(&ec->ec_hook)) != OK)
|
|
panic("couldn't enable interrupt: %d", r);
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* ec_reset *
|
|
*===========================================================================*/
|
|
static void ec_reset(ether_card_t *ec)
|
|
{
|
|
/* Stop/start the chip, and clear all RX,TX-slots. The spec says this type
|
|
* of reset should be done on MERR, UFLO, and TX BUFF errors. For now it is
|
|
* called only for UFLO and TX BUFF (which causes UFLO). MERR is not (yet?)
|
|
* handled. Also note that the PCnet spec says that the LANCE chip does not
|
|
* require resetting Rx/Tx, but PCnet does. We intend to support both here.
|
|
*/
|
|
unsigned short ioaddr = ec->ec_port;
|
|
int i;
|
|
|
|
/* stop */
|
|
write_csr(ioaddr, LANCE_CSR0, LANCE_CSR0_STOP);
|
|
/* start */
|
|
write_csr(ioaddr, LANCE_CSR0, LANCE_CSR0_STRT);
|
|
|
|
/* purge Tx-ring */
|
|
tx_slot_nr = cur_tx_slot_nr = 0;
|
|
for (i=0; i<TX_RING_SIZE; i++)
|
|
{
|
|
lp->tx_ring[i].u.base = 0;
|
|
isstored[i]=0;
|
|
}
|
|
|
|
/* re-init Rx-ring */
|
|
rx_slot_nr = 0;
|
|
for (i=0; i<RX_RING_SIZE; i++)
|
|
{
|
|
lp->rx_ring[i].buf_length = -ETH_FRAME_LEN;
|
|
lp->rx_ring[i].u.addr[3] |= 0x80;
|
|
}
|
|
|
|
/* store a buffered message on the slot if it exists */
|
|
netdriver_send();
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* do_recv *
|
|
*===========================================================================*/
|
|
static ssize_t do_recv(struct netdriver_data *data, size_t max)
|
|
{
|
|
ether_card_t *ec;
|
|
vir_bytes length;
|
|
int packet_processed;
|
|
int status;
|
|
unsigned short ioaddr;
|
|
|
|
ec = &ec_state;
|
|
ioaddr = ec->ec_port;
|
|
|
|
/* we check all the received slots until find a properly received packet */
|
|
packet_processed = FALSE;
|
|
while (!packet_processed)
|
|
{
|
|
status = lp->rx_ring[rx_slot_nr].u.base >> 24;
|
|
|
|
/* is the slot marked as ready? */
|
|
if ( (status & 0x80) != 0x00 )
|
|
return SUSPEND; /* no */
|
|
|
|
/* did an error occur? */
|
|
if (status != 0x03)
|
|
{
|
|
if (status & 0x01)
|
|
ec->eth_stat.ets_recvErr++;
|
|
if (status & 0x04)
|
|
ec->eth_stat.ets_fifoOver++;
|
|
if (status & 0x08)
|
|
ec->eth_stat.ets_CRCerr++;
|
|
if (status & 0x10)
|
|
ec->eth_stat.ets_OVW++;
|
|
if (status & 0x20)
|
|
ec->eth_stat.ets_frameAll++;
|
|
length = 0;
|
|
}
|
|
else
|
|
{
|
|
ec->eth_stat.ets_packetR++;
|
|
length = lp->rx_ring[rx_slot_nr].msg_length;
|
|
}
|
|
|
|
/* do we now have a valid packet? */
|
|
if (length > 0)
|
|
{
|
|
if (length > max)
|
|
length = max;
|
|
netdriver_copyout(data, 0, lp->rbuf[rx_slot_nr], length);
|
|
packet_processed = TRUE;
|
|
}
|
|
|
|
/* set up this slot again, and we move to the next slot */
|
|
lp->rx_ring[rx_slot_nr].buf_length = -ETH_FRAME_LEN;
|
|
lp->rx_ring[rx_slot_nr].u.addr[3] |= 0x80;
|
|
|
|
write_csr(ioaddr, LANCE_CSR0,
|
|
LANCE_CSR0_BABL|LANCE_CSR0_CERR|LANCE_CSR0_MISS
|
|
|LANCE_CSR0_MERR|LANCE_CSR0_IDON|LANCE_CSR0_IENA);
|
|
|
|
rx_slot_nr = (rx_slot_nr + 1) & RX_RING_MOD_MASK;
|
|
}
|
|
|
|
/* return the length of the packet we have received */
|
|
return length;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* do_send *
|
|
*===========================================================================*/
|
|
static int do_send(struct netdriver_data *data, size_t size)
|
|
{
|
|
int check;
|
|
ether_card_t *ec;
|
|
unsigned short ioaddr;
|
|
|
|
ec = &ec_state;
|
|
|
|
/* if all slots are used, this request must be deferred */
|
|
if (isstored[tx_slot_nr]==1)
|
|
return SUSPEND;
|
|
|
|
/* copy the packet to the slot on DMA address */
|
|
netdriver_copyin(data, 0, lp->tbuf[tx_slot_nr], size);
|
|
|
|
/* set-up for transmitting, and transmit it if needed. */
|
|
lp->tx_ring[tx_slot_nr].buf_length = -size;
|
|
lp->tx_ring[tx_slot_nr].misc = 0x0;
|
|
lp->tx_ring[tx_slot_nr].u.base = tx_ring_base[tx_slot_nr];
|
|
isstored[tx_slot_nr]=1;
|
|
if (cur_tx_slot_nr == tx_slot_nr)
|
|
check=1;
|
|
else
|
|
check=0;
|
|
tx_slot_nr = (tx_slot_nr + 1) & TX_RING_MOD_MASK;
|
|
|
|
if (check == 1)
|
|
{
|
|
ioaddr = ec->ec_port;
|
|
lp->tx_ring[cur_tx_slot_nr].u.addr[3] = 0x83;
|
|
write_csr(ioaddr, LANCE_CSR0, LANCE_CSR0_IENA|LANCE_CSR0_TDMD);
|
|
}
|
|
|
|
return OK;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* do_stat *
|
|
*===========================================================================*/
|
|
static void do_stat(eth_stat_t *stat)
|
|
{
|
|
|
|
memcpy(stat, &ec_state.eth_stat, sizeof(*stat));
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* do_stop *
|
|
*===========================================================================*/
|
|
static void do_stop(void)
|
|
{
|
|
ether_card_t *ec;
|
|
unsigned short ioaddr;
|
|
|
|
ec = &ec_state;
|
|
|
|
ioaddr = ec->ec_port;
|
|
|
|
/* stop */
|
|
write_csr(ioaddr, LANCE_CSR0, LANCE_CSR0_STOP);
|
|
|
|
/* Reset */
|
|
in_word(ioaddr+LANCE_RESET);
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* get_addressing *
|
|
*===========================================================================*/
|
|
static void get_addressing(int devind, ether_card_t *ec)
|
|
{
|
|
unsigned int ioaddr;
|
|
int reg, irq;
|
|
|
|
for (reg = PCI_BAR; reg <= PCI_BAR_6; reg += 4)
|
|
{
|
|
ioaddr = pci_attr_r32(devind, reg);
|
|
|
|
if ((ioaddr & PCI_BAR_IO_MASK) == 0 || (ioaddr & PCI_BAR_IO) == 0)
|
|
continue;
|
|
/* Strip the I/O address out of the returned value */
|
|
ioaddr &= PCI_BAR_IO_MASK;
|
|
ec->ec_port = ioaddr;
|
|
}
|
|
|
|
/* KK: Get the IRQ number */
|
|
irq = pci_attr_r8(devind, PCI_IPR);
|
|
if (irq)
|
|
irq = pci_attr_r8(devind, PCI_ILR);
|
|
ec->ec_irq = irq;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* lance_probe *
|
|
*===========================================================================*/
|
|
static int lance_probe(ether_card_t *ec, unsigned int skip)
|
|
{
|
|
unsigned short pci_cmd;
|
|
unsigned short ioaddr;
|
|
int lance_version, chip_version;
|
|
int devind, r;
|
|
u16_t vid, did;
|
|
|
|
pci_init();
|
|
|
|
r= pci_first_dev(&devind, &vid, &did);
|
|
if (r == 0)
|
|
return 0;
|
|
|
|
while (skip--)
|
|
{
|
|
r= pci_next_dev(&devind, &vid, &did);
|
|
if (!r)
|
|
return 0;
|
|
}
|
|
|
|
pci_reserve(devind);
|
|
|
|
get_addressing(devind, ec);
|
|
|
|
/* ===== Bus Master ? ===== */
|
|
pci_cmd = pci_attr_r32(devind, PCI_CR);
|
|
if (!(pci_cmd & PCI_CR_MAST_EN)) {
|
|
pci_cmd |= PCI_CR_MAST_EN;
|
|
pci_attr_w32(devind, PCI_CR, pci_cmd);
|
|
}
|
|
|
|
/* ===== Probe Details ===== */
|
|
ioaddr = ec->ec_port;
|
|
|
|
/* Reset */
|
|
in_word(ioaddr+LANCE_RESET);
|
|
|
|
if (read_csr(ioaddr, LANCE_CSR0) != LANCE_CSR0_STOP)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
/* Probe Chip Version */
|
|
out_word(ioaddr+LANCE_ADDR, 88); /* Get the version of the chip */
|
|
if (in_word(ioaddr+LANCE_ADDR) != 88)
|
|
lance_version = 0;
|
|
else
|
|
{
|
|
chip_version = read_csr(ioaddr, LANCE_CSR88);
|
|
chip_version |= read_csr(ioaddr, LANCE_CSR89) << 16;
|
|
|
|
if ((chip_version & 0xfff) != 0x3)
|
|
{
|
|
return 0;
|
|
}
|
|
chip_version = (chip_version >> 12) & 0xffff;
|
|
for (lance_version = 1; chip_table[lance_version].id_number != 0;
|
|
++lance_version)
|
|
if (chip_table[lance_version].id_number == chip_version)
|
|
break;
|
|
}
|
|
|
|
#if VERBOSE
|
|
printf("%s: %s at %X:%d\n",
|
|
ec->port_name, chip_table[lance_version].name,
|
|
ec->ec_port, ec->ec_irq);
|
|
#endif
|
|
|
|
return lance_version;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* virt_to_bus *
|
|
*===========================================================================*/
|
|
static phys_bytes virt_to_bus(void *ptr)
|
|
{
|
|
phys_bytes value;
|
|
int r;
|
|
|
|
if ((r = sys_umap(SELF, VM_D, (vir_bytes)ptr, 4, &value)) != OK)
|
|
panic("sys_umap failed: %d", r);
|
|
|
|
return value;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* lance_init_hw *
|
|
*===========================================================================*/
|
|
static void lance_init_hw(ether_card_t *ec, ether_addr_t *addr)
|
|
{
|
|
phys_bytes lance_buf_phys;
|
|
int i, r;
|
|
Address l;
|
|
unsigned short ioaddr = ec->ec_port;
|
|
|
|
/* ============= setup init_block(cf. lance_probe1) ================ */
|
|
/* make sure data structure is 8-byte aligned and below 16MB (for DMA) */
|
|
|
|
/* Allocate memory */
|
|
if ((lance_buf = alloc_contig(LANCE_BUF_SIZE, AC_ALIGN4K|AC_LOWER16M,
|
|
&lance_buf_phys)) == NULL)
|
|
panic("alloc_contig failed: %d", LANCE_BUF_SIZE);
|
|
|
|
l = (vir_bytes)lance_buf;
|
|
lp = (struct lance_interface *)l;
|
|
|
|
/* disable Tx and Rx */
|
|
lp->init_block.mode = LANCE_CSR15_DTX|LANCE_CSR15_DRX;
|
|
lp->init_block.filter[0] = lp->init_block.filter[1] = 0x0;
|
|
/* using multiple Rx/Tx buffer */
|
|
lp->init_block.rx_ring
|
|
= (virt_to_bus(&lp->rx_ring) & 0xffffff) | RX_RING_LEN_BITS;
|
|
lp->init_block.tx_ring
|
|
= (virt_to_bus(&lp->tx_ring) & 0xffffff) | TX_RING_LEN_BITS;
|
|
|
|
l = virt_to_bus(&lp->init_block);
|
|
write_csr(ioaddr, LANCE_CSR1, (unsigned short)l);
|
|
write_csr(ioaddr, LANCE_CSR2, (unsigned short)(l >> 16));
|
|
write_csr(ioaddr, LANCE_CSR4,
|
|
LANCE_CSR4_APAD_XMT|LANCE_CSR4_MFCOM|LANCE_CSR4_RCVCCOM
|
|
|LANCE_CSR4_TXSTRTM|LANCE_CSR4_JABM);
|
|
|
|
/* ============= Get MAC address (cf. lance_probe1) ================ */
|
|
for (i = 0; i < 6; ++i)
|
|
addr->ea_addr[i]=in_byte(ioaddr+LANCE_ETH_ADDR+i);
|
|
|
|
/* Allow the user to override the hardware address. */
|
|
ec_confaddr(addr);
|
|
|
|
/* ============ (re)start init_block(cf. lance_reset) =============== */
|
|
/* Reset the LANCE */
|
|
(void)in_word(ioaddr+LANCE_RESET);
|
|
|
|
/* ----- Re-initialize the LANCE ----- */
|
|
/* Set station address */
|
|
for (i = 0; i < 6; ++i)
|
|
lp->init_block.phys_addr[i] = addr->ea_addr[i];
|
|
/* Preset the receive ring headers */
|
|
for (i=0; i<RX_RING_SIZE; i++)
|
|
{
|
|
lp->rx_ring[i].buf_length = -ETH_FRAME_LEN;
|
|
/* OWN */
|
|
lp->rx_ring[i].u.base = virt_to_bus(lp->rbuf[i]) & 0xffffff;
|
|
/* we set the top byte as the very last thing */
|
|
lp->rx_ring[i].u.addr[3] = 0x80;
|
|
}
|
|
/* Preset the transmitting ring headers */
|
|
for (i=0; i<TX_RING_SIZE; i++)
|
|
{
|
|
lp->tx_ring[i].u.base = 0;
|
|
tx_ring_base[i] = virt_to_bus(lp->tbuf[i]) & 0xffffff;
|
|
isstored[i] = 0;
|
|
}
|
|
/* enable Rx and Tx */
|
|
lp->init_block.mode = 0x0;
|
|
|
|
l = (Address)virt_to_bus(&lp->init_block);
|
|
write_csr(ioaddr, LANCE_CSR1, (short)l);
|
|
write_csr(ioaddr, LANCE_CSR2, (short)(l >> 16));
|
|
write_csr(ioaddr, LANCE_CSR4,
|
|
LANCE_CSR4_APAD_XMT|LANCE_CSR4_MFCOM|LANCE_CSR4_RCVCCOM
|
|
|LANCE_CSR4_TXSTRTM|LANCE_CSR4_JABM);
|
|
|
|
/* ----- start when init done. ----- */
|
|
/* stop */
|
|
write_csr(ioaddr, LANCE_CSR0, LANCE_CSR0_STOP);
|
|
/* init */
|
|
write_csr(ioaddr, LANCE_CSR0, LANCE_CSR0_INIT);
|
|
/* poll for IDON */
|
|
for (i = 10000; i > 0; --i)
|
|
if (read_csr(ioaddr, LANCE_CSR0) & LANCE_CSR0_IDON)
|
|
break;
|
|
|
|
/* Set 'Multicast Table' */
|
|
for (i=0;i<4;++i)
|
|
{
|
|
write_csr(ioaddr, LANCE_CSR8 + i, 0xffff);
|
|
}
|
|
|
|
/* Set 'Receive Mode' */
|
|
if (ec->flags & ECF_PROMISC)
|
|
{
|
|
write_csr(ioaddr, LANCE_CSR15, LANCE_CSR15_PROM);
|
|
}
|
|
else
|
|
{
|
|
if (ec->flags & (ECF_BROAD | ECF_MULTI))
|
|
{
|
|
write_csr(ioaddr, LANCE_CSR15, 0x0000);
|
|
}
|
|
else
|
|
{
|
|
write_csr(ioaddr, LANCE_CSR15, LANCE_CSR15_DRCVBC);
|
|
}
|
|
}
|
|
|
|
/* Set the interrupt handler */
|
|
ec->ec_hook = ec->ec_irq;
|
|
if ((r=sys_irqsetpolicy(ec->ec_irq, 0, &ec->ec_hook)) != OK)
|
|
panic("couldn't set IRQ policy: %d", r);
|
|
if ((r = sys_irqenable(&ec->ec_hook)) != OK)
|
|
panic("couldn't enable interrupt: %d", r);
|
|
|
|
/* start && enable interrupt */
|
|
write_csr(ioaddr, LANCE_CSR0,
|
|
LANCE_CSR0_IDON|LANCE_CSR0_IENA|LANCE_CSR0_STRT);
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* in_byte *
|
|
*===========================================================================*/
|
|
static u8_t in_byte(port_t port)
|
|
{
|
|
int r;
|
|
u32_t value;
|
|
|
|
r= sys_inb(port, &value);
|
|
if (r != OK)
|
|
panic("sys_inb failed: %d", r);
|
|
return value;
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* in_word *
|
|
*===========================================================================*/
|
|
static u16_t in_word(port_t port)
|
|
{
|
|
int r;
|
|
u32_t value;
|
|
|
|
r= sys_inw(port, &value);
|
|
if (r != OK)
|
|
panic("sys_inw failed: %d", r);
|
|
return value;
|
|
}
|
|
|
|
|
|
/*===========================================================================*
|
|
* out_word *
|
|
*===========================================================================*/
|
|
static void out_word(port_t port, u16_t value)
|
|
{
|
|
int r;
|
|
|
|
r= sys_outw(port, value);
|
|
if (r != OK)
|
|
panic("sys_outw failed: %d", r);
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* read_csr *
|
|
*===========================================================================*/
|
|
static u16_t read_csr(port_t ioaddr, u16_t csrno)
|
|
{
|
|
out_word(ioaddr+LANCE_ADDR, csrno);
|
|
return in_word(ioaddr+LANCE_DATA);
|
|
}
|
|
|
|
/*===========================================================================*
|
|
* write_csr *
|
|
*===========================================================================*/
|
|
static void write_csr(port_t ioaddr, u16_t csrno, u16_t value)
|
|
{
|
|
out_word(ioaddr+LANCE_ADDR, csrno);
|
|
out_word(ioaddr+LANCE_DATA, value);
|
|
}
|