0a6a1f1d05
This brings our tree to NetBSD 7.0, as found on -current on the 10-10-2015. This updates: - LLVM to 3.6.1 - GCC to GCC 5.1 - Replace minix/commands/zdump with usr.bin/zdump - external/bsd/libelf has moved to /external/bsd/elftoolchain/ - Import ctwm - Drop sprintf from libminc Change-Id: I149836ac18e9326be9353958bab9b266efb056f0
231 lines
6.3 KiB
C
231 lines
6.3 KiB
C
/* $NetBSD: lock.h,v 1.32 2015/02/25 13:52:42 joerg Exp $ */
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/*-
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* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Machine-dependent spin lock operations.
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*
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* NOTE: The SWP insn used here is available only on ARM architecture
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* version 3 and later (as well as 2a). What we are going to do is
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* expect that the kernel will trap and emulate the insn. That will
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* be slow, but give us the atomicity that we need.
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*/
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#ifndef _ARM_LOCK_H_
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#define _ARM_LOCK_H_
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static __inline int
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__SIMPLELOCK_LOCKED_P(__cpu_simple_lock_t *__ptr)
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{
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return *__ptr == __SIMPLELOCK_LOCKED;
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}
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static __inline int
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__SIMPLELOCK_UNLOCKED_P(__cpu_simple_lock_t *__ptr)
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{
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return *__ptr == __SIMPLELOCK_UNLOCKED;
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}
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static __inline void
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__cpu_simple_lock_clear(__cpu_simple_lock_t *__ptr)
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{
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*__ptr = __SIMPLELOCK_UNLOCKED;
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}
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static __inline void
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__cpu_simple_lock_set(__cpu_simple_lock_t *__ptr)
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{
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*__ptr = __SIMPLELOCK_LOCKED;
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}
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#ifdef _KERNEL
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#include <arm/cpufunc.h>
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#define mb_read drain_writebuf /* in cpufunc.h */
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#define mb_write drain_writebuf /* in cpufunc.h */
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#define mb_memory drain_writebuf /* in cpufunc.h */
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#endif
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#ifdef _ARM_ARCH_6
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static __inline unsigned int
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__arm_load_exclusive(__cpu_simple_lock_t *__alp)
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{
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unsigned int __rv;
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if (/*CONSTCOND*/sizeof(*__alp) == 1) {
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__asm __volatile("ldrexb\t%0,[%1]" : "=r"(__rv) : "r"(__alp));
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} else {
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__asm __volatile("ldrex\t%0,[%1]" : "=r"(__rv) : "r"(__alp));
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}
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return __rv;
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}
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/* returns 0 on success and 1 on failure */
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static __inline unsigned int
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__arm_store_exclusive(__cpu_simple_lock_t *__alp, unsigned int __val)
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{
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unsigned int __rv;
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if (/*CONSTCOND*/sizeof(*__alp) == 1) {
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__asm __volatile("strexb\t%0,%1,[%2]"
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: "=&r"(__rv) : "r"(__val), "r"(__alp) : "cc", "memory");
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} else {
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__asm __volatile("strex\t%0,%1,[%2]"
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: "=&r"(__rv) : "r"(__val), "r"(__alp) : "cc", "memory");
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}
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return __rv;
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}
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#elif defined(_KERNEL)
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static __inline unsigned char
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__swp(unsigned char __val, __cpu_simple_lock_t *__ptr)
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{
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uint32_t __val32;
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__asm volatile("swpb %0, %1, [%2]"
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: "=&r" (__val32) : "r" (__val), "r" (__ptr) : "memory");
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return __val32;
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}
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#else
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/*
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* On MP Cortex, SWP no longer guarantees atomic results. Thus we pad
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* out SWP so that when the cpu generates an undefined exception we can replace
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* the SWP/MOV instructions with the right LDREX/STREX instructions.
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*
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* This is why we force the SWP into the template needed for LDREX/STREX
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* including the extra instructions and extra register for testing the result.
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*/
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static __inline int
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__swp(int __val, __cpu_simple_lock_t *__ptr)
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{
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int __tmp, __rv;
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__asm volatile(
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#if 1
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"1:\t" "swp %[__rv], %[__val], [%[__ptr]]"
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"\n\t" "b 2f"
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#else
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"1:\t" "ldrex %[__rv],[%[__ptr]]"
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"\n\t" "strex %[__tmp],%[__val],[%[__ptr]]"
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#endif
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"\n\t" "cmp %[__tmp],#0"
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"\n\t" "bne 1b"
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"\n" "2:"
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: [__rv] "=&r" (__rv), [__tmp] "=&r" (__tmp)
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: [__val] "r" (__val), [__ptr] "r" (__ptr) : "cc", "memory");
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return __rv;
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}
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#endif /* !_ARM_ARCH_6 */
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static __inline void
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__arm_membar_producer(void)
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{
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#ifdef _ARM_ARCH_7
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__asm __volatile("dsb" ::: "memory");
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#elif defined(_ARM_ARCH_6)
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__asm __volatile("mcr\tp15,0,%0,c7,c10,4" :: "r"(0) : "memory");
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#endif
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}
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static __inline void
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__arm_membar_consumer(void)
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{
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#ifdef _ARM_ARCH_7
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__asm __volatile("dmb" ::: "memory");
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#elif defined(_ARM_ARCH_6)
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__asm __volatile("mcr\tp15,0,%0,c7,c10,5" :: "r"(0) : "memory");
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#endif
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}
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static __inline void __unused
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__cpu_simple_lock_init(__cpu_simple_lock_t *__alp)
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{
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*__alp = __SIMPLELOCK_UNLOCKED;
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__arm_membar_producer();
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}
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#if !defined(__thumb__) || defined(_ARM_ARCH_T2)
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static __inline void __unused
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__cpu_simple_lock(__cpu_simple_lock_t *__alp)
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{
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#ifdef _ARM_ARCH_6
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__arm_membar_consumer();
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do {
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/* spin */
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} while (__arm_load_exclusive(__alp) != __SIMPLELOCK_UNLOCKED
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|| __arm_store_exclusive(__alp, __SIMPLELOCK_LOCKED));
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__arm_membar_producer();
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#else
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while (__swp(__SIMPLELOCK_LOCKED, __alp) != __SIMPLELOCK_UNLOCKED)
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continue;
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#endif
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}
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#else
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void __cpu_simple_lock(__cpu_simple_lock_t *);
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#endif
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#if !defined(__thumb__) || defined(_ARM_ARCH_T2)
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static __inline int __unused
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__cpu_simple_lock_try(__cpu_simple_lock_t *__alp)
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{
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#ifdef _ARM_ARCH_6
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__arm_membar_consumer();
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do {
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if (__arm_load_exclusive(__alp) != __SIMPLELOCK_UNLOCKED) {
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return 0;
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}
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} while (__arm_store_exclusive(__alp, __SIMPLELOCK_LOCKED));
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__arm_membar_producer();
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return 1;
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#else
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return (__swp(__SIMPLELOCK_LOCKED, __alp) == __SIMPLELOCK_UNLOCKED);
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#endif
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}
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#else
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int __cpu_simple_lock_try(__cpu_simple_lock_t *);
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#endif
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static __inline void __unused
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__cpu_simple_unlock(__cpu_simple_lock_t *__alp)
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{
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#ifdef _ARM_ARCH_8
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if (sizeof(*__alp) == 1) {
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__asm __volatile("stlb\t%0, [%1]"
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:: "r"(__SIMPLELOCK_UNLOCKED), "r"(__alp) : "memory");
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} else {
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__asm __volatile("stl\t%0, [%1]"
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:: "r"(__SIMPLELOCK_UNLOCKED), "r"(__alp) : "memory");
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}
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#else
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__arm_membar_consumer();
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*__alp = __SIMPLELOCK_UNLOCKED;
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__arm_membar_producer();
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#endif
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}
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#endif /* _ARM_LOCK_H_ */
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