b6cbf7203b
This patch imports the unmodified current version of NetBSD libc. The NetBSD includes are in /nbsd_include, while the libc code itself is split between lib/nbsd_libc and common/lib/libc.
299 lines
6.8 KiB
ArmAsm
299 lines
6.8 KiB
ArmAsm
/* $NetBSD: memset.S,v 1.2 2008/02/16 17:37:13 apb Exp $ */
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/*-
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* Copyright (c) 2002 SHIMIZU Ryo. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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#if defined(LIBC_SCCS) && !defined(lint)
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RCSID("$NetBSD: memset.S,v 1.2 2008/02/16 17:37:13 apb Exp $")
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#endif
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#define REG_PTR r0
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#define REG_TMP1 r1
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#ifdef BZERO
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# define REG_C r2
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# define REG_DST r4
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# define REG_LEN r5
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#else
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# define REG_DST0 r3
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# define REG_DST r4
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# define REG_C r5
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# define REG_LEN r6
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#endif
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#ifdef BZERO
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ENTRY(bzero)
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#else
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ENTRY(memset)
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mov REG_DST,REG_DST0 /* for return value */
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#endif
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/* small amount to fill ? */
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mov #28,REG_TMP1
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cmp/hs REG_TMP1,REG_LEN /* if (len >= 28) goto large; */
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bt/s large
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mov #12,REG_TMP1 /* if (len >= 12) goto small; */
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cmp/hs REG_TMP1,REG_LEN
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bt/s small
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#ifdef BZERO
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mov #0,REG_C
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#endif
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/* very little fill (0 ~ 11 bytes) */
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tst REG_LEN,REG_LEN
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add REG_DST,REG_LEN
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bt/s done
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add #1,REG_DST
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/* unroll 4 loops */
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cmp/eq REG_DST,REG_LEN
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1: mov.b REG_C,@-REG_LEN
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bt/s done
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cmp/eq REG_DST,REG_LEN
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mov.b REG_C,@-REG_LEN
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bt/s done
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cmp/eq REG_DST,REG_LEN
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mov.b REG_C,@-REG_LEN
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bt/s done
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cmp/eq REG_DST,REG_LEN
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mov.b REG_C,@-REG_LEN
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bf/s 1b
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cmp/eq REG_DST,REG_LEN
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done:
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#ifdef BZERO
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rts
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nop
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#else
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rts
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mov REG_DST0,r0
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#endif
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small:
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mov REG_DST,r0
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tst #1,r0
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bt/s small_aligned
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mov REG_DST,REG_TMP1
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shll REG_LEN
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mova 1f,r0 /* 1f must be 4bytes aligned! */
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add #16,REG_TMP1 /* REG_TMP1 = dst+16; */
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sub REG_LEN,r0
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jmp @r0
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mov REG_C,r0
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.align 2
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mov.b r0,@(15,REG_TMP1)
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mov.b r0,@(14,REG_TMP1)
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mov.b r0,@(13,REG_TMP1)
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mov.b r0,@(12,REG_TMP1)
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mov.b r0,@(11,REG_TMP1)
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mov.b r0,@(10,REG_TMP1)
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mov.b r0,@(9,REG_TMP1)
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mov.b r0,@(8,REG_TMP1)
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mov.b r0,@(7,REG_TMP1)
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mov.b r0,@(6,REG_TMP1)
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mov.b r0,@(5,REG_TMP1)
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mov.b r0,@(4,REG_TMP1)
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mov.b r0,@(3,REG_TMP1)
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mov.b r0,@(2,REG_TMP1)
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mov.b r0,@(1,REG_TMP1)
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mov.b r0,@REG_TMP1
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mov.b r0,@(15,REG_DST)
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mov.b r0,@(14,REG_DST)
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mov.b r0,@(13,REG_DST)
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mov.b r0,@(12,REG_DST)
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mov.b r0,@(11,REG_DST)
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mov.b r0,@(10,REG_DST)
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mov.b r0,@(9,REG_DST)
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mov.b r0,@(8,REG_DST)
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mov.b r0,@(7,REG_DST)
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mov.b r0,@(6,REG_DST)
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mov.b r0,@(5,REG_DST)
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mov.b r0,@(4,REG_DST)
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mov.b r0,@(3,REG_DST)
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mov.b r0,@(2,REG_DST)
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mov.b r0,@(1,REG_DST)
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#ifdef BZERO
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rts
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1: mov.b r0,@REG_DST
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#else
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mov.b r0,@REG_DST
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1: rts
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mov REG_DST0,r0
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#endif
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/* 2 bytes aligned small fill */
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small_aligned:
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#ifndef BZERO
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extu.b REG_C,REG_TMP1 /* REG_C = ??????xx, REG_TMP1 = ????00xx */
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shll8 REG_C /* REG_C = ????xx00, REG_TMP1 = ????00xx */
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or REG_TMP1,REG_C /* REG_C = ????xxxx */
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#endif
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mov REG_LEN,r0
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tst #1,r0 /* len is aligned? */
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bt/s 1f
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add #-1,r0
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mov.b REG_C,@(r0,REG_DST) /* fill last a byte */
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mov r0,REG_LEN
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1:
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mova 1f,r0 /* 1f must be 4bytes aligned! */
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sub REG_LEN,r0
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jmp @r0
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mov REG_C,r0
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.align 2
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mov.w r0,@(30,REG_DST)
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mov.w r0,@(28,REG_DST)
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mov.w r0,@(26,REG_DST)
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mov.w r0,@(24,REG_DST)
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mov.w r0,@(22,REG_DST)
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mov.w r0,@(20,REG_DST)
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mov.w r0,@(18,REG_DST)
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mov.w r0,@(16,REG_DST)
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mov.w r0,@(14,REG_DST)
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mov.w r0,@(12,REG_DST)
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mov.w r0,@(10,REG_DST)
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mov.w r0,@(8,REG_DST)
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mov.w r0,@(6,REG_DST)
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mov.w r0,@(4,REG_DST)
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mov.w r0,@(2,REG_DST)
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#ifdef BZERO
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rts
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1: mov.w r0,@REG_DST
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#else
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mov.w r0,@REG_DST
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1: rts
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mov REG_DST0,r0
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#endif
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.align 2
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large:
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#ifdef BZERO
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mov #0,REG_C
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#else
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extu.b REG_C,REG_TMP1 /* REG_C = ??????xx, REG_TMP1 = ????00xx */
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shll8 REG_C /* REG_C = ????xx00, REG_TMP1 = ????00xx */
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or REG_C,REG_TMP1 /* REG_C = ????xx00, REG_TMP1 = ????xxxx */
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swap.w REG_TMP1,REG_C /* REG_C = xxxx????, REG_TMP1 = ????xxxx */
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xtrct REG_TMP1,REG_C /* REG_C = xxxxxxxx */
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#endif
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mov #3,REG_TMP1
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tst REG_TMP1,REG_DST
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mov REG_DST,REG_PTR
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bf/s unaligned_dst
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add REG_LEN,REG_PTR /* REG_PTR = dst + len; */
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tst REG_TMP1,REG_LEN
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bf/s unaligned_len
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aligned:
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/* fill 32*n bytes */
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mov #32,REG_TMP1
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cmp/hi REG_LEN,REG_TMP1
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bt 9f
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.align 2
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1: sub REG_TMP1,REG_PTR
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mov.l REG_C,@REG_PTR
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sub REG_TMP1,REG_LEN
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mov.l REG_C,@(4,REG_PTR)
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cmp/hi REG_LEN,REG_TMP1
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mov.l REG_C,@(8,REG_PTR)
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mov.l REG_C,@(12,REG_PTR)
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mov.l REG_C,@(16,REG_PTR)
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mov.l REG_C,@(20,REG_PTR)
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mov.l REG_C,@(24,REG_PTR)
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bf/s 1b
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mov.l REG_C,@(28,REG_PTR)
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9:
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/* fill left 4*n bytes */
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cmp/eq REG_DST,REG_PTR
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bt 9f
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add #4,REG_DST
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cmp/eq REG_DST,REG_PTR
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1: mov.l REG_C,@-REG_PTR
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bt/s 9f
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cmp/eq REG_DST,REG_PTR
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mov.l REG_C,@-REG_PTR
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bt/s 9f
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cmp/eq REG_DST,REG_PTR
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mov.l REG_C,@-REG_PTR
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bt/s 9f
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cmp/eq REG_DST,REG_PTR
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mov.l REG_C,@-REG_PTR
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bf/s 1b
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cmp/eq REG_DST,REG_PTR
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9:
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#ifdef BZERO
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rts
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nop
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#else
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rts
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mov REG_DST0,r0
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#endif
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unaligned_dst:
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mov #1,REG_TMP1
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tst REG_TMP1,REG_DST /* if (dst & 1) { */
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add #1,REG_TMP1
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bt/s 2f
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tst REG_TMP1,REG_DST
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mov.b REG_C,@REG_DST /* *dst++ = c; */
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add #1,REG_DST
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tst REG_TMP1,REG_DST
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2: /* } */
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/* if (dst & 2) { */
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bt 4f
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mov.w REG_C,@REG_DST /* *(uint16_t*)dst++ = c; */
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add #2,REG_DST
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4: /* } */
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tst #3,REG_PTR /* if (ptr & 3) { */
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bt/s 4f /* */
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unaligned_len:
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tst #1,REG_PTR /* if (ptr & 1) { */
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bt/s 2f
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tst #2,REG_PTR
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mov.b REG_C,@-REG_PTR /* --ptr = c; */
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2: /* } */
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/* if (ptr & 2) { */
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bt 4f
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mov.w REG_C,@-REG_PTR /* *--(uint16_t*)ptr = c; */
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4: /* } */
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/* } */
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mov REG_PTR,REG_LEN
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bra aligned
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sub REG_DST,REG_LEN
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