b6cbf7203b
This patch imports the unmodified current version of NetBSD libc. The NetBSD includes are in /nbsd_include, while the libc code itself is split between lib/nbsd_libc and common/lib/libc.
197 lines
5.4 KiB
ArmAsm
197 lines
5.4 KiB
ArmAsm
/* $NetBSD: memset.S,v 1.4 2001/08/02 01:17:28 eeh Exp $ */
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/*
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* Copyright (c) 2001, Eduardo E. Horvath
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Header: bzero.s,v 1.1 92/06/25 12:52:46 torek Exp
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*/
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#include <machine/asm.h>
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#ifndef _LOCORE
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#define _LOCORE
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#endif
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#include <machine/ctlreg.h>
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#include <machine/frame.h>
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#include <machine/psl.h>
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#if defined(LIBC_SCCS) && !defined(lint)
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RCSID("$NetBSD: memset.S,v 1.4 2001/08/02 01:17:28 eeh Exp $")
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#endif /* LIBC_SCCS and not lint */
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/*
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* bzero(addr, len)
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*
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* We want to use VIS instructions if we're clearing out more than
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* 256 bytes, but to do that we need to properly save and restore the
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* FP registers. Unfortunately the code to do that in the kernel needs
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* to keep track of the current owner of the FPU, hence the different
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* code.
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*
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* XXXXX To produce more efficient code, we do not allow lengths
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* greater than 0x80000000000000000, which are negative numbers.
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* This should not really be an issue since the VA hole should
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* cause any such ranges to fail anyway.
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*/
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ENTRY(bzero)
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! %o0 = addr, %o1 = len
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mov %o1, %o2
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clr %o1 ! Initialize our pattern
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/*
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* memset(addr, c, len)
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*
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*/
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ENTRY(memset)
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! %o0 = addr, %o1 = pattern, %o2 = len
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mov %o0, %o4 ! Save original pointer
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Lbzero_internal:
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btst 7, %o0 ! Word aligned?
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bz,pn %xcc, 0f
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nop
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inc %o0
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deccc %o2 ! Store up to 7 bytes
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bge,a,pt %xcc, Lbzero_internal
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stb %o1, [%o0 - 1]
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retl ! Duplicate Lbzero_done
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mov %o4, %o0
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0:
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/*
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* Duplicate the pattern so it fills 64-bits.
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*/
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andcc %o1, 0x0ff, %o1 ! No need to extend zero
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bz,pt %icc, 1f
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sllx %o1, 8, %o3 ! sigh. all dependent insns.
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or %o1, %o3, %o1
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sllx %o1, 16, %o3
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or %o1, %o3, %o1
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sllx %o1, 32, %o3
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or %o1, %o3, %o1
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1:
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#if 1
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!! Now we are 64-bit aligned
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cmp %o2, 256 ! Use block clear if len > 256
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bge,pt %xcc, Lbzero_block ! use block store insns
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#endif
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deccc 8, %o2
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Lbzero_longs:
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bl,pn %xcc, Lbzero_cleanup ! Less than 8 bytes left
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nop
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3:
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inc 8, %o0
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deccc 8, %o2
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bge,pt %xcc, 3b
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stx %o1, [%o0 - 8] ! Do 1 longword at a time
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/*
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* Len is in [-8..-1] where -8 => done, -7 => 1 byte to zero,
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* -6 => two bytes, etc. Mop up this remainder, if any.
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*/
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Lbzero_cleanup:
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btst 4, %o2
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bz,pt %xcc, 5f ! if (len & 4) {
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nop
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stw %o1, [%o0] ! *(int *)addr = 0;
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inc 4, %o0 ! addr += 4;
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5:
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btst 2, %o2
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bz,pt %xcc, 7f ! if (len & 2) {
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nop
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sth %o1, [%o0] ! *(short *)addr = 0;
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inc 2, %o0 ! addr += 2;
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7:
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btst 1, %o2
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bnz,a %icc, Lbzero_done ! if (len & 1)
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stb %o1, [%o0] ! *addr = 0;
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Lbzero_done:
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retl
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mov %o4, %o0 ! Restore ponter for memset (ugh)
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#if 1
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Lbzero_block:
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/*
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* Userland:
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*
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* Floating point registers are volatile. What luck.
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*
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* See locore.s for the kernel version.
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*
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*/
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! wr %g0, FPRS_FEF, %fprs ! Enable FPU
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!! We are now 8-byte aligned. We need to become 64-byte aligned.
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btst 63, %o0
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bz,pt %xcc, 2f
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nop
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1:
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stx %o1, [%o0]
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inc 8, %o0
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btst 63, %o0
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bnz,pt %xcc, 1b
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dec 8, %o2
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2:
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brz %o1, 3f ! Skip the memory op
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fzero %f0 ! for bzero
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stx %o1, [%o0] ! Flush this puppy to RAM
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membar #StoreLoad
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ldd [%o0], %f0
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3:
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fmovd %f0, %f2 ! Duplicate the pattern
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fmovd %f0, %f4
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fmovd %f0, %f6
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fmovd %f0, %f8
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fmovd %f0, %f10
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fmovd %f0, %f12
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fmovd %f0, %f14
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!! Remember: we were 8 bytes too far
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dec 56, %o2 ! Go one iteration too far
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5:
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stda %f0, [%o0] ASI_BLK_P ! Store 64 bytes
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deccc 64, %o2
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bg,pn %xcc, 5b
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inc 64, %o0
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membar #Sync
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/*
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* Now we're done we need to load the FPU state from where
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* we put it.
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*/
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ba,pt %xcc, Lbzero_longs ! Finish up the remainder
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inccc 56, %o2 ! Restore the count
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#endif
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