1cd76c7513
. primary purpose is to synchronize with <ieeefp.h> which expects a fp_prec from sys/arch/x86/include/ieeefp.h
132 lines
3.8 KiB
C
132 lines
3.8 KiB
C
/* $NetBSD: cpufunc.h,v 1.13 2011/09/24 10:32:52 jym Exp $ */
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/*-
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* Copyright (c) 1998, 2007 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum, and by Andrew Doran.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _X86_CPUFUNC_H_
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#define _X86_CPUFUNC_H_
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/*
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* Functions to provide access to x86-specific instructions.
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*/
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#include <sys/cdefs.h>
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#include <sys/types.h>
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#include <machine/segments.h>
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#include <machine/specialreg.h>
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#ifdef _KERNEL
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void x86_pause(void);
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void x86_lfence(void);
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void x86_sfence(void);
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void x86_mfence(void);
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void x86_flush(void);
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#ifndef XEN
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void x86_patch(bool);
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#endif
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void invlpg(vaddr_t);
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void lidt(struct region_descriptor *);
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void lldt(u_short);
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void ltr(u_short);
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void lcr0(u_long);
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u_long rcr0(void);
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void lcr2(vaddr_t);
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vaddr_t rcr2(void);
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void lcr3(vaddr_t);
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vaddr_t rcr3(void);
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void lcr4(vaddr_t);
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vaddr_t rcr4(void);
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void lcr8(vaddr_t);
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vaddr_t rcr8(void);
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void tlbflush(void);
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void tlbflushg(void);
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void dr0(void *, uint32_t, uint32_t, uint32_t);
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vaddr_t rdr6(void);
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void ldr6(vaddr_t);
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void wbinvd(void);
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void breakpoint(void);
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void x86_hlt(void);
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void x86_stihlt(void);
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u_int x86_getss(void);
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void fldcw(void *);
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void fnclex(void);
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void fninit(void);
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void fnsave(void *);
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void fnstcw(void *);
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void fnstsw(void *);
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void fp_divide_by_0(void);
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void frstor(void *);
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void fwait(void);
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void clts(void);
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void stts(void);
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void fldummy(const double *);
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void fxsave(void *);
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void fxrstor(void *);
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void x86_monitor(const void *, uint32_t, uint32_t);
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void x86_mwait(uint32_t, uint32_t);
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void x86_ldmxcsr(void *);
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#define x86_cpuid(a,b) x86_cpuid2((a),0,(b))
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void x86_cpuid2(unsigned, unsigned, unsigned *);
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/* Use read_psl, write_psl when saving and restoring interrupt state. */
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void x86_disable_intr(void);
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void x86_enable_intr(void);
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u_long x86_read_psl(void);
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void x86_write_psl(u_long);
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/* Use read_flags, write_flags to adjust other members of %eflags. */
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u_long x86_read_flags(void);
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void x86_write_flags(u_long);
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void x86_reset(void);
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/*
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* Some of the undocumented AMD64 MSRs need a 'passcode' to access.
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*
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* See LinuxBIOSv2: src/cpu/amd/model_fxx/model_fxx_init.c
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*/
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#define OPTERON_MSR_PASSCODE 0x9c5a203aU
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uint64_t rdmsr(u_int);
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uint64_t rdmsr_locked(u_int, u_int);
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int rdmsr_safe(u_int, uint64_t *);
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uint64_t rdtsc(void);
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uint64_t rdpmc(u_int);
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void wrmsr(u_int, uint64_t);
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void wrmsr_locked(u_int, u_int, uint64_t);
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void setfs(int);
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void setusergs(int);
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#endif /* _KERNEL */
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#endif /* !_X86_CPUFUNC_H_ */
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