 f65b3b8fbf
			
		
	
	
		f65b3b8fbf
		
	
	
	
	
		
			
			interrupts to avoid clobbering register B. This seems to have fixed the corrupting-CMOS bug when enabling profiling.
		
			
				
	
	
		
			103 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			103 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* system dependent functions for use inside the whole kernel. */
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| 
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| #include "../../kernel.h"
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| 
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| #include <unistd.h>
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| #include <ibm/cmos.h>
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| #include <ibm/bios.h>
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| #include <minix/portio.h>
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| 
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| #include "proto.h"
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| 
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| PUBLIC void arch_shutdown(int how)
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| {
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| 	/* Mask all interrupts, including the clock. */
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| 	outb( INT_CTLMASK, ~0);
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| 
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| 	if(how != RBT_RESET) {
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| 		/* return to boot monitor */
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| 
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| 		outb( INT_CTLMASK, 0);            
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| 		outb( INT2_CTLMASK, 0);
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|         
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| 		/* Return to the boot monitor. Set
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| 		 * the program if not already done.
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| 		 */
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| 		if (how != RBT_MONITOR)
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| 			phys_copy(vir2phys(""), kinfo.params_base, 1);
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| 		level0(monitor);
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| 	} else {
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| 		/* Reset the system by forcing a processor shutdown. First stop
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| 		 * the BIOS memory test by setting a soft reset flag.
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| 		 */
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| 		u16_t magic = STOP_MEM_CHECK;
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| 		phys_copy(vir2phys(&magic), SOFT_RESET_FLAG_ADDR,
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|        	 	SOFT_RESET_FLAG_SIZE);
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| 		level0(reset);
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| 	}
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| }
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| 
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| PUBLIC void system_init(void)
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| {
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| 	prot_init();
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| }
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| 
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| #define COM1_BASE       0x3F8
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| #define COM1_THR        (COM1_BASE + 0)
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| #define   LSR_THRE      0x20
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| #define COM1_LSR        (COM1_BASE + 5)
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| 
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| PUBLIC void ser_putc(char c)
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| {
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|         int i;
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|         int lsr, thr;
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| 
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|         lsr= COM1_LSR;
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|         thr= COM1_THR;
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|         for (i= 0; i<100000; i++)
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|         {
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|                 if (inb( lsr) & LSR_THRE)
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|                         break;
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|         }
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|         outb( thr, c);
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| }
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| 
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| #if SPROFILE
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| 
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| PUBLIC int arch_init_profile_clock(u32_t freq)
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| {
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|   int r;
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|   /* Set CMOS timer frequency. */
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|   outb(RTC_INDEX, RTC_REG_A);
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|   outb(RTC_IO, RTC_A_DV_OK | freq);
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|   /* Enable CMOS timer interrupts. */
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|   outb(RTC_INDEX, RTC_REG_B);
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|   r = inb(RTC_IO);
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|   outb(RTC_INDEX, RTC_REG_B); 
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|   outb(RTC_IO, r | RTC_B_PIE);
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|   /* Mandatory read of CMOS register to enable timer interrupts. */
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|   outb(RTC_INDEX, RTC_REG_C);
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|   inb(RTC_IO);
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| 
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|   return CMOS_CLOCK_IRQ;
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| }
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| 
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| PUBLIC void arch_stop_profile_clock(void)
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| {
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|   int r;
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|   /* Disable CMOS timer interrupts. */
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|   outb(RTC_INDEX, RTC_REG_B);
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|   r = inb(RTC_IO);
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|   outb(RTC_INDEX, RTC_REG_B);  
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|   outb(RTC_IO, r & ~RTC_B_PIE);
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| }
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| 
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| PUBLIC void arch_ack_profile_clock(void)
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| {
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|   /* Mandatory read of CMOS register to re-enable timer interrupts. */
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|   outb(RTC_INDEX, RTC_REG_C);
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|   inb(RTC_IO);
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| }
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| 
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| #endif
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